diff options
| author | Albert Magyar | 2020-04-14 14:27:07 -0700 |
|---|---|---|
| committer | Albert Magyar | 2020-07-27 08:50:09 -0700 |
| commit | 9ab58c1efb503aec00c22dbd70434038ec87dcab (patch) | |
| tree | 142f382b48dbda695a78f97d11eeef0dcb4e79e3 | |
| parent | 3fcfbf363e7e04c759f0523d8c4a43427ccdf4a9 (diff) | |
Update RightShiftTests.fir to avoid buggy Counter pattern
* See freechipsproject/chisel3#1408
| -rw-r--r-- | test/integration/RightShiftTester.fir | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/integration/RightShiftTester.fir b/test/integration/RightShiftTester.fir index f15a1239..d85757b8 100644 --- a/test/integration/RightShiftTester.fir +++ b/test/integration/RightShiftTester.fir @@ -37,8 +37,8 @@ circuit RightShiftTester : dut.clock <= clock dut.reset <= reset reg T_6 : UInt<2>, clock with : (reset => (reset, UInt<2>("h00"))) + node T_8 = eq(T_6, UInt<2>("h03")) when UInt<1>("h01") : - node T_8 = eq(T_6, UInt<2>("h03")) node T_10 = and(UInt<1>("h00"), T_8) node T_13 = add(T_6, UInt<1>("h01")) node T_14 = tail(T_13, 1) |