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| author | Kevin Laeufer | 2020-07-29 14:35:36 -0700 |
|---|---|---|
| committer | GitHub | 2020-07-29 21:35:36 +0000 |
| commit | 3a6e352626915751b2b2a5d6aec4203fb8e83a1d (patch) | |
| tree | 02d2333f81d995785f21d173744aab7d7b05a664 | |
| parent | 734e3e462ce74178147d5d6b0b6bdc5557f41103 (diff) | |
RemoveWires: improve dependencies and declare ResolveKinds as an invalidation (#1797)
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
| -rw-r--r-- | src/main/scala/firrtl/transforms/RemoveWires.scala | 16 | ||||
| -rw-r--r-- | src/test/scala/firrtlTests/LoweringCompilersSpec.scala | 6 |
2 files changed, 12 insertions, 10 deletions
diff --git a/src/main/scala/firrtl/transforms/RemoveWires.scala b/src/main/scala/firrtl/transforms/RemoveWires.scala index 33daa8ce..0e70ec1f 100644 --- a/src/main/scala/firrtl/transforms/RemoveWires.scala +++ b/src/main/scala/firrtl/transforms/RemoveWires.scala @@ -25,6 +25,7 @@ class RemoveWires extends Transform with DependencyAPIMigration { override def prerequisites = firrtl.stage.Forms.MidForm ++ Seq( Dependency(passes.LowerTypes), Dependency(passes.Legalize), + Dependency(passes.ResolveKinds), Dependency(transforms.RemoveReset), Dependency[transforms.CheckCombLoops] ) @@ -32,7 +33,10 @@ class RemoveWires extends Transform with DependencyAPIMigration { override def optionalPrerequisiteOf = Seq.empty - override def invalidates(a: Transform) = false + override def invalidates(a: Transform) = a match { + case passes.ResolveKinds => true + case _ => false + } // Extract all expressions that are references to a Node, Wire, or Reg // Since we are operating on LowForm, they can only be WRefs @@ -151,13 +155,7 @@ class RemoveWires extends Transform with DependencyAPIMigration { } } - /* @todo move ResolveKinds outside */ - private val cleanup = Seq( - passes.ResolveKinds - ) - def execute(state: CircuitState): CircuitState = { - val result = state.copy(circuit = state.circuit.map(onModule)) - cleanup.foldLeft(result) { case (in, xform) => xform.execute(in) } - } + def execute(state: CircuitState): CircuitState = + state.copy(circuit = state.circuit.map(onModule)) } diff --git a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala index ae546f7b..024f86a7 100644 --- a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala +++ b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala @@ -189,7 +189,11 @@ class LoweringCompilersSpec extends FlatSpec with Matchers { it should "replicate the old order" in { val tm = new TransformManager(Forms.LowForm, Forms.MidForm) - compare(legacyTransforms(new MiddleFirrtlToLowFirrtl), tm) + val patches = Seq( + // RemoveWires now visibly invalidates ResolveKinds + Add(11, Seq(Dependency(firrtl.passes.ResolveKinds))) + ) + compare(legacyTransforms(new MiddleFirrtlToLowFirrtl), tm, patches) } behavior of "MinimumLowFirrtlOptimization" |
