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2016-01-16Ignore eclipse .projectducky
2016-01-16Import a logging library so we don't reinvent the wheel and have implicits ↵ducky
flying around everywhere
2016-01-16Refactor passes systemducky
2016-01-16Default platform-agnostic, ignore platform-specific FileCheckducky
2016-01-16Update README with better Linux and Scala instructionsducky
2016-01-16Added notes for Richard to work onazidar
2016-01-16Merge branch 'new-mem' of github.com:ucb-bar/firrtl into scala-new-memazidar
2016-01-16Added a bunch of tests and added firrtl-stanza and firrtl-scala to .gitignoreazidar
2016-01-16Standard Verilog doesn't use Resolve(), but lists out the resolution passes ↵azidar
individually
2016-01-16Merge branch 'new-mem' of github.com:ucb-bar/firrtl into scala-new-memazidar
2016-01-16Fixed all tests so they either pass are marked as expected failuresazidar
2016-01-16Added notes for Richard to work onazidar
2016-01-16Updated passes so they test new-memazidar
2016-01-16Fixed a testazidar
2016-01-16Fixed bug in lowering memories that had aggregate data typesazidar
2016-01-16Fixed bug in check-init that allows it to check on non-lowered thingsazidar
2016-01-16Moved back to create-exps instead of fast-create-exps to fix bug - ↵azidar
fast-create-exps still needs debugging
2016-01-16Nodes must now be ground typesazidar
2016-01-16Fixed up minor errors after rebase onto masterazidar
2016-01-16Fixed Vector performance testsazidar
2016-01-16Reworked Verilog emission of registers to if/else instead of ?:azidar
2016-01-16No longer split on muxesazidar
2016-01-16Commented back in Starting and Finishing for testingazidar
2016-01-16Sped up remove access by checking a conditionazidar
2016-01-16Added more data in printout of time to compileazidar
2016-01-16printf no longer includes a new lineazidar
2016-01-16Verilog emission no longer casts input to shr or bit selectazidar
2016-01-16Added hashed on get flipazidar
2016-01-16Sped up some passes. Added global mname to allow easy per-module hashes for ↵azidar
accellerating functions
2016-01-16Made create-exps a bit fasterazidar
2016-01-16Finished first cut at new firrtl - time for testing! Chirrtl requires masks ↵azidar
to be specified with write and rdwr mports
2016-01-16Fixed a bunch of tests, and minor bugsazidar
2016-01-16Added src and test filesazidar
2016-01-16WIP adding chirrtlazidar
2016-01-16WIP Almost there, need to generate enable connectionsazidar
2016-01-16WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit ↵azidar
roadblock in assigning clocked ports
2016-01-16WIP getting through testsazidar
2016-01-16Finished supporting nested accesses. Required some nuianced thinking. Pass ↵azidar
all feature tests. Deleted CondRead because it tested a problem we don't have any more
2016-01-16WIP, hit semantic bug in WSubAccessazidar
2016-01-16New memory works with verilog. Slowly changing tests and fixing bugs.azidar
Decided to not have Conditionally in low firrtl - instead, Print and Stop have enables
2016-01-16WIP. Compiles and almost done with verilog backend. Need to think about ↵azidar
emitting ports (and the assignments to them)
2016-01-16WIP. Compiles and there's some outputazidar
2016-01-16WIP. Compiles, need to testazidar
2016-01-16WIPazidar
2016-01-16Added memory thoughtsazidar
2016-01-16WIP need to correctly output readwrite portsazidar
2016-01-16Merge branch 'scala' of github.com:ucb-bar/firrtlazidar
2016-01-16Added some commentsazidar
2016-01-16Added performance testsazidar
2016-01-16Printf no longer adds a new lineazidar
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