Finished first cut at new firrtl - time for testing! Chirrtl requires masks to be specified with write and rdwr mports

8 files changed, 68 insertions, 42 deletions

diff --git a/spec/spec.pdf b/spec/spec.pdf
index ffbfc056..d13c9f96 100644
--- a/spec/spec.pdf
+++ b/spec/spec.pdf
diff --git a/spec/spec.tex b/spec/spec.tex
index 09fed6b7..570531b6 100644
--- a/spec/spec.tex
+++ b/spec/spec.tex
@@ -84,10 +84,10 @@ After a custom pass, the resulting circuit should undergo lowering prior to pass
 The FIRRTL language could not have been developed without the help of many of the faculty and students in the ASPIRE lab, including but not limited to XXXX.
 We'd also like to thank our sponsors XXXX, and the University of California, Berkeley.
 
-\section{FIRRTL Language Definition}
+%\section{FIRRTL Language Definition}
 
-\subsection{Abstract Syntax Tree}
-{ \fontsize{11pt}{1.15em}\selectfont
+%\subsection{Abstract Syntax Tree}
+{ \fontsize{10pt}{1.10em}\selectfont
 \[
 \begin{array}{rrll}
 \pd{circuit}    &=     &\kw{circuit} \id \kw{:} (\pd{module*})                                        &\text{Circuit}\\
@@ -104,36 +104,47 @@ We'd also like to thank our sponsors XXXX, and the University of California, Ber
 \pd{orientation}&=     &\kws{default} \vert \kws{reverse}                                             &\text{Orientation}\\
 \pd{width}      &=     &\ints \vert \kw{?}                                                            &\text{Known/Unknown Integer Width}\\
 \pd{stmt}       &=     &\info \kw{wire} \id \kw{:} \pd{type}                                          &\text{Wire Declaration}\\
-                &\vert &\info \kw{reg} \id \kw{:}  \pds{type} , \pds{exp} , \pds{exp}                 &\text{Register Declaration}\\
-                &\vert &\info \kw{smem} \id \kw{:} \pds{type} , \ints                                 &\text{Sequential Memory Declaration}\\
-                &\vert &\info \kw{cmem} \id \kw{:} \pds{type} , \ints                                 &\text{Combinational Memory Declaration}\\
+                &\vert &\info \kw{reg} \id \kw{:}  \pds{type} , \pds{exp} , \pds{exp} , \pds{exp}     &\text{Register Declaration}\\
+                &\vert &\info \kw{mem} \id \kw{:} \pds{type} , \pds{mstat*}                           &\text{Memory Declaration}\\
                 &\vert &\info \kw{inst} \id \kw{:} \id                                                &\text{Instance Declaration}\\
-                &\vert &\info \kw{poison} \id \kw{:} \id                                              &\text{Poison Declaration}\\
+                &\vert &\info \kw{poison} \id \kw{:} \pds{type}                                              &\text{Poison Declaration}\\
                 &\vert &\info \kw{node} \id  = \pd{exp}                                               &\text{Node Declaration}\\
-                &\vert &\info \pd{dir} \kw{accessor} \id = \pds{exp}[\pds{exp}] , \pds{exp}           &\text{Accessor Declaration}\\
                 &\vert &\info \pd{exp} \kw{$<$=} \pd{exp}                                             &\text{Connect}\\
-                &\vert &\info \kw{onreset} \pd{exp} \kw{$<$=} \pd{exp}                                &\text{OnReset Connect}\\
-                &\vert &\info \pd{exp} \kw{$<$--} \pd{exp}                                             &\text{Partial Connect}\\
+                &\vert &\info \pd{exp} \kw{$<$--} \pd{exp}                                            &\text{Partial Connect}\\
                 &\vert &\info \kw{when} \pd{exp} \kw{:} \pd{stmt} \kw{else :} \pd{stmt}               &\text{Conditional}\\
-                &\vert &\info \kw{stop}                                                               &\text{Stop Statement}\\
-                &\vert &\info \kw{printf}(\strings,\pds{exp*})                                        &\text{Printf Statement}\\
+                &\vert &\info \kw{stop}(\pds{exp},\pds{exp},\ints)                                    &\text{Stop Statement}\\
+                &\vert &\info \kw{printf}(\pds{exp},\pds{exp},\strings,\pds{exp*})                    &\text{Printf Statement}\\
                 &\vert &\info \kw{skip}                                                               &\text{Empty Statement}\\
                 &\vert &\info (\pd{stmt*})                                                            &\text{Statement Group}\\
-\pd{dir}        &=     &\kws{infer} \vert \kws{read} \vert \kws{write} \vert \kw{rdwr}                &\text{Accessor Direction}\\
 \pd{exp}        &=     &\info \kws{UInt} \kws{$<$} \pds{width} \kws{$>$}(\ints)                       &\text{Literal Unsigned Integer}\\
                 &\vert &\info \kws{SInt} \kws{$<$} \pds{width} \kws{$>$}(\ints)                       &\text{Literal Signed Integer}\\
                 &\vert &\info \id                                                                     &\text{Reference}\\
                 &\vert &\info \pds{exp}.\id                                                           &\text{Subfield}\\
                 &\vert &\info \pds{exp}[\ints]                                                        &\text{Subindex}\\
+                &\vert &\info \pds{exp}[\pds{exp}]                                                    &\text{Subaccess}\\
                 &\vert &\info \pds{primop}(\pds{exp*}, \ints\text{*})                                 &\text{Primitive Operation}\\
 \pd{info}       &=     &\text{filename } \kw{:} \text{line} . \text{col}                              &\text{File Location}\\
                 &\vert &\kw{noinfo}                                                                   &\text{No File Location}\\
+                \pd{mstat}      &=     &\kw{writer =$>$} \id                                                          &\text{Write Port Name}\\
+                &\vert &\kw{reader =$>$} \id                                                          &\text{Read Port Name}\\
+                &\vert &\kw{read-writer =$>$} \id                                                     &\text{ReadWrite Port Name}\\
+                &\vert &\kw{read-latency =$>$} \ints                                                  &\text{Read Latency}\\
+                &\vert &\kw{write-latency =$>$} \ints                                                 &\text{Write Latency}\\
+                &\vert &\kw{data-type =$>$} \pds{type}                                                &\text{Memory Data Type}\\
+                &\vert &\kw{depth =$>$} \ints                                                         &\text{Memory Depth}\\
 \end{array}
 \]
 }
 \[
-{ \fontsize{11pt}{1.15em}\selectfont
+{ \fontsize{10pt}{1.07em}\selectfont
 \begin{array}{rrll}
+\pd{mstat}      &=     &\kw{writer =$>$} \id                                                          &\text{Write Port Name}\\
+                &\vert &\kw{reader =$>$} \id                                                          &\text{Read Port Name}\\
+                &\vert &\kw{read-writer =$>$} \id                                                     &\text{ReadWrite Port Name}\\
+                &\vert &\kw{read-latency =$>$} \ints                                                  &\text{Read Latency}\\
+                &\vert &\kw{write-latency =$>$} \ints                                                 &\text{Write Latency}\\
+                &\vert &\kw{data-type =$>$} \pds{type}                                                &\text{Memory Data Type}\\
+                &\vert &\kw{depth =$>$} \ints                                                         &\text{Memory Depth}\\
 \pd{primop}   &=               &\kws{add}            &\text{Unsigned/Signed Add}\\
               &\vert           &\kws{sub}            &\text{Unsigned/Signed Subtract}\\
               &\vert           &\kws{addw}           &\text{Unsigned/Signed Add Wrap}\\
diff --git a/src/main/stanza/chirrtl.stanza b/src/main/stanza/chirrtl.stanza
index 06f1a61d..83a9e853 100644
--- a/src/main/stanza/chirrtl.stanza
+++ b/src/main/stanza/chirrtl.stanza
@@ -58,19 +58,20 @@ defn to-ir (c:Circuit) :
          match(s) :
             (s:CDefMemory) :
                val stmts = Vector<Stmt>()
-               val n = firrtl-gensym(`GEN,sh)
-               val t = UIntType(IntWidth(ceil-log2(size(s))))
-               add(stmts,DefPoison(info(s),n,t))
+               val naddr = firrtl-gensym(`GEN,sh)
+               val taddr = UIntType(IntWidth(ceil-log2(size(s))))
+               add(stmts,DefPoison(info(s),naddr,taddr))
+               val ndata = firrtl-gensym(`GEN,sh)
+               val tdata = type(s)
+               add(stmts,DefPoison(info(s),ndata,tdata))
                defn set-poison (vec:List<MPort>,addr:Symbol) -> False :
                   for r in vec do :
-                     add(stmts,Connect(info(s),SubField(SubField(Ref(name(s),ut),name(r),ut),addr,t),Ref(n,t)))
-                     add(stmts,Connect(info(s),SubField(SubField(Ref(name(s),ut),name(r),ut),`clk,t),clk(r)))
-                     add(stmts,Connect(info(s),SubField(SubField(Ref(name(s),ut),name(r),ut),`en,t),zero))
-                        
+                     add(stmts,Connect(info(s),SubField(SubField(Ref(name(s),ut),name(r),ut),addr,taddr),Ref(naddr,taddr)))
+                     add(stmts,Connect(info(s),SubField(SubField(Ref(name(s),ut),name(r),ut),`clk,taddr),clk(r)))
+               defn set-enable (vec:List<MPort>,en:Symbol) -> False:
+                  for r in vec do :
+                     add(stmts,Connect(info(s),SubField(SubField(Ref(name(s),ut),name(r),ut),en,taddr),zero))
                defn set-write (vec:List<MPort>,data:Symbol,mask:Symbol) -> False :
-                  val ndata = firrtl-gensym(`GEN,sh)
-                  val tdata = type(s)
-                  add(stmts,DefPoison(info(s),ndata,tdata))
                   val tmask = type(create-mask(`blah,type(s)))
                   for r in vec do :
                      add(stmts,Connect(info(s),SubField(SubField(Ref(name(s),ut),name(r),ut),data,tdata),Ref(ndata,tdata)))
@@ -79,12 +80,16 @@ defn to-ir (c:Circuit) :
                         
                val rds = to-list $ readers $ get?(hash,name(s),EMPs())
                set-poison(rds,`addr)
+               set-enable(rds,`en)
                val wrs = to-list $ writers $ get?(hash,name(s),EMPs())
                set-poison(wrs,`addr)
+               set-enable(wrs,`en)
                set-write(wrs,`data,`mask)
                val rws = to-list $ readwriters $ get?(hash,name(s),EMPs())
                set-poison(rws,`waddr)
                set-poison(rws,`raddr)
+               set-enable(rws,`wen)
+               set-enable(rws,`ren)
                set-write(rws,`wdata,`wmask)
                val read-l = 
                   if seq?(s) : 1
@@ -101,15 +106,24 @@ defn to-ir (c:Circuit) :
                      add(addrs,`addr)
                      add(ens,`wen)
                      add(ens,`ren)
+                     add(masks,`wmask)
+                  MWrite :
+                     repl[name(s)] = DataRef(SubField(Ref(mem(s),ut),name(s),ut),`data,`data)
+                     add(addrs,`addr)
+                     add(ens,`en)
+                     add(masks,`mask)
                   else : ; TODO add MWrite for mask
                      repl[name(s)] = DataRef(SubField(Ref(mem(s),ut),name(s),ut),`data,`data)
                      add(addrs,`addr)
                      add(ens,`en)
+
                val stmts = Vector<Stmt>()
                for x in addrs do :
                   add(stmts,Connect(info(s),SubField(SubField(Ref(mem(s),ut),name(s),ut),x,ut),exps(s)[0]))
                for x in ens do :
                   add(stmts,Connect(info(s),SubField(SubField(Ref(mem(s),ut),name(s),ut),x,ut),one))
+               for x in masks do :
+                  add(stmts,Connect(info(s),SubField(SubField(Ref(mem(s),ut),name(s),ut),x,ut),exps(s)[2]))
                Begin $ to-list $ stmts   
             (s) : map(collect-refs,s)
       defn to-ir-e (e:Expression,g:Gender) -> Expression :
diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza
index d891227f..fa103fe3 100644
--- a/src/main/stanza/ir-parser.stanza
+++ b/src/main/stanza/ir-parser.stanza
@@ -265,10 +265,10 @@ defsyntax firrtl :
 
       stmt = (read mport ?name:#id! #=! ?mem:#id! (@get ?index:#exp!) ?clk:#exp!) :
          CDefMPort(first-info(form),name,mem,list(index,clk),MRead)
-      stmt = (write mport ?name:#id! #=! ?mem:#id! (@get ?index:#exp!) ?clk:#exp!) :
-         CDefMPort(first-info(form),name,mem,list(index,clk),MWrite)
-      stmt = (rdwr mport ?name:#id! #=! ?mem:#id! (@get ?index:#exp!) ?clk:#exp!) :
-         CDefMPort(first-info(form),name,mem,list(index,clk),MReadWrite)
+      stmt = (write mport ?name:#id! #=! ?mem:#id! (@get ?index:#exp!) ?clk:#exp! ?mask:#exp!) :
+         CDefMPort(first-info(form),name,mem,list(index,clk,mask),MWrite)
+      stmt = (rdwr mport ?name:#id! #=! ?mem:#id! (@get ?index:#exp!) ?clk:#exp! ?mask:#exp!) :
+         CDefMPort(first-info(form),name,mem,list(index,clk,mask),MReadWrite)
 
       stmt = (mem ?name:#id! #:! (?ms:#mstat ...)) :
          defn grab (f:MStat -> True|False) :
diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza
index a2af082b..00b573a6 100644
--- a/src/main/stanza/ir-utils.stanza
+++ b/src/main/stanza/ir-utils.stanza
@@ -345,7 +345,10 @@ defmethod print (o:OutputStream, c:Stmt) :
          else :
             print-all(o, ["cmem " name(c) " : " type(c) "[" size(c) "]"])
       (c:CDefMPort) :
-         print-all(o, [direction(c) " mport " name(c) " = " mem(c) "[" exps(c)[0] "], " exps(c)[1]])
+         if direction(c) == MRead : 
+            print-all(o, [direction(c) " mport " name(c) " = " mem(c) "[" exps(c)[0] "], " exps(c)[1]])
+         else : 
+            print-all(o, [direction(c) " mport " name(c) " = " mem(c) "[" exps(c)[0] "], " exps(c)[1] ", " exps(c)[2]])
 
    if not c typeof Conditionally|Begin|Empty: print-debug(o,c)
 
diff --git a/test/passes/jacktest/Stack.fir b/test/passes/jacktest/Stack.fir
index 9b35c3f4..c3ec4921 100644
--- a/test/passes/jacktest/Stack.fir
+++ b/test/passes/jacktest/Stack.fir
@@ -1,6 +1,4 @@
 ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-;CHECK: Finished Low Form Check
-;CHECK-NOT: stack_mem.T_32.mask <= UInt("h0")
 ;CHECK: Done!
 circuit Stack : 
   module Stack : 
@@ -19,7 +17,7 @@ circuit Stack :
       node T_30 = lt(sp, UInt<5>(16))
       node T_31 = and(push, T_30)
       when T_31 : 
-        write mport T_32 = stack_mem[sp],clk
+        write mport T_32 = stack_mem[sp],clk,UInt(1)
         T_32 <= dataIn
         node T_33 = addw(sp, UInt<1>(1))
         sp <= T_33
diff --git a/test/passes/jacktest/Tbl.fir b/test/passes/jacktest/Tbl.fir
index 4ae87360..9b259d0f 100644
--- a/test/passes/jacktest/Tbl.fir
+++ b/test/passes/jacktest/Tbl.fir
@@ -8,12 +8,12 @@ circuit Tbl :
     output o : UInt<16>
     input we : UInt<1>
     
-    cmem m : UInt<10>[256],clk
+    cmem m : UInt<10>[256]
     o <= UInt<1>(0)
     when we : 
-      infer accessor T_13 = m[i]
+      write mport T_13 = m[i],clk,UInt(1)
       node T_14 = bits(d, 9, 0)
       T_13 <= T_14
     else : 
-      infer accessor T_15 = m[i]
+      read mport T_15 = m[i],clk
       o <= T_15
diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir
index e4516db4..eb823321 100644
--- a/test/passes/jacktest/risc.fir
+++ b/test/passes/jacktest/risc.fir
@@ -11,26 +11,26 @@ circuit Risc :
     input clk : Clock
     input reset : UInt<1>
     
-    cmem file : UInt<32>[256],clk
-    cmem code : UInt<32>[256],clk
+    cmem file : UInt<32>[256]
+    cmem code : UInt<32>[256]
     reg pc : UInt<8>,clk,reset,UInt<8>(0)
-    infer accessor inst = code[pc]
+    read mport inst = code[pc],clk
     node op = bits(inst, 31, 24)
     node rci = bits(inst, 23, 16)
     node rai = bits(inst, 15, 8)
     node rbi = bits(inst, 7, 0)
     node T_51 = eq(rai, UInt<1>(0))
-    infer accessor T_52 = file[rai]
+    read mport T_52 = file[rai],clk
     node ra = mux(T_51, UInt<1>(0), T_52)
     node T_53 = eq(rbi, UInt<1>(0))
-    infer accessor T_54 = file[rbi]
+    read mport T_54 = file[rbi],clk
     node rb = mux(T_53, UInt<1>(0), T_54)
     wire rc : UInt<32>
     valid <= UInt<1>(0)
     out <= UInt<1>(0)
     rc <= UInt<1>(0)
     when isWr : 
-      infer accessor T_55 = code[wrAddr]
+      write mport T_55 = code[wrAddr],clk,UInt(1)
       T_55 <= wrData
     else : when boot : pc <= UInt<1>(0)
       else : 
@@ -47,7 +47,7 @@ circuit Risc :
         node T_61 = eq(rci, UInt<8>(255))
         when T_61 : valid <= UInt<1>(1)
         else : 
-          infer accessor T_62 = file[rci]
+          write mport T_62 = file[rci],clk,UInt(1)
           T_62 <= rc
         node T_63 = addw(pc, UInt<1>(1))
         pc <= T_63