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Diffstat (limited to 'test/passes/jacktest/Stack.fir')
| -rw-r--r-- | test/passes/jacktest/Stack.fir | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/test/passes/jacktest/Stack.fir b/test/passes/jacktest/Stack.fir index 9b35c3f4..c3ec4921 100644 --- a/test/passes/jacktest/Stack.fir +++ b/test/passes/jacktest/Stack.fir @@ -1,6 +1,4 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Finished Low Form Check -;CHECK-NOT: stack_mem.T_32.mask <= UInt("h0") ;CHECK: Done! circuit Stack : module Stack : @@ -19,7 +17,7 @@ circuit Stack : node T_30 = lt(sp, UInt<5>(16)) node T_31 = and(push, T_30) when T_31 : - write mport T_32 = stack_mem[sp],clk + write mport T_32 = stack_mem[sp],clk,UInt(1) T_32 <= dataIn node T_33 = addw(sp, UInt<1>(1)) sp <= T_33 |