diff options
Diffstat (limited to 'test')
| -rw-r--r-- | test/passes/jacktest/Stack.fir | 4 | ||||
| -rw-r--r-- | test/passes/jacktest/Tbl.fir | 6 | ||||
| -rw-r--r-- | test/passes/jacktest/risc.fir | 14 |
3 files changed, 11 insertions, 13 deletions
diff --git a/test/passes/jacktest/Stack.fir b/test/passes/jacktest/Stack.fir index 9b35c3f4..c3ec4921 100644 --- a/test/passes/jacktest/Stack.fir +++ b/test/passes/jacktest/Stack.fir @@ -1,6 +1,4 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Finished Low Form Check -;CHECK-NOT: stack_mem.T_32.mask <= UInt("h0") ;CHECK: Done! circuit Stack : module Stack : @@ -19,7 +17,7 @@ circuit Stack : node T_30 = lt(sp, UInt<5>(16)) node T_31 = and(push, T_30) when T_31 : - write mport T_32 = stack_mem[sp],clk + write mport T_32 = stack_mem[sp],clk,UInt(1) T_32 <= dataIn node T_33 = addw(sp, UInt<1>(1)) sp <= T_33 diff --git a/test/passes/jacktest/Tbl.fir b/test/passes/jacktest/Tbl.fir index 4ae87360..9b259d0f 100644 --- a/test/passes/jacktest/Tbl.fir +++ b/test/passes/jacktest/Tbl.fir @@ -8,12 +8,12 @@ circuit Tbl : output o : UInt<16> input we : UInt<1> - cmem m : UInt<10>[256],clk + cmem m : UInt<10>[256] o <= UInt<1>(0) when we : - infer accessor T_13 = m[i] + write mport T_13 = m[i],clk,UInt(1) node T_14 = bits(d, 9, 0) T_13 <= T_14 else : - infer accessor T_15 = m[i] + read mport T_15 = m[i],clk o <= T_15 diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir index e4516db4..eb823321 100644 --- a/test/passes/jacktest/risc.fir +++ b/test/passes/jacktest/risc.fir @@ -11,26 +11,26 @@ circuit Risc : input clk : Clock input reset : UInt<1> - cmem file : UInt<32>[256],clk - cmem code : UInt<32>[256],clk + cmem file : UInt<32>[256] + cmem code : UInt<32>[256] reg pc : UInt<8>,clk,reset,UInt<8>(0) - infer accessor inst = code[pc] + read mport inst = code[pc],clk node op = bits(inst, 31, 24) node rci = bits(inst, 23, 16) node rai = bits(inst, 15, 8) node rbi = bits(inst, 7, 0) node T_51 = eq(rai, UInt<1>(0)) - infer accessor T_52 = file[rai] + read mport T_52 = file[rai],clk node ra = mux(T_51, UInt<1>(0), T_52) node T_53 = eq(rbi, UInt<1>(0)) - infer accessor T_54 = file[rbi] + read mport T_54 = file[rbi],clk node rb = mux(T_53, UInt<1>(0), T_54) wire rc : UInt<32> valid <= UInt<1>(0) out <= UInt<1>(0) rc <= UInt<1>(0) when isWr : - infer accessor T_55 = code[wrAddr] + write mport T_55 = code[wrAddr],clk,UInt(1) T_55 <= wrData else : when boot : pc <= UInt<1>(0) else : @@ -47,7 +47,7 @@ circuit Risc : node T_61 = eq(rci, UInt<8>(255)) when T_61 : valid <= UInt<1>(1) else : - infer accessor T_62 = file[rci] + write mport T_62 = file[rci],clk,UInt(1) T_62 <= rc node T_63 = addw(pc, UInt<1>(1)) pc <= T_63 |