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2017-03-22Fixed zero width perf bug #502Adam Izraelevitz
Now remove DefNodes of zero width Don't deeply walk nodes (was the source of the bug)
2017-03-22Fix unapply of pinAdam Izraelevitz
2017-03-22Fixing whitespace broke test....azidar
2017-03-22Bugfix: apply/unapply of PinAnnotation brokenazidar
2017-03-17Add utilites for digraphs and netlist analysesAlbert Magyar
2017-03-17Give better error message if missing emitedcircuitAdam Izraelevitz
2017-03-15Merge pull request #495 from albert-magyar/fix-rocket-regressAlbert Magyar
Use newer rocket regression spec without comb loop
2017-03-15Use newer rocket regression spec without comb loopAlbert Magyar
2017-03-15Update readme with links to wiki (#493)Adam Izraelevitz
2017-03-14Small fixAdam Izraelevitz
2017-03-14Fixed shadowing of expression lesson2Adam Izraelevitz
2017-03-14Style fixesAdam Izraelevitz
2017-03-14Fixed README tutorial linkAdam Izraelevitz
2017-03-14Added lesson2Adam Izraelevitz
2017-03-10Tweak git clone commandEdward Wang
HTTPS clone is with .git; cd only with no error.
2017-03-10Set theme jekyll-theme-minimalAdam Izraelevitz
2017-03-10Changed custom transform option and help textAdam Izraelevitz
2017-03-10Added comments and section in READMEAdam Izraelevitz
2017-03-10Added tutorial passAdam Izraelevitz
2017-03-10Added custom transform commandline optionAdam Izraelevitz
2017-03-10Added Circuit mappersAdam Izraelevitz
2017-03-09make sure infer-rw works for exclusive when statements (#481)Donggyu
2017-03-09Sint tests and change in serialization (#456)Adam Izraelevitz
SInt representation is no longer 2's complement, but instead a positive number (hex or base 10) that is optionally preceded by a sign (-+).
2017-03-06Zero width (#402)Adam Izraelevitz
* Added Zero width wires. Semantics: - No change to width inference rules, e.g. a<0> + b<2> = c<3> - Replace zero width wires with UInt<1>(0) or SInt<1>(0) - Performs constant prop. - Redo width/type inference * Remove errant println * Moved ZeroWidth after ConvertFixedToSInt * Added more tests, bugfix match on connect Also replaced constprop with infertypes for correctness * Updated to new emitter and test infrastructure
2017-03-06Fix mistake when rebasingAdam Izraelevitz
2017-03-06After merge, fixed added transformsAdam Izraelevitz
2017-03-06Added more stylized debugging styleAdam Izraelevitz
2017-03-06Addresses #459. Rewords transform annotations API.Adam Izraelevitz
Now, any annotation not propagated by a transform is considered deleted. A new DeletedAnnotation is added in place of it.
2017-03-06Added pass name to debug loggerAdam Izraelevitz
2017-03-06Add ability to emit 1 file per module (#443)Jack Koenig
Changes Emitters to also be Transforms and use Annotations for both telling an emitter to do emission as well as getting the emitted result. Helper functions ease the use of the new interface. Also adds a FirrtlExecutionOptions field as well as a command-line option. Use of Writers in Compilers and Emitters is now deprecated.
2017-03-03Bugfix: InlineInstances must prefix instancesAdam Izraelevitz
2017-03-01Allow nested digit fields in subfield expressionsJack Koenig
Workaround for #470. This allows parsing DoubleLits in subfield expressions.
2017-03-01Fix bug in Lexer rule for DoubleLit and add testsJack Koenig
2017-02-28Fix validation print for log-level (#394)Colin Schmidt
2017-02-27castrhs shouldn't assume rhs is uint (#467)Angie Wang
* castrhs shouldn't assume rhs is uint * don't cast if types are the same * changed castrhs to catch invalid lhs, rhs type combinations * change error msg
2017-02-27Add chisel2 isVCSAvailable, isCommandAvailable to FileUtils. (#439)Jim Lawson
2017-02-26Align types and names of ports in emitted Verilog (#463)Jack Koenig
2017-02-23move more general utils out of memutils, mov WIR helpers to WIR.scala and ↵Angie
update uses
2017-02-23messed up clocktype matchAngie
2017-02-23fix bug in blackboxsourcehelper apply -- pointed to wrong transformAngie
2017-02-23added more helpersAngie
2017-02-23Add support for bundle fields to start with digits (#462)Jack Koenig
Also remove parsing support for ids with characters not supported in Verilog nor in the Firrtl spec
2017-02-23Fix warning from Cadence IncisiveScott Johnson
The fix for PR #305 caused a new compile warning from Cadence Incisive: always @(*) begin end | ncelab: *W,STARMT (../TestHarness.MyConfig.v,196147|9): This @* expands to empty list, will never wake up. This change satisfies all of: VCS, Incisive, Questa, Vivado, Verilator.
2017-02-22[stevo]: Adams fixStevo Bailey
2017-02-22Add jenkins-build target to check scalastyle and coverage. (#445)Adam Izraelevitz
2017-02-21Implementation of nodedupe mem (#447)Colin Schmidt
This allows the replseqmem transform to not deduplicate some memories, based on their name.
2017-02-16[skip chisel tests] Add ability to skip Chisel tests in Travis (#444)Jack Koenig
2017-02-14Add support for Analog types in partial connect (#435)Jack Koenig
Also add support for width inference
2017-02-14Fixes #441, ConvertFixedToSInt not recursing expsAdam Izraelevitz
2017-02-14Add println/throwInternalError to EmitterAdam Izraelevitz