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authorAdam Izraelevitz2017-03-06 16:07:20 -0800
committerAdam Izraelevitz2017-03-06 16:48:15 -0800
commita7fa5cd7e3c55c2bc828a04f60b6a4c41ea3876a (patch)
treeeef18a9913b5aa1fc318950e28953e018be9495d
parentfa4922dd3d985350fbc30281f6ffcf6e05c542ad (diff)
After merge, fixed added transforms
-rw-r--r--src/main/scala/firrtl/Emitter.scala12
-rw-r--r--src/test/scala/firrtlTests/AnnotationTests.scala3
-rw-r--r--src/test/scala/firrtlTests/PassTests.scala1
3 files changed, 12 insertions, 4 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 10d3ae85..b1c318fa 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -148,7 +148,11 @@ sealed abstract class FirrtlEmitter(form: CircuitForm) extends Transform with Em
emitAllModules(state.circuit) map (EmittedFirrtlModuleAnnotation(_))
case _ => Seq()
}
- state.copy(annotations = Some(AnnotationMap(newAnnos)))
+ val annos = newAnnos ++ (state.annotations match {
+ case None => Seq.empty
+ case Some(a) => a.annotations
+ })
+ state.copy(annotations = Some(AnnotationMap(annos)))
}
// Old style, deprecated
@@ -775,6 +779,10 @@ class VerilogEmitter extends Transform with PassBased with Emitter {
}
case _ => Seq()
}
- state.copy(annotations = Some(AnnotationMap(newAnnos)))
+ val annos = newAnnos ++ (state.annotations match {
+ case None => Seq.empty
+ case Some(a) => a.annotations
+ })
+ state.copy(annotations = Some(AnnotationMap(annos)))
}
}
diff --git a/src/test/scala/firrtlTests/AnnotationTests.scala b/src/test/scala/firrtlTests/AnnotationTests.scala
index 534b6540..5a86bfe5 100644
--- a/src/test/scala/firrtlTests/AnnotationTests.scala
+++ b/src/test/scala/firrtlTests/AnnotationTests.scala
@@ -136,8 +136,7 @@ class AnnotationTests extends AnnotationSpec with Matchers {
}
val anno = InlineAnnotation(CircuitName("Top"))
val annoOpt = Some(AnnotationMap(Seq(anno)))
- val writer = new StringWriter()
- val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, annoOpt), writer, Seq(new DeletingTransform))
+ val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, annoOpt), Seq(new DeletingTransform))
result.annotations.get.annotations.head should matchPattern {
case DeletedAnnotation(x, anno) =>
}
diff --git a/src/test/scala/firrtlTests/PassTests.scala b/src/test/scala/firrtlTests/PassTests.scala
index 8e5d74ad..589dfd38 100644
--- a/src/test/scala/firrtlTests/PassTests.scala
+++ b/src/test/scala/firrtlTests/PassTests.scala
@@ -9,6 +9,7 @@ import firrtl.ir.Circuit
import firrtl.Parser.UseInfo
import firrtl.passes.{Pass, PassExceptions, RemoveEmpty}
import firrtl._
+import logger._
// An example methodology for testing Firrtl Passes
// Spec class should extend this class