| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2017-11-28 | Have DedupModules report renaming | Jack | |
| 2017-11-28 | Refactor RenameMap to rename Components if their Module is renamed | Jack | |
| 2017-11-16 | Move digraph exceptions out of digraph class (#688) | Albert Magyar | |
| 2017-11-16 | Make Yosys equivalence check more robust (#686) | Jack Koenig | |
| Also let Travis know that equivalence checks can take a while | |||
| 2017-11-10 | Make digraph methods deterministic (#653) | Albert Magyar | |
| 2017-11-08 | Add InfoSpec for checking Info propagation | Jack Koenig | |
| 2017-11-08 | Add FirrtlCheckers and scalatest helpers for testing | Jack Koenig | |
| 2017-11-08 | Emit source locators as comments in emitted Verilog | Jack Koenig | |
| 2017-10-31 | Fix bug emitting and reparsing ExtModule String parameters (#675) | Jack Koenig | |
| 2017-10-03 | Merge pull request #670 from freechipsproject/add-formal-check | Jack Koenig | |
| Add Yosys formal equivalence checking to Travis regressions | |||
| 2017-10-01 | Add script for formally comparing emitted Verilog | Jack Koenig | |
| Also add Travis test for running this script on PRs | |||
| 2017-10-01 | Add Yosys 0.7 install | Jack Koenig | |
| 2017-10-01 | Remove redundant tests from Travis | Jack | |
| 2017-09-30 | Make ReplaceAccesses optimize multi-dimensional accesses (#665) | Albert Magyar | |
| 2017-09-30 | Update README.md to link tech report (#550) | Adam Izraelevitz | |
| 2017-09-30 | Fixed zero width cat but (#651) | Adam Izraelevitz | |
| 2017-09-29 | StringLit.verilogEscape should support all printable ASCII chars (#668) | Jack Koenig | |
| Defined as the range from ' ' to '~' [0x20, 0x7e] | |||
| 2017-09-29 | Namespace - only save suffix for temp names (#667) | Jack Koenig | |
| This prevents collisions for one prefix (including temp) from incrementing the suffix for other prefixes. Makes names more stable. | |||
| 2017-09-22 | Fix string lit (#663) | Jack Koenig | |
| Refactor StringLit to use String instead of Array[Byte] | |||
| 2017-09-21 | Some ScalaDoc warning fixes | Edward Wang | |
| 2017-09-21 | Fix problem where wrong verilog file is used. (#661) | Chick Markley | |
| When calling verilator in a subdirectory like ./test_run_dir/... verilator will read the verilog file from the current working directory if there is a file there with the right name. This fix specifies the specific path of the verilog file intended. | |||
| 2017-09-19 | Provide mechanism so that programs can optionally (#660) | Chick Markley | |
| not exit when --help is included in program flags | |||
| 2017-09-19 | Create way of collecting program arguments in Driver (#659) | Chick Markley | |
| Adds programArgs to commonOptions programArgs is all arguments on command line with out leading -/+ or are not bound to a flag. Create simple test | |||
| 2017-09-14 | Update sbt to 0.13.16; add Scala 2.12 support. (#639) | Jim Lawson | |
| * Update sbt to 0.13.16; add Scala 2.12 support. To clean, test, and build Scala 2.11 and Scala 2.12 versions: % sbt +clean +test +publishLocal * Update Travis to test in 2.11.11 and 2.12.3 * Try different way of providing Travis Scala version * Attempt to get verilator built before tests. | |||
| 2017-09-12 | Make pathsInDAG walk all possible paths (#655) | Schuyler Eldridge | |
| * Make pathsInDAG walk all possible paths Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Use linearization order when finding all paths in DAG | |||
| 2017-09-06 | Write tests on multi-rooted circuits for ConstProp | Edward Wang | |
| Since InstanceGraph now has all modules in its graph, test ConstProp on all modules as a default behaviour. - Need to think about how to target ConstProp only for a specific module? Close #644 | |||
| 2017-09-05 | Add InstanceGraph tests | Edward Wang | |
| 2017-09-05 | Make InstanceGraph track module hierarchies not contained in the top-level ↵ | Albert Magyar | |
| hierarchy | |||
| 2017-08-31 | Added option to emit final annotations (#649) | Adam Izraelevitz | |
| * Added option to emit final annotations * Removed extra > from output-anno-file * Removed other extra > from input-anno-file | |||
| 2017-08-23 | Reorder port and wire assignments in Verilog (#641) | Adam Izraelevitz | |
| * Reorder port and wire assignments in Verilog * Fixed up syntax | |||
| 2017-08-14 | Constant propagation across module boundaries (#633) | Jack Koenig | |
| 2017-08-04 | bug fix for cases when we want to flatten a module in which a module is ↵ | Andrey Ayupov | |
| instantiated multiple times (#634) | |||
| 2017-08-01 | DCE for IsInvalid (#629) | Donggyu | |
| 2017-07-26 | Flatten transformation (#631) | Andrey Ayupov | |
| * initial implementation of InlineDeepTransformation * rewrote transformation to not have any side effects in terms on inlining that was not annotated to be inlined * minor rewrites * renamed transformations to Flatten * fixes according to review * added more comments and fixed formating/style * fixed spacing, minor style fixes | |||
| 2017-07-18 | Merge pull request #626 from freechipsproject/fix-swap-bug | Jack Koenig | |
| Fix ConstProp bug where multiple names would swap with one | |||
| 2017-07-17 | do not swap wire names with node names | Donggyu Kim | |
| 2017-07-17 | Fix ConstProp bug where multiple names would swap with one | Jack Koenig | |
| Fixes issue in https://github.com/freechipsproject/rocket-chip/pull/848 | |||
| 2017-07-14 | Fix bug in DiGraph.reverse on an graph with one vertex, no edges (#628) | Jack Koenig | |
| 2017-07-06 | Fixed inability to disable combo loop check (#619) | Chick Markley | |
| * Fixed inability to disable combo loop check Moved checking of dontCheckComboLoops into loadAnnotations so that it works in cases where Driver.execute is not used. * Fix test for annotations, modifications to loadAnnotations made 2 more annotations visible. * Remove debug println from DriverSpec | |||
| 2017-07-03 | Merge pull request #621 from freechipsproject/const-prop-regs | Jack Koenig | |
| Const prop regs | |||
| 2017-06-29 | ConstProp registers that are only connected to or reset to a consant | Jack Koenig | |
| 2017-06-29 | Connect registers with no connections to zero | Jack Koenig | |
| 2017-06-29 | Add test for padding constant connections to wires in ConstProp | Jack Koenig | |
| 2017-06-29 | Merge pull request #620 from freechipsproject/keep-names | Jack Koenig | |
| Preserve "better" names in Constant Propagation | |||
| 2017-06-29 | Preserve "better" names in Constant Propagation | Jack Koenig | |
| Names that do not start with '_' are "better" than those that do | |||
| 2017-06-29 | Merge pull request #616 from freechipsproject/split-travis | Jack Koenig | |
| Use Travis Build Stages | |||
| 2017-06-29 | [Travis] Explicitly limit chisel tests parallelism to 2 | Jack | |
| 2017-06-29 | [Travis] Use Build Stages | Jack | |
| 2017-06-29 | Merge pull request #617 from freechipsproject/const-prop-regs | Jack Koenig | |
| Improvements to Constant Propagation and Testing | |||
| 2017-06-28 | Make Constant Propagation respect dontTouch | Jack Koenig | |
| Constant Propagation will not optimize across components marked dontTouch | |||
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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