sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2016-01-23	Moved inst declarations after other declarations	azidar

2016-01-23	Fixed commas for instances in verilog	azidar

2016-01-23	Added more semicolons	azidar

2016-01-23	Added semicolon after assigns in verilog	azidar

2016-01-23	off by one error when emitting ports in verilog	azidar

2016-01-23	Fixed combinational read verilog backend	azidar

2016-01-23	Removed more prints ;)	azidar

2016-01-23	Removed print statements	azidar

2016-01-23	Fixed bug where the write mask wasn't being generated correctly	azidar

2016-01-23	Removed debugging printlns	azidar

2016-01-23	Added inference to mports	azidar

2016-01-23	Added prefix checker, now compliant with firrtl spec	azidar

2016-01-23	Changed chirrtl to not require known mask values	azidar

2016-01-22	Merge branch 'new-spec' of github.com:ucb-bar/firrtl into new-mem	azidar
	Conflicts: spec/spec.pdf
2016-01-22	Added pdf	azidar

2016-01-22	Added a word	azidar

2016-01-22	Added funding number, as well as additional acknowledgements	azidar

2016-01-22	Finished version 0.2.0. Included leftovers for future user manual.	azidar

2016-01-21	First cut, some unfinished sections but readable	azidar

2016-01-20	WIP, almost finished with expressions. Removed poison, add is invalid and ↵	azidar
	validif()
2016-01-20	WIP, need to update chirrtl with new mask syntax	azidar

2016-01-20	WIP: finished partial connect	azidar

2016-01-19	WIP: Writing new spec.	azidar

2016-01-17	Forgot to add the changes	azidar

2016-01-17	Fixed error where memory of size 1 would create an index of size 0. This can ↵	azidar
	be fixed in the future with a pass that removes these memories
2016-01-17	Added check for uint on access index type	azidar

2016-01-17	Removed temporary files	azidar

2016-01-17	BIT-AND, BIT-OR, and BIT-XOR now can accept SInts. Fixed tests	azidar

2016-01-16	Added a bunch of tests and added firrtl-stanza and firrtl-scala to .gitignore	azidar

2016-01-16	Standard Verilog doesn't use Resolve(), but lists out the resolution passes ↵	azidar
	individually
2016-01-16	Fixed all tests so they either pass are marked as expected failures	azidar

2016-01-16	Updated passes so they test new-mem	azidar

2016-01-16	Fixed a test	azidar

2016-01-16	Fixed bug in lowering memories that had aggregate data types	azidar

2016-01-16	Fixed bug in check-init that allows it to check on non-lowered things	azidar

2016-01-16	Moved back to create-exps instead of fast-create-exps to fix bug - ↵	azidar
	fast-create-exps still needs debugging
2016-01-16	Nodes must now be ground types	azidar

2016-01-16	Fixed up minor errors after rebase onto master	azidar

2016-01-16	Fixed Vector performance tests	azidar

2016-01-16	Reworked Verilog emission of registers to if/else instead of ?:	azidar

2016-01-16	No longer split on muxes	azidar

2016-01-16	Commented back in Starting and Finishing for testing	azidar

2016-01-16	Sped up remove access by checking a condition	azidar

2016-01-16	Added more data in printout of time to compile	azidar

2016-01-16	printf no longer includes a new line	azidar

2016-01-16	Verilog emission no longer casts input to shr or bit select	azidar

2016-01-16	Added hashed on get flip	azidar

2016-01-16	Sped up some passes. Added global mname to allow easy per-module hashes for ↵	azidar
	accellerating functions
2016-01-16	Made create-exps a bit faster	azidar

2016-01-16	Finished first cut at new firrtl - time for testing! Chirrtl requires masks ↵	azidar
	to be specified with write and rdwr mports