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2016-10-17Reorganized memory blackboxing (#336)Adam Izraelevitz
* Reorganized memory blackboxing Moved to new package memlib Added comments Moved utility functions around Removed unused AnnotateValidMemConfigs.scala * Fixed tests to pass * Use DefAnnotatedMemory instead of AppendableInfo * Broke passes up into simpler passes AnnotateMemMacros -> (ToMemIR, ResolveMaskGranularity) UpdateDuplicateMemMacros -> (RenameAnnotatedMemoryPorts, ResolveMemoryReference) * Fixed to make tests run * Minor changes from code review * Removed vim comments and renamed ReplSeqMem
2016-10-17Add fixed point type (#322)Adam Izraelevitz
* WIP: Adding FixedType to Firrtl proper Got simple example running through width inference Checks should be ok Need to look into FixedLiteral more * Added simple test for fixed types * Added asFixedPoint to primops * Added tail case for FixedType * Added ConvertFixedToSInt.scala Added pass to MiddleToLowerFirrtl transform * Replace AsFixedType with AsSInt in fixed removal * Bugfix: constant from asFixed not deleted * Added unit test for bulk connect * Fixed partial connect bug #241 * Fixed missing case for FixedPoint in legalizeConnect * Add FixedMathSpec that demonstrates some problems with FixedPointMath * Fixed test and ConvertToSInt to pass. Negative binary points not easily supported, needs much more time to implement. * Refactored checking neg widths Make checking for negative binary points easier * Added tests for inferring many FixedType ops shl, shr, cat, bits, head, tail, setbp, shiftbp * Handle bpshl, bpshr, bpset in ConvertFixedToSInt Changed name from shiftbp -> bpshl, bpshr Change name from setbp -> bpset Added more tests * Added set binary point test that fails * Added simple test for zero binary point * gitignore fixes for antlr intermediate dir and intellij dir * removed unused imports retool the fixed point with zero binary point test * simplified example of inability to set binary point to zero * Temporary fix for zero-width binary point This fix allows for all widths to be zero, but since this is a feature I am working on next, I'm not going to bother with a more stringent check. * change version for dsp tools * Removed extra temporary file * Fixed merge bug * Fixed another merge bug * Removed commented out/unrelated files * Removed snake case
2016-10-11Scala style cleanup take 5 (#324)Chick Markley
* working through variable shrouding * working through variable shrouding * working through variable shadowing * working through variable shadowing hmm there are some very fragile match {} in Passes * working through variable shadowing hmm there are some very fragile match {} in Passes * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * Fixes suggested by Adam
2016-10-07Add test for Firrtl mems with no ports (#327)Jack Koenig
2016-10-07change default info mode to append (#328)Colin Schmidt
this makes it much easier to see where something went wrong during compilation if the lines have no info initially or its on internal nodes
2016-10-06Merge pull request #321 from ucb-bar/fix_infer_mdirJim Lawson
Fix CInferMDir
2016-09-29Merge branch 'master' into fix_infer_mdirJim Lawson
2016-09-27eliminate postfix operator problematic statementschick
2016-09-27remove unnecessary parentheseschick
2016-09-27enclosing block redundantchick
2016-09-27No return type for implicit functionchick
2016-09-27Anonymous function convertible to a method valuechick
2016-09-26add CInferMDirSpecDonggyu Kim
2016-09-26fix CInferMDir on SubAccessDonggyu Kim
indices should be read ports
2016-09-26Added max width check to dshl shift amount (#318)Adam Izraelevitz
Address #297
2016-09-26Update installation doc regarding #315 (#317)muojp
2016-09-25Spec features added: AnalogType and Attach (#295)Adam Izraelevitz
* Spec features added: AnalogType and Attach AnalogType(width: Width): - Concrete syntax: wire x: AnalogType<10> - New groundtype, very restricted in use cases. - Can only declare ports and wires with Analog type - Analog types are never equivalent, thus if x and y have Analog types: x <= y is never legal. Attach(info: Info, source: Expression, exprs: Seq[Expression]): - Concrete syntax: attach x to (y, z) - New statement - Source can be any groundtyped expression (UInt, SInt, Analog, Clock) - Exprs must have an Analog type reference an instance port - Source and exprs must have identical widths Included WDefInstanceConnector to enable emission of Verilog inout Should be mostly feature complete. Need to update spec if PR gets accepted. * Fixed bug where invalidated ports aren't handled * Bugfix for VerilogPrep Intermediate wires for invalidated instance ports were not invalidated * Bugfix: calling create_exp with name/tpe Returns unknown gender, which was passing through Caused temporary wire to not be declared Because Verilog is dumb, undeclared wires are assumed to be 1bit signals * Addressed donggyukim's style comments * Reworked pass to only allow analog types in attach Restrict source to be only wire or port kind Much simpler implementation, almost identical functionality Clearer semantics (i think?) * Fixup bugs from pulling in new changes from master * comments for type eqs and small style fixes
2016-09-25Merge pull request #260 from ucb-bar/mem_latency_pipesDonggyu
Mem latency pipes
2016-09-25offload latency pipe generation for memories from VerilogEmitterDonggyu Kim
discussed with @azidar
2016-09-25more readable verilog generation for register updatesDonggyu Kim
2016-09-25Merge pull request #316 from ucb-bar/style-cleanup-take-3Donggyu
Style cleanup take 3
2016-09-25Syntactic sugar says use (A, B) instead of Tuple2[A, B]chick
2016-09-25use sys.error instead of deprecated errorchick
2016-09-25stuff like this mutable.LinkedHashMap needs the mutable prefixchick
2016-09-25remove unnecessary blockschick
example 1 s"${x}" example 2 case blah => { ??? }
2016-09-25implicit functions should specify return typechick
2016-09-25 use name parameter when calling a function with boolean constantchick
2016-09-25Change file name ReplacesSubAccesses ReplaceAccesschick
2016-09-25convert all occurencess of BigInt == Int to BigInt == BigIntchick
2016-09-25Fix Anonymous function convertible to a method valuechick
if methods has parens, then referencing without parens is a method value, you don't need following underscore
2016-09-25Minor fixes, typo in wordchick
missing declarations in scala doc
2016-09-25Use empty-parens as appropriate for f: => Unit callschick
2016-09-25Update README.mdAdam Izraelevitz
2016-09-23Update Verilator on Travis to 3.886 (#315)Jack Koenig
2016-09-23use .count instead of filter and sizechick
2016-09-23Use parens on Unit methodschick
2016-09-23use .isEmpty, .nonEmpty, isDefinedchick
2016-09-23use .indiceschick
2016-09-23use .head instead of (0)chick
2016-09-22Fixed width inference for add, sub (#312)Adam Izraelevitz
Fixes #308 Fixes #193
2016-09-21Fix clock connections in InferReadWrite (#310)Donggyu
2016-09-21Merge pull request #306 from ucb-bar/refactor_mem_passesDonggyu
Style Fixes for Memory Passes
2016-09-21swap functions in MemPortUtils and MemTransformUtils properly for further ↵Donggyu Kim
refactoring
2016-09-21refactor AnnotateValidMemConfigsDonggyu Kim
2016-09-21refactor ReplaceMemMacrosDonggyu Kim
2016-09-21refactor UpdateDuplicateMemMacrosDonggyu Kim
2016-09-21clean up ReplSeqMemDonggyu Kim
2016-09-21refactor AnnotateMemMacrosDonggyu Kim
2016-09-21refactor InferReadWriteDonggyu Kim
2016-09-21generalize Analysis.getConnects for code resuseDonggyu Kim
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