Merge pull request #316 from ucb-bar/style-cleanup-take-3

Style cleanup take 3

27 files changed, 202 insertions, 215 deletions

diff --git a/src/main/scala/firrtl/Annotations.scala b/src/main/scala/firrtl/Annotations.scala
index 173006ab..a529d6f1 100644
--- a/src/main/scala/firrtl/Annotations.scala
+++ b/src/main/scala/firrtl/Annotations.scala
@@ -81,7 +81,7 @@ object Annotations {
   trait Rigid extends Permissibility {
     def check(from: Named, tos: Seq[Named], which: Annotation): Unit = tos.size match {
       case 0 => throw new AnnotationException(s"Cannot remove the rigid annotation ${which.serialize} on ${from.name}")
-      case 1 => {}
+      case 1 =>
       case _ => throw new AnnotationException(s"Cannot expand a rigid annotation on ${from.name} -> ${tos.map(_.name)}")
     }
   }
@@ -92,7 +92,7 @@ object Annotations {
   trait Firm extends Permissibility {
     def check(from: Named, tos: Seq[Named], which: Annotation): Unit = tos.size match {
       case 0 => throw new AnnotationException(s"Cannot remove the firm annotation ${which.serialize} on ${from.name}")
-      case _ => {}
+      case _ =>
     }
   }
 
@@ -163,7 +163,7 @@ object Annotations {
     def serialize: String = this.toString
     def update(tos: Seq[Named]): Seq[Annotation] = {
       check(target, tos, this)
-      propagate(target, tos, duplicate _)
+      propagate(target, tos, duplicate)
     }
   }
 
@@ -177,7 +177,7 @@ object Annotations {
     val (namedMap: NamedMap, idMap:IDMap) =
       //annotations.foldLeft(Tuple2[NamedMap, IDMap](Map.empty, Map.empty)){
       annotations.foldLeft((Map.empty: NamedMap, Map.empty: IDMap)){
-        (partialMaps: Tuple2[NamedMap, IDMap], annotation: Annotation) => {
+        (partialMaps: (NamedMap, IDMap), annotation: Annotation) => {
           val tIDToAnn = partialMaps._1.getOrElse(annotation.target, Map.empty)
           val pNMap = partialMaps._1 + (annotation.target -> (tIDToAnn + (annotation.tID -> annotation)))
 
diff --git a/src/main/scala/firrtl/Driver.scala b/src/main/scala/firrtl/Driver.scala
index 4022a813..ca25ef7a 100644
--- a/src/main/scala/firrtl/Driver.scala
+++ b/src/main/scala/firrtl/Driver.scala
@@ -155,7 +155,7 @@ Optional Arguments:
         case flag :: value :: tail if(customOptions.contains(flag)) =>
           annotations += customOptions(flag)(value)
           nextOption(map, tail)
-        case ("-h" | "--help") :: tail => { println(usage); sys.exit(0) }
+        case ("-h" | "--help") :: tail => println(usage); sys.exit(0)
         case option :: tail =>
           throw new Exception("Unknown option " + option + usage)
       }
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 435bc484..1e7c3103 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -31,6 +31,7 @@ import com.typesafe.scalalogging.LazyLogging
 import java.nio.file.{Paths, Files}
 import java.io.{Reader, Writer}
 
+import scala.collection.mutable
 import scala.sys.process._
 import scala.io.Source
 
@@ -190,11 +191,11 @@ class VerilogEmitter extends Emitter {
        case Pad =>
          val w = bitWidth(a0.tpe)
          val diff = (c0 - w)
-         if (w == 0) Seq(a0)
+         if (w == BigInt(0)) Seq(a0)
          else doprim.tpe match {
            // Either sign extend or zero extend.
-           // If width == 1, don't extract bit
-           case (_: SIntType) if w == 1 => Seq("{", c0, "{", a0, "}}")
+           // If width == BigInt(1), don't extract bit
+           case (_: SIntType) if w == BigInt(1) => Seq("{", c0, "{", a0, "}}")
            case (_: SIntType) => Seq("{{", diff, "{", a0, "[", w - 1, "]}},", a0, "}")
            case (_) => Seq("{{", diff, "'d0}, ", a0, "}")
          }
@@ -229,7 +230,7 @@ class VerilogEmitter extends Emitter {
          Seq(cast(a0), "[", _, "]")) reduce (_ + " ^ " + _)
        case Cat => Seq("{", cast(a0), ",", cast(a1), "}")
        // If selecting zeroth bit and single-bit wire, just emit the wire
-       case Bits if c0 == 0 && c1 == 0 && bitWidth(a0.tpe) == 1 => Seq(a0)
+       case Bits if c0 == 0 && c1 == 0 && bitWidth(a0.tpe) == BigInt(1) => Seq(a0)
        case Bits if c0 == c1 => Seq(a0, "[", c0, "]")
        case Bits => Seq(a0, "[", c0, ":", c1, "]")
        case Head =>
@@ -245,7 +246,7 @@ class VerilogEmitter extends Emitter {
    }
    
     def emit_verilog(m: Module)(implicit w: Writer): DefModule = {
-      val netlist = LinkedHashMap[WrappedExpression, Expression]()
+      val netlist = mutable.LinkedHashMap[WrappedExpression, Expression]()
       val simlist = ArrayBuffer[Statement]()
       val namespace = Namespace(m)
       def build_netlist(s: Statement): Statement = s map build_netlist match {
@@ -269,7 +270,7 @@ class VerilogEmitter extends Emitter {
       val declares = ArrayBuffer[Seq[Any]]()
       val instdeclares = ArrayBuffer[Seq[Any]]()
       val assigns = ArrayBuffer[Seq[Any]]()
-      val at_clock = LinkedHashMap[Expression,ArrayBuffer[Seq[Any]]]()
+      val at_clock = mutable.LinkedHashMap[Expression,ArrayBuffer[Seq[Any]]]()
       val initials = ArrayBuffer[Seq[Any]]()
       val simulates = ArrayBuffer[Seq[Any]]()
       def declare (b: String, n: String, t: Type) = t match {
@@ -311,7 +312,7 @@ class VerilogEmitter extends Emitter {
 
         def addUpdate(e: Expression, tabs: String): Seq[Seq[Any]] = {
           netlist.getOrElse(e, e) match {
-            case m: Mux if canFlatten(m) => {
+            case m: Mux if canFlatten(m) =>
               val ifStatement = Seq(tabs, "if(", m.cond, ") begin")
               val trueCase = addUpdate(m.tval, tabs + tab)
               val elseStatement = Seq(tabs, "end else begin")
@@ -322,7 +323,6 @@ class VerilogEmitter extends Emitter {
                 ifStatement +: trueCase :+ endStatement
               else
                 ifStatement +: trueCase ++: elseStatement +: falseCase :+ endStatement
-            }
             case _ if (weq(e, r)) => Seq()
             case _ => Seq(Seq(tabs, r, " <= ", e, ";"))
           }
@@ -640,9 +640,9 @@ class VerilogEmitter extends Emitter {
       }
 
       build_netlist(m.body)
-      build_ports
+      build_ports()
       build_streams(m.body)
-      emit_streams
+      emit_streams()
       m
    }
 
diff --git a/src/main/scala/firrtl/LexerHelper.scala b/src/main/scala/firrtl/LexerHelper.scala
index 2b2f68a8..6346eaaf 100644
--- a/src/main/scala/firrtl/LexerHelper.scala
+++ b/src/main/scala/firrtl/LexerHelper.scala
@@ -107,7 +107,7 @@ abstract class LexerHelper {
       t
   }
 
-  // will be overriden to FIRRTLLexer.super.nextToken() in the g4 file
+  // will be overridden to FIRRTLLexer.super.nextToken() in the g4 file
   protected def pullToken(): Token
 
   private def createToken(tokenType: Int, copyFrom: Token): Token =
diff --git a/src/main/scala/firrtl/Mappers.scala b/src/main/scala/firrtl/Mappers.scala
index c443ac37..ee1b5d0d 100644
--- a/src/main/scala/firrtl/Mappers.scala
+++ b/src/main/scala/firrtl/Mappers.scala
@@ -37,16 +37,16 @@ object Mappers {
     def map(stmt: Statement): Statement
   }
   private object StmtMagnet {
-    implicit def forStmt(f: Statement => Statement) = new StmtMagnet {
+    implicit def forStmt(f: Statement => Statement): StmtMagnet = new StmtMagnet {
       override def map(stmt: Statement): Statement = stmt mapStmt f
     }
-    implicit def forExp(f: Expression => Expression) = new StmtMagnet {
+    implicit def forExp(f: Expression => Expression): StmtMagnet = new StmtMagnet {
       override def map(stmt: Statement): Statement = stmt mapExpr f
     }
-    implicit def forType(f: Type => Type) = new StmtMagnet {
+    implicit def forType(f: Type => Type): StmtMagnet = new StmtMagnet {
       override def map(stmt: Statement) : Statement = stmt mapType f
     }
-    implicit def forString(f: String => String) = new StmtMagnet {
+    implicit def forString(f: String => String): StmtMagnet = new StmtMagnet {
       override def map(stmt: Statement): Statement = stmt mapString f
     }
   }
@@ -60,13 +60,13 @@ object Mappers {
     def map(expr: Expression): Expression
   }
   private object ExprMagnet {
-    implicit def forExpr(f: Expression => Expression) = new ExprMagnet {
+    implicit def forExpr(f: Expression => Expression): ExprMagnet = new ExprMagnet {
       override def map(expr: Expression): Expression = expr mapExpr f
     }
-    implicit def forType(f: Type => Type) = new ExprMagnet {
+    implicit def forType(f: Type => Type): ExprMagnet = new ExprMagnet {
       override def map(expr: Expression): Expression = expr mapType f
     }
-    implicit def forWidth(f: Width => Width) = new ExprMagnet {
+    implicit def forWidth(f: Width => Width): ExprMagnet = new ExprMagnet {
       override def map(expr: Expression): Expression = expr mapWidth f
     }
   }
@@ -79,10 +79,10 @@ object Mappers {
     def map(tpe: Type): Type
   }
   private object TypeMagnet {
-    implicit def forType(f: Type => Type) = new TypeMagnet {
+    implicit def forType(f: Type => Type): TypeMagnet = new TypeMagnet {
       override def map(tpe: Type): Type = tpe mapType f
     }
-    implicit def forWidth(f: Width => Width) = new TypeMagnet {
+    implicit def forWidth(f: Width => Width): TypeMagnet = new TypeMagnet {
       override def map(tpe: Type): Type = tpe mapWidth f
     }
   }
@@ -95,7 +95,7 @@ object Mappers {
     def map(width: Width): Width
   }
   private object WidthMagnet {
-    implicit def forWidth(f: Width => Width) = new WidthMagnet {
+    implicit def forWidth(f: Width => Width): WidthMagnet = new WidthMagnet {
       override def map(width: Width): Width = width match {
         case mapable: HasMapWidth => mapable mapWidth f // WIR
         case other => other // Standard IR nodes
@@ -111,13 +111,13 @@ object Mappers {
     def map(module: DefModule): DefModule
   }
   private object ModuleMagnet {
-    implicit def forStmt(f: Statement => Statement) = new ModuleMagnet {
+    implicit def forStmt(f: Statement => Statement): ModuleMagnet = new ModuleMagnet {
       override def map(module: DefModule): DefModule = module mapStmt f
     }
-    implicit def forPorts(f: Port => Port) = new ModuleMagnet {
+    implicit def forPorts(f: Port => Port): ModuleMagnet = new ModuleMagnet {
       override def map(module: DefModule): DefModule = module mapPort f
     }
-    implicit def forString(f: String => String) = new ModuleMagnet {
+    implicit def forString(f: String => String): ModuleMagnet = new ModuleMagnet {
       override def map(module: DefModule): DefModule = module mapString f
     }
   }
diff --git a/src/main/scala/firrtl/Namespace.scala b/src/main/scala/firrtl/Namespace.scala
index 1e922673..4fbab779 100644
--- a/src/main/scala/firrtl/Namespace.scala
+++ b/src/main/scala/firrtl/Namespace.scala
@@ -27,6 +27,7 @@ MODIFICATIONS.
 
 package firrtl
 
+import scala.collection.mutable
 import scala.collection.mutable.HashSet
 import firrtl.ir._
 import Mappers._
@@ -34,7 +35,7 @@ import Mappers._
 class Namespace private {
   private val tempNamePrefix: String = "GEN"
   // Begin with a tempNamePrefix in namespace so we always have a number suffix
-  private val namespace = HashSet[String](tempNamePrefix)
+  private val namespace = mutable.HashSet[String](tempNamePrefix)
   private var n = 0L
 
   def tryName(value: String): Boolean = {
diff --git a/src/main/scala/firrtl/StringLit.scala b/src/main/scala/firrtl/StringLit.scala
index 501e9686..fd282177 100644
--- a/src/main/scala/firrtl/StringLit.scala
+++ b/src/main/scala/firrtl/StringLit.scala
@@ -79,11 +79,10 @@ trait StringLitHandler {
             // TODO Finalize supported escapes, implement hex2Bytes
             //case 0x78 => (4, hex2Bytes(in.slice(2, 3)))) // hex escape
             //case 0x75 => (6, hex2Bytes(in.slice(2, 5))) // unicode excape 
-            case e => { // error
-              val msg = s"Invalid escape character ${e.toChar}! " + 
+            case e => // error
+              val msg = s"Invalid escape character ${e.toChar}! " +
                          "Valid characters [nt'\"\\]"
               throw new InvalidEscapeCharException(msg)
-            }
           }
           unescape(in.drop(n), out ++ bytes) // consume n
         } else {
@@ -111,11 +110,11 @@ object VerilogStringLitHandler extends StringLitHandler {
     def format(in: Array[Byte], out: Array[Byte], percent: Boolean): Array[Byte] = {
       if (in.isEmpty) out
       else {
-        if (percent && in.head == 'x') format(in.tail, out :+ 'h'.toByte, false)
+        if (percent && in.head == 'x') format(in.tail, out :+ 'h'.toByte, percent = false)
         else format(in.tail, out :+ in.head, in.head == '%' && !percent)
       }
     }
-    StringLit(format(lit.array, Array(), false))
+    StringLit(format(lit.array, Array(), percent = false))
   }
 }
 
diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala
index 05628d3f..453e9a0c 100644
--- a/src/main/scala/firrtl/Utils.scala
+++ b/src/main/scala/firrtl/Utils.scala
@@ -41,6 +41,7 @@ import firrtl.PrimOps._
 import firrtl.Mappers._
 import firrtl.WrappedExpression._
 import firrtl.WrappedType._
+import scala.collection.mutable
 import scala.collection.mutable.{StringBuilder, ArrayBuffer, LinkedHashMap, HashMap, HashSet}
 import java.io.PrintWriter
 import com.typesafe.scalalogging.LazyLogging
@@ -80,7 +81,7 @@ object Utils extends LazyLogging {
     if (bi < BigInt(0)) "\"h" + bi.toString(16).substring(1) + "\""
     else "\"h" + bi.toString(16) + "\""
 
-  implicit def toWrappedExpression (x:Expression) = new WrappedExpression(x)
+  implicit def toWrappedExpression (x:Expression): WrappedExpression = new WrappedExpression(x)
   def ceilLog2(x: BigInt): Int = (x-1).bitLength
   def max(a: BigInt, b: BigInt): BigInt = if (a >= b) a else b
   def min(a: BigInt, b: BigInt): BigInt = if (a >= b) b else a
@@ -144,7 +145,8 @@ object Utils extends LazyLogging {
   }
 
   /** Returns true if t, or any subtype, contains a flipped field
-    * @param t [[firrtl.ir.Type]]
+    *
+    * @param t type [[firrtl.ir.Type]] to be checked
     * @return if t contains [[firrtl.ir.Flip]]
     */
   def hasFlip(t: Type): Boolean = t match {
@@ -523,7 +525,7 @@ class MemoizedHash[T](val t: T) {
   * The graph is a map between the name of a node to set of names of that nodes children
   */
 class ModuleGraph {
-  val nodes = HashMap[String, HashSet[String]]()
+  val nodes = mutable.HashMap[String, mutable.HashSet[String]]()
 
   /**
     * Add a child to a parent node
@@ -534,7 +536,7 @@ class ModuleGraph {
     * @return a list indicating a path from child to parent, empty if no such path
     */
   def add(parent: String, child: String): List[String] = {
-    val childSet = nodes.getOrElseUpdate(parent, new HashSet[String])
+    val childSet = nodes.getOrElseUpdate(parent, new mutable.HashSet[String])
     childSet += child
     pathExists(child, parent, List(child, parent))
   }
@@ -546,7 +548,7 @@ class ModuleGraph {
     *
     * @param child  starting name
     * @param parent name to find in children (recursively)
-    * @param path
+    * @param path   path being investigated as possible route
     * @return
     */
   def pathExists(child: String, parent: String, path: List[String] = Nil): List[String] = {
diff --git a/src/main/scala/firrtl/Visitor.scala b/src/main/scala/firrtl/Visitor.scala
index 05202555..00ef8f1b 100644
--- a/src/main/scala/firrtl/Visitor.scala
+++ b/src/main/scala/firrtl/Visitor.scala
@@ -61,15 +61,13 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[FirrtlNode] {
       case ZeroPattern(_*) => BigInt(0)
       case HexPattern(hexdigits) =>
         hexdigits(0) match {
-          case NegPattern(_) => {
+          case NegPattern(_) =>
             BigInt("-" + hexdigits, 16)
-          }
           case _ => BigInt(hexdigits, 16)
         }
-      case DecPattern(sign, num) => {
+      case DecPattern(sign, num) =>
         if (sign != null) BigInt(sign + num, 10)
         else BigInt(num, 10)
-      }
       case _ => throw new Exception("Invalid String for conversion to BigInt " + s)
     }
   }
@@ -297,7 +295,7 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[FirrtlNode] {
       Reference(ctx.getText, UnknownType)
     else
       ctx.getChild(0).getText match {
-        case "UInt" => {
+        case "UInt" =>
           // This could be better
           val (width, value) =
             if (ctx.getChildCount > 4)
@@ -307,8 +305,7 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[FirrtlNode] {
               (IntWidth(BigInt(scala.math.max(bigint.bitLength, 1))), bigint)
             }
           UIntLiteral(value, width)
-        }
-        case "SInt" => {
+        case "SInt" =>
           val (width, value) =
             if (ctx.getChildCount > 4)
               (IntWidth(string2BigInt(ctx.IntLit(0).getText)), string2BigInt(ctx.IntLit(1).getText))
@@ -317,7 +314,6 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[FirrtlNode] {
               (IntWidth(BigInt(bigint.bitLength + 1)), bigint)
             }
           SIntLiteral(value, width)
-        }
         case "validif(" => ValidIf(visitExp(ctx.exp(0)), visitExp(ctx.exp(1)), UnknownType)
         case "mux(" => Mux(visitExp(ctx.exp(0)), visitExp(ctx.exp(1)), visitExp(ctx.exp(2)), UnknownType)
         case _ =>
diff --git a/src/main/scala/firrtl/passes/CheckChirrtl.scala b/src/main/scala/firrtl/passes/CheckChirrtl.scala
index 771577be..9858c0d2 100644
--- a/src/main/scala/firrtl/passes/CheckChirrtl.scala
+++ b/src/main/scala/firrtl/passes/CheckChirrtl.scala
@@ -37,25 +37,25 @@ object CheckChirrtl extends Pass {
   type NameSet = collection.mutable.HashSet[String]
 
   class NotUniqueException(info: Info, mname: String, name: String) extends PassException(
-    s"${info}: [module ${mname}] Reference ${name} does not have a unique name.")
+    s"$info: [module $mname] Reference $name does not have a unique name.")
   class InvalidLOCException(info: Info, mname: String) extends PassException(
-    s"${info}: [module ${mname}] Invalid connect to an expression that is not a reference or a WritePort.")
+    s"$info: [module $mname] Invalid connect to an expression that is not a reference or a WritePort.")
   class UndeclaredReferenceException(info: Info, mname: String, name: String) extends PassException(
-    s"${info}: [module ${mname}] Reference ${name} is not declared.")
+    s"$info: [module $mname] Reference $name is not declared.")
   class MemWithFlipException(info: Info, mname: String, name: String) extends PassException(
-    s"${info}: [module ${mname}] Memory ${name} cannot be a bundle type with flips.")
+    s"$info: [module $mname] Memory $name cannot be a bundle type with flips.")
   class InvalidAccessException(info: Info, mname: String) extends PassException(
-    s"${info}: [module ${mname}] Invalid access to non-reference.")
+    s"$info: [module $mname] Invalid access to non-reference.")
   class ModuleNotDefinedException(info: Info, mname: String, name: String) extends PassException(
-    s"${info}: Module ${name} is not defined.")
+    s"$info: Module $name is not defined.")
   class NegWidthException(info: Info, mname: String) extends PassException(
-    s"${info}: [module ${mname}] Width cannot be negative or zero.")
+    s"$info: [module $mname] Width cannot be negative or zero.")
   class NegVecSizeException(info: Info, mname: String) extends PassException(
-    s"${info}: [module ${mname}] Vector type size cannot be negative.")
+    s"$info: [module $mname] Vector type size cannot be negative.")
   class NegMemSizeException(info: Info, mname: String) extends PassException(
-    s"${info}: [module ${mname}] Memory size cannot be negative or zero.")
+    s"$info: [module $mname] Memory size cannot be negative or zero.")
   class NoTopModuleException(info: Info, name: String) extends PassException(
-    s"${info}: A single module must be named ${name}.")
+    s"$info: A single module must be named $name.")
 
   // TODO FIXME
   // - Do we need to check for uniquness on port names?
@@ -149,7 +149,7 @@ object CheckChirrtl extends Pass {
       case 1 =>
       case _ => errors append new NoTopModuleException(c.info, c.main)
     }
-    errors.trigger
+    errors.trigger()
     c
   }
 }
diff --git a/src/main/scala/firrtl/passes/CheckInitialization.scala b/src/main/scala/firrtl/passes/CheckInitialization.scala
index 7d7f2f32..12b83c55 100644
--- a/src/main/scala/firrtl/passes/CheckInitialization.scala
+++ b/src/main/scala/firrtl/passes/CheckInitialization.scala
@@ -116,7 +116,7 @@ object CheckInitialization extends Pass {
       case m: Module => checkInitM(m)
       case m => // Do nothing
     }
-    errors.trigger
+    errors.trigger()
     c
   }
 }
diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala
index d5fbdeeb..03ea106c 100644
--- a/src/main/scala/firrtl/passes/Checks.scala
+++ b/src/main/scala/firrtl/passes/Checks.scala
@@ -40,41 +40,41 @@ object CheckHighForm extends Pass {
 
   // Custom Exceptions
   class NotUniqueException(info: Info, mname: String, name: String) extends PassException(
-    s"${info}: [module ${mname}] Reference ${name} does not have a unique name.")
+    s"$info: [module $mname] Reference $name does not have a unique name.")
   class InvalidLOCException(info: Info, mname: String) extends PassException(
-    s"${info}: [module ${mname}] Invalid connect to an expression that is not a reference or a WritePort.")
+    s"$info: [module $mname] Invalid connect to an expression that is not a reference or a WritePort.")
   class NegUIntException(info: Info, mname: String) extends PassException(
-    s"${info}: [module ${mname}] UIntLiteral cannot be negative.")
+    s"$info: [module $mname] UIntLiteral cannot be negative.")
   class UndeclaredReferenceException(info: Info, mname: String, name: String) extends PassException(
-    s"${info}: [module ${mname}] Reference ${name} is not declared.")
+    s"$info: [module $mname] Reference $name is not declared.")
   class PoisonWithFlipException(info: Info, mname: String, name: String) extends PassException(
-    s"${info}: [module ${mname}] Poison ${name} cannot be a bundle type with flips.")
+    s"$info: [module $mname] Poison $name cannot be a bundle type with flips.")
   class MemWithFlipException(info: Info, mname: String, name: String) extends PassException(
-    s"${info}: [module ${mname}] Memory ${name} cannot be a bundle type with flips.")
+    s"$info: [module $mname] Memory $name cannot be a bundle type with flips.")
   class InvalidAccessException(info: Info, mname: String) extends PassException(
-    s"${info}: [module ${mname}] Invalid access to non-reference.")
+    s"$info: [module $mname] Invalid access to non-reference.")
   class ModuleNotDefinedException(info: Info, mname: String, name: String) extends PassException(
-    s"${info}: Module ${name} is not defined.")
+    s"$info: Module $name is not defined.")
   class IncorrectNumArgsException(info: Info, mname: String, op: String, n: Int) extends PassException(
-    s"${info}: [module ${mname}] Primop ${op} requires ${n} expression arguments.")
+    s"$info: [module $mname] Primop $op requires $n expression arguments.")
   class IncorrectNumConstsException(info: Info, mname: String, op: String, n: Int) extends PassException(
-    s"${info}: [module ${mname}] Primop ${op} requires ${n} integer arguments.")
+    s"$info: [module $mname] Primop $op requires $n integer arguments.")
   class NegWidthException(info: Info, mname: String) extends PassException(
-    s"${info}: [module ${mname}] Width cannot be negative or zero.")
+    s"$info: [module $mname] Width cannot be negative or zero.")
   class NegVecSizeException(info: Info, mname: String) extends PassException(
-    s"${info}: [module ${mname}] Vector type size cannot be negative.")
+    s"$info: [module $mname] Vector type size cannot be negative.")
   class NegMemSizeException(info: Info, mname: String) extends PassException(
-    s"${info}: [module ${mname}] Memory size cannot be negative or zero.")
+    s"$info: [module $mname] Memory size cannot be negative or zero.")
   class BadPrintfException(info: Info, mname: String, x: Char) extends PassException(
-    s"${info}: [module ${mname}] Bad printf format: " + "\"%" + x + "\"")
+    s"$info: [module $mname] Bad printf format: " + "\"%" + x + "\"")
   class BadPrintfTrailingException(info: Info, mname: String) extends PassException(
-    s"${info}: [module ${mname}] Bad printf format: trailing " + "\"%\"")
+    s"$info: [module $mname] Bad printf format: trailing " + "\"%\"")
   class BadPrintfIncorrectNumException(info: Info, mname: String) extends PassException(
-    s"${info}: [module ${mname}] Bad printf format: incorrect number of arguments")
+    s"$info: [module $mname] Bad printf format: incorrect number of arguments")
   class InstanceLoop(info: Info, mname: String, loop: String) extends PassException(
-    s"${info}: [module ${mname}] Has instance loop $loop")
+    s"$info: [module $mname] Has instance loop $loop")
   class NoTopModuleException(info: Info, name: String) extends PassException(
-    s"${info}: A single module must be named ${name}.")
+    s"$info: A single module must be named $name.")
 
   // TODO FIXME
   // - Do we need to check for uniquness on port names?
@@ -222,7 +222,7 @@ object CheckHighForm extends Pass {
       case 1 =>
       case _ => errors append new NoTopModuleException(c.info, c.main)
     }
-    errors.trigger
+    errors.trigger()
     c
   }
 }
@@ -232,51 +232,51 @@ object CheckTypes extends Pass {
 
   // Custom Exceptions
   class SubfieldNotInBundle(info: Info, mname: String, name: String) extends PassException(
-    s"${info}: [module ${mname} ]  Subfield ${name} is not in bundle.")
+    s"$info: [module $mname ]  Subfield $name is not in bundle.")
   class SubfieldOnNonBundle(info: Info, mname: String, name: String) extends PassException(
-    s"${info}: [module ${mname}]  Subfield ${name} is accessed on a non-bundle.")
+    s"$info: [module $mname]  Subfield $name is accessed on a non-bundle.")
   class IndexTooLarge(info: Info, mname: String, value: Int) extends PassException(
-    s"${info}: [module ${mname}]  Index with value ${value} is too large.")
+    s"$info: [module $mname]  Index with value $value is too large.")
   class IndexOnNonVector(info: Info, mname: String) extends PassException(
-    s"${info}: [module ${mname}]  Index illegal on non-vector type.")
+    s"$info: [module $mname]  Index illegal on non-vector type.")
   class AccessIndexNotUInt(info: Info, mname: String) extends PassException(
-    s"${info}: [module ${mname}]  Access index must be a UInt type.")
+    s"$info: [module $mname]  Access index must be a UInt type.")
   class IndexNotUInt(info: Info, mname: String) extends PassException(
-    s"${info}: [module ${mname}]  Index is not of UIntType.")
+    s"$info: [module $mname]  Index is not of UIntType.")
   class EnableNotUInt(info: Info, mname: String) extends PassException(
-    s"${info}: [module ${mname}]  Enable is not of UIntType.")
+    s"$info: [module $mname]  Enable is not of UIntType.")
   class InvalidConnect(info: Info, mname: String, lhs: String, rhs: String) extends PassException(
-    s"${info}: [module ${mname}]  Type mismatch. Cannot connect ${lhs} to ${rhs}.")
+    s"$info: [module $mname]  Type mismatch. Cannot connect $lhs to $rhs.")
   class InvalidRegInit(info: Info, mname: String) extends PassException(
-    s"${info}: [module ${mname}]  Type of init must match type of DefRegister.")
+    s"$info: [module $mname]  Type of init must match type of DefRegister.")
   class PrintfArgNotGround(info: Info, mname: String) extends PassException(
-    s"${info}: [module ${mname}]  Printf arguments must be either UIntType or SIntType.")
+    s"$info: [module $mname]  Printf arguments must be either UIntType or SIntType.")
   class ReqClk(info: Info, mname: String) extends PassException(
-    s"${info}: [module ${mname}]  Requires a clock typed signal.")
+    s"$info: [module $mname]  Requires a clock typed signal.")
   class EnNotUInt(info: Info, mname: String) extends PassException(
-    s"${info}: [module ${mname}]  Enable must be a UIntType typed signal.")
+    s"$info: [module $mname]  Enable must be a UIntType typed signal.")
   class PredNotUInt(info: Info, mname: String) extends PassException(
-    s"${info}: [module ${mname}]  Predicate not a UIntType.")
+    s"$info: [module $mname]  Predicate not a UIntType.")
   class OpNotGround(info: Info, mname: String, op: String) extends PassException(
-    s"${info}: [module ${mname}]  Primop ${op} cannot operate on non-ground types.")
+    s"$info: [module $mname]  Primop $op cannot operate on non-ground types.")
   class OpNotUInt(info: Info, mname: String, op: String, e: String) extends PassException(
-    s"${info}: [module ${mname}]  Primop ${op} requires argument ${e} to be a UInt type.")
+    s"$info: [module $mname]  Primop $op requires argument $e to be a UInt type.")
   class OpNotAllUInt(info: Info, mname: String, op: String) extends PassException(
-    s"${info}: [module ${mname}]  Primop ${op} requires all arguments to be UInt type.")
+    s"$info: [module $mname]  Primop $op requires all arguments to be UInt type.")
   class OpNotAllSameType(info: Info, mname: String, op: String) extends PassException(
-    s"${info}: [module ${mname}]  Primop ${op} requires all operands to have the same type.")
+    s"$info: [module $mname]  Primop $op requires all operands to have the same type.")
   class NodePassiveType(info: Info, mname: String) extends PassException(
-    s"${info}: [module ${mname}]  Node must be a passive type.")
+    s"$info: [module $mname]  Node must be a passive type.")
   class MuxSameType(info: Info, mname: String) extends PassException(
-    s"${info}: [module ${mname}]  Must mux between equivalent types.")
+    s"$info: [module $mname]  Must mux between equivalent types.")
   class MuxPassiveTypes(info: Info, mname: String) extends PassException(
-    s"${info}: [module ${mname}]  Must mux between passive types.")
+    s"$info: [module $mname]  Must mux between passive types.")
   class MuxCondUInt(info: Info, mname: String) extends PassException(
-    s"${info}: [module ${mname}]  A mux condition must be of type UInt.")
+    s"$info: [module $mname]  A mux condition must be of type UInt.")
   class ValidIfPassiveTypes(info: Info, mname: String) extends PassException(
-    s"${info}: [module ${mname}]  Must validif a passive type.")
+    s"$info: [module $mname]  Must validif a passive type.")
   class ValidIfCondUInt(info: Info, mname: String) extends PassException(
-    s"${info}: [module ${mname}]  A validif condition must be of type UInt.")
+    s"$info: [module $mname]  A validif condition must be of type UInt.")
 
   //;---------------- Helper Functions --------------
   def ut: UIntType = UIntType(UnknownWidth)
@@ -419,7 +419,7 @@ object CheckTypes extends Pass {
     }
 
     c.modules foreach (m => m map check_types_s(m.info, m.name))
-    errors.trigger
+    errors.trigger()
     c
   }
 }
@@ -436,7 +436,7 @@ object CheckGenders extends Pass {
   }
    
   class WrongGender(info:Info, mname: String, expr: String, wrong: Gender, right: Gender) extends PassException(
-    s"${info}: [module ${mname}]  Expression ${expr} is used as a ${wrong} but can only be used as a ${right}.")
+    s"$info: [module $mname]  Expression $expr is used as a $wrong but can only be used as a $right.")
    
   def run (c:Circuit): Circuit = {
     val errors = new Errors()
@@ -522,7 +522,7 @@ object CheckGenders extends Pass {
       genders ++= (m.ports map (p => p.name -> to_gender(p.direction)))
       m map check_genders_s(m.info, m.name, genders)
     }
-    errors.trigger
+    errors.trigger()
     c
   }
 }
@@ -530,17 +530,17 @@ object CheckGenders extends Pass {
 object CheckWidths extends Pass {
   def name = "Width Check"
   class UninferredWidth (info: Info, mname: String) extends PassException(
-    s"${info} : [module ${mname}]  Uninferred width.")
+    s"$info : [module $mname]  Uninferred width.")
   class WidthTooSmall(info: Info, mname: String, b: BigInt) extends PassException(
     s"$info : [module $mname]  Width too small for constant ${serialize(b)}.")
   class NegWidthException(info:Info, mname: String) extends PassException(
-    s"${info}: [module ${mname}] Width cannot be negative or zero.")
+    s"$info: [module $mname] Width cannot be negative or zero.")
   class BitsWidthException(info: Info, mname: String, hi: BigInt, width: BigInt) extends PassException(
-    s"${info}: [module ${mname}] High bit $hi in bits operator is larger than input width $width.")
+    s"$info: [module $mname] High bit $hi in bits operator is larger than input width $width.")
   class HeadWidthException(info: Info, mname: String, n: BigInt, width: BigInt) extends PassException(
-    s"${info}: [module ${mname}] Parameter $n in head operator is larger than input width $width.")
+    s"$info: [module $mname] Parameter $n in head operator is larger than input width $width.")
   class TailWidthException(info: Info, mname: String, n: BigInt, width: BigInt) extends PassException(
-    s"${info}: [module ${mname}] Parameter $n in tail operator is larger than input width $width.")
+    s"$info: [module $mname] Parameter $n in tail operator is larger than input width $width.")
 
   def run(c: Circuit): Circuit = {
     val errors = new Errors()
@@ -594,7 +594,7 @@ object CheckWidths extends Pass {
     }
 
     c.modules foreach check_width_m
-    errors.trigger
+    errors.trigger()
     c
   }
 }
diff --git a/src/main/scala/firrtl/passes/ConstProp.scala b/src/main/scala/firrtl/passes/ConstProp.scala
index bb8ca549..a95d3de0 100644
--- a/src/main/scala/firrtl/passes/ConstProp.scala
+++ b/src/main/scala/firrtl/passes/ConstProp.scala
@@ -60,8 +60,8 @@ object ConstProp extends Pass {
   object FoldAND extends FoldLogicalOp {
     def fold(c1: Literal, c2: Literal) = UIntLiteral(c1.value & c2.value, c1.width max c2.width)
     def simplify(e: Expression, lhs: Literal, rhs: Expression) = lhs match {
-      case UIntLiteral(v, w) if v == 0 => UIntLiteral(0, w)
-      case SIntLiteral(v, w) if v == 0 => UIntLiteral(0, w)
+      case UIntLiteral(v, w) if v == BigInt(0) => UIntLiteral(0, w)
+      case SIntLiteral(v, w) if v == BigInt(0) => UIntLiteral(0, w)
       case UIntLiteral(v, IntWidth(w)) if v == (BigInt(1) << bitWidth(rhs.tpe).toInt) - 1 => rhs
       case _ => e
     }
@@ -70,8 +70,8 @@ object ConstProp extends Pass {
   object FoldOR extends FoldLogicalOp {
     def fold(c1: Literal, c2: Literal) = UIntLiteral(c1.value | c2.value, c1.width max c2.width)
     def simplify(e: Expression, lhs: Literal, rhs: Expression) = lhs match {
-      case UIntLiteral(v, _) if v == 0 => rhs
-      case SIntLiteral(v, _) if v == 0 => asUInt(rhs, e.tpe)
+      case UIntLiteral(v, _) if v == BigInt(0) => rhs
+      case SIntLiteral(v, _) if v == BigInt(0) => asUInt(rhs, e.tpe)
       case UIntLiteral(v, IntWidth(w)) if v == (BigInt(1) << bitWidth(rhs.tpe).toInt) - 1 => lhs
       case _ => e
     }
@@ -80,8 +80,8 @@ object ConstProp extends Pass {
   object FoldXOR extends FoldLogicalOp {
     def fold(c1: Literal, c2: Literal) = UIntLiteral(c1.value ^ c2.value, c1.width max c2.width)
     def simplify(e: Expression, lhs: Literal, rhs: Expression) = lhs match {
-      case UIntLiteral(v, _) if v == 0 => rhs
-      case SIntLiteral(v, _) if v == 0 => asUInt(rhs, e.tpe)
+      case UIntLiteral(v, _) if v == BigInt(0) => rhs
+      case SIntLiteral(v, _) if v == BigInt(0) => asUInt(rhs, e.tpe)
       case _ => e
     }
   }
@@ -89,7 +89,7 @@ object ConstProp extends Pass {
   object FoldEqual extends FoldLogicalOp {
     def fold(c1: Literal, c2: Literal) = UIntLiteral(if (c1.value == c2.value) 1 else 0, IntWidth(1))
     def simplify(e: Expression, lhs: Literal, rhs: Expression) = lhs match {
-      case UIntLiteral(v, IntWidth(w)) if v == 1 && w == 1 && bitWidth(rhs.tpe) == 1 => rhs
+      case UIntLiteral(v, IntWidth(w)) if v == BigInt(1) && w == BigInt(1) && bitWidth(rhs.tpe) == BigInt(1) => rhs
       case _ => e
     }
   }
@@ -97,7 +97,7 @@ object ConstProp extends Pass {
   object FoldNotEqual extends FoldLogicalOp {
     def fold(c1: Literal, c2: Literal) = UIntLiteral(if (c1.value != c2.value) 1 else 0, IntWidth(1))
     def simplify(e: Expression, lhs: Literal, rhs: Expression) = lhs match {
-      case UIntLiteral(v, IntWidth(w)) if v == 0 && w == 1 && bitWidth(rhs.tpe) == 1 => rhs
+      case UIntLiteral(v, IntWidth(w)) if v == BigInt(0) && w == BigInt(1) && bitWidth(rhs.tpe) == BigInt(1) => rhs
       case _ => e
     }
   }
@@ -176,7 +176,7 @@ object ConstProp extends Pass {
       }
       // Calculates an expression's range of values
       x match {
-        case e: DoPrim => {
+        case e: DoPrim =>
           def r0 = range(e.args.head)
           def r1 = range(e.args(1))
           e.op match {
@@ -192,7 +192,6 @@ object ConstProp extends Pass {
             case Geq if (r0 < r1) => zero
             case _ => e
           }
-        }
         case e => e
       }
     }
@@ -230,12 +229,11 @@ object ConstProp extends Pass {
       case _ => e
     }
     case Bits => e.args.head match {
-      case lit: Literal => {
+      case lit: Literal =>
         val hi = e.consts.head.toInt
         val lo = e.consts(1).toInt
         require(hi >= lo)
         UIntLiteral((lit.value >> lo) & ((BigInt(1) << (hi - lo + 1)) - 1), getWidth(e.tpe))
-      }
       case x if bitWidth(e.tpe) == bitWidth(x.tpe) => x.tpe match {
         case t: UIntType => x
         case _ => asUInt(x, e.tpe)
@@ -246,14 +244,14 @@ object ConstProp extends Pass {
   }
 
   private def constPropMuxCond(m: Mux) = m.cond match {
-    case UIntLiteral(c, _) => pad(if (c == 1) m.tval else m.fval, m.tpe)
+    case UIntLiteral(c, _) => pad(if (c == BigInt(1)) m.tval else m.fval, m.tpe)
     case _ => m
   }
 
   private def constPropMux(m: Mux): Expression = (m.tval, m.fval) match {
     case _ if m.tval == m.fval => m.tval
     case (t: UIntLiteral, f: UIntLiteral) =>
-      if (t.value == 1 && f.value == 0 && bitWidth(m.tpe) == 1) m.cond
+      if (t.value == BigInt(1) && f.value == BigInt(0) && bitWidth(m.tpe) == BigInt(1)) m.cond
       else constPropMuxCond(m)
     case _ => constPropMuxCond(m)
   }
diff --git a/src/main/scala/firrtl/passes/InferReadWrite.scala b/src/main/scala/firrtl/passes/InferReadWrite.scala
index 74800cf5..f863c7e7 100644
--- a/src/main/scala/firrtl/passes/InferReadWrite.scala
+++ b/src/main/scala/firrtl/passes/InferReadWrite.scala
@@ -55,7 +55,7 @@ object InferReadWritePass extends Pass {
   type Statements = collection.mutable.ArrayBuffer[Statement]
   type PortSet = collection.mutable.HashSet[String]
 
-  private implicit def toString(e: Expression) = e.serialize
+  private implicit def toString(e: Expression): String = e.serialize
 
   def getProductTerms(connects: Connects)(e: Expression): Seq[Expression] = e match {
     // No ConstProp yet...
@@ -178,7 +178,7 @@ class InferReadWrite(transID: TransID) extends Transform with SimpleRun {
   def execute(c: Circuit, map: AnnotationMap) = map get transID match {
     case Some(p) => p get CircuitName(c.main) match {
       case Some(InferReadWriteAnnotation(_, _)) => run(c, passSeq)
-      case _ => error("Unexpected annotation for InferReadWrite")
+      case _ => sys.error("Unexpected annotation for InferReadWrite")
     }
     case _ => TransformResult(c)
   }
diff --git a/src/main/scala/firrtl/passes/InferWidths.scala b/src/main/scala/firrtl/passes/InferWidths.scala
index ebec4d80..1a8cc343 100644
--- a/src/main/scala/firrtl/passes/InferWidths.scala
+++ b/src/main/scala/firrtl/passes/InferWidths.scala
@@ -287,8 +287,8 @@ object InferWidths extends Pass {
             v <- h.get(w.name) if !v.isInstanceOf[VarWidth]
             result <- solve(v)
           } yield result
-        case (w: MaxWidth) => reduceOptions(forceNonEmpty(w.args.map(solve _), Some(BigInt(0))), max)
-        case (w: MinWidth) => reduceOptions(forceNonEmpty(w.args.map(solve _), None), min)
+        case (w: MaxWidth) => reduceOptions(forceNonEmpty(w.args.map(solve), Some(BigInt(0))), max)
+        case (w: MinWidth) => reduceOptions(forceNonEmpty(w.args.map(solve), None), min)
         case (w: PlusWidth) => map2(solve(w.arg1), solve(w.arg2), {_ + _})
         case (w: MinusWidth) => map2(solve(w.arg1), solve(w.arg2), {_ - _})
         case (w: ExpWidth) => map2(Some(BigInt(2)), solve(w.arg1), pow_minus_one)
diff --git a/src/main/scala/firrtl/passes/Inline.scala b/src/main/scala/firrtl/passes/Inline.scala
index 23d8caf1..e2a69751 100644
--- a/src/main/scala/firrtl/passes/Inline.scala
+++ b/src/main/scala/firrtl/passes/Inline.scala
@@ -22,7 +22,7 @@ class InlineInstances (transID: TransID) extends Transform {
    def execute(circuit: Circuit, annotationMap: AnnotationMap): TransformResult = {
      annotationMap.get(transID) match {
        case None => TransformResult(circuit, None, None)
-       case Some(map) => {
+       case Some(map) =>
          val moduleNames = mutable.HashSet[ModuleName]()
          val instanceNames = mutable.HashSet[ComponentName]()
          map.values.foreach {x: Annotation => x match {
@@ -32,7 +32,6 @@ class InlineInstances (transID: TransID) extends Transform {
          }}
          check(circuit, moduleNames.toSet, instanceNames.toSet)
          run(circuit, moduleNames.toSet, instanceNames.toSet)
-       }
 
        // Default behavior is to error if more than one annotation for inlining
        //  This could potentially change
@@ -49,11 +48,11 @@ class InlineInstances (transID: TransID) extends Transform {
       val moduleMap = (for(m <- c.modules) yield m.name -> m).toMap
       def checkExists(name: String): Unit =
          if (!moduleMap.contains(name))
-            errors += new PassException(s"Annotated module does not exist: ${name}")
+            errors += new PassException(s"Annotated module does not exist: $name")
       def checkExternal(name: String): Unit = moduleMap(name) match {
-            case m: ExtModule => errors += new PassException(s"Annotated module cannot be an external module: ${name}")
-            case _ => {}
-         }
+            case m: ExtModule => errors += new PassException(s"Annotated module cannot be an external module: $name")
+            case _ =>
+      }
       def checkInstance(cn: ComponentName): Unit = {
          var containsCN = false
          def onStmt(name: String)(s: Statement): Statement = {
@@ -63,7 +62,7 @@ class InlineInstances (transID: TransID) extends Transform {
                      containsCN = true
                      checkExternal(module_name)
                   }
-               case _ => {}
+               case _ =>
             }
             s map onStmt(name)
          }
@@ -101,71 +100,67 @@ class InlineInstances (transID: TransID) extends Transform {
          val inlinedInstances = mutable.ArrayBuffer[String]()
          // Recursive. Replaces inst.port with inst$port
          def onExp(e: Expression): Expression = e match {
-            case WSubField(WRef(ref, _, _, _), field, tpe, gen) => {
-               // Relies on instance declaration before any instance references
-               if (inlinedInstances.contains(ref)) {
-                  val newName = ref + inlineDelim + field
-                  set(ComponentName(ref, ModuleName(m.name, cname)), Seq.empty)
-                  WRef(newName, tpe, WireKind, gen)
-               }
-               else e
-            }
+            case WSubField(WRef(ref, _, _, _), field, tpe, gen) =>
+              // Relies on instance declaration before any instance references
+              if (inlinedInstances.contains(ref)) {
+                 val newName = ref + inlineDelim + field
+                 set(ComponentName(ref, ModuleName(m.name, cname)), Seq.empty)
+                 WRef(newName, tpe, WireKind, gen)
+              }
+              else e
             case e => e map onExp
          }
          // Recursive. Inlines tagged instances
          def onStmt(s: Statement): Statement = s match {
-               case WDefInstance(info, instName, moduleName, instTpe) => {
-                  def rename(name:String): String = {
-                     val newName = instName + inlineDelim + name
-                     update(ComponentName(name, ModuleName(moduleName, cname)), ComponentName(newName, ModuleName(m.name, cname)))
-                     newName
-                  }
-                  // Rewrites references in inlined statements from ref to inst$ref
-                  def renameStmt(s: Statement): Statement = {
-                     def renameExp(e: Expression): Expression = {
-                        e map renameExp match {
-                           case WRef(name, tpe, kind, gen) => WRef(rename(name), tpe, kind, gen)
-                           case e => e
-                        }
-                     }
-                     s map rename map renameStmt map renameExp
-                  }
-                  val shouldInline =
-                     modsToInline.contains(ModuleName(moduleName, cname)) ||
-                        instsToInline.contains(ComponentName(instName, ModuleName(m.name, cname)))
-                  // Used memoized instance if available
-                  val instModule =
-                     if (inlinedModules.contains(name)) inlinedModules(name)
-                     else {
-                        // Warning - can infinitely recurse if there is an instance loop
-                        onModule(originalModules(moduleName))
-                     }
-                  if (shouldInline) {
-                     inlinedInstances += instName
-                     val instInModule = instModule match {
-                        case m: ExtModule => throw new PassException("Cannot inline external module")
-                        case m: Module => m
-                     }
-                     val stmts = mutable.ArrayBuffer[Statement]()
-                     for (p <- instInModule.ports) {
-                        stmts += DefWire(p.info, rename(p.name), p.tpe)
-                     }
-                     stmts += renameStmt(instInModule.body)
-                     Block(stmts.toSeq)
-                  } else s
-               }
+               case WDefInstance(info, instName, moduleName, instTpe) =>
+                 def rename(name:String): String = {
+                    val newName = instName + inlineDelim + name
+                    update(ComponentName(name, ModuleName(moduleName, cname)), ComponentName(newName, ModuleName(m.name, cname)))
+                    newName
+                 }
+                 // Rewrites references in inlined statements from ref to inst$ref
+                 def renameStmt(s: Statement): Statement = {
+                    def renameExp(e: Expression): Expression = {
+                       e map renameExp match {
+                          case WRef(name, tpe, kind, gen) => WRef(rename(name), tpe, kind, gen)
+                          case e => e
+                       }
+                    }
+                    s map rename map renameStmt map renameExp
+                 }
+                 val shouldInline =
+                    modsToInline.contains(ModuleName(moduleName, cname)) ||
+                       instsToInline.contains(ComponentName(instName, ModuleName(m.name, cname)))
+                 // Used memoized instance if available
+                 val instModule =
+                    if (inlinedModules.contains(name)) inlinedModules(name)
+                    else {
+                       // Warning - can infinitely recurse if there is an instance loop
+                       onModule(originalModules(moduleName))
+                    }
+                 if (shouldInline) {
+                    inlinedInstances += instName
+                    val instInModule = instModule match {
+                       case m: ExtModule => throw new PassException("Cannot inline external module")
+                       case m: Module => m
+                    }
+                    val stmts = mutable.ArrayBuffer[Statement]()
+                    for (p <- instInModule.ports) {
+                       stmts += DefWire(p.info, rename(p.name), p.tpe)
+                    }
+                    stmts += renameStmt(instInModule.body)
+                    Block(stmts.toSeq)
+                 } else s
                case s => s map onExp map onStmt
             }
          m match {
-            case Module(info, name, ports, body) => {
-               val mx = Module(info, name, ports, onStmt(body))
-               inlinedModules(name) = mx
-               mx
-            }
-            case m: ExtModule => {
-               inlinedModules(m.name) = m
-               m
-            }
+            case Module(info, name, ports, body) =>
+              val mx = Module(info, name, ports, onStmt(body))
+              inlinedModules(name) = mx
+              mx
+            case m: ExtModule =>
+              inlinedModules(m.name) = m
+              m
          }
       }
 
diff --git a/src/main/scala/firrtl/passes/LowerTypes.scala b/src/main/scala/firrtl/passes/LowerTypes.scala
index 967b4a1c..70631cc3 100644
--- a/src/main/scala/firrtl/passes/LowerTypes.scala
+++ b/src/main/scala/firrtl/passes/LowerTypes.scala
@@ -112,7 +112,7 @@ object LowerTypes extends Pass {
           case None => mem
         }
         Seq(mergeRef(loMem, mergeRef(port, field)))
-      case name => error(s"Error! Unhandled memory field ${name}")(info, mname)
+      case name => error(s"Error! Unhandled memory field $name")(info, mname)
     }
   }
 
diff --git a/src/main/scala/firrtl/passes/PadWidths.scala b/src/main/scala/firrtl/passes/PadWidths.scala
index e0a2e304..9f1d906c 100644
--- a/src/main/scala/firrtl/passes/PadWidths.scala
+++ b/src/main/scala/firrtl/passes/PadWidths.scala
@@ -39,7 +39,7 @@ object PadWidths extends Pass {
       case Lt | Leq | Gt | Geq | Eq | Neq | Not | And | Or | Xor |
            Add | Sub | Mul | Div | Rem | Shr =>
         // sensitive ops
-        e map fixup((e.args map (width(_)) foldLeft 0)(math.max(_, _)))
+        e map fixup((e.args map width _ foldLeft 0)(math.max))
       case Dshl =>
         // special case as args aren't all same width
         e copy (op = Dshlw, args = Seq(fixup(width(e.tpe))(e.args.head), e.args(1)))
diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala
index 7b37cf65..a182b2af 100644
--- a/src/main/scala/firrtl/passes/Passes.scala
+++ b/src/main/scala/firrtl/passes/Passes.scala
@@ -204,7 +204,7 @@ object Legalize extends Pass {
         case SIntType(_) =>
           val bits = DoPrim(Bits, e.args, Seq(msb, msb), BoolType)
           DoPrim(AsSInt, Seq(bits), Seq.empty, SIntType(IntWidth(1)))
-        case t => error(s"Unsupported type ${t} for Primop Shift Right")
+        case t => error(s"Unsupported type $t for Primop Shift Right")
       }
     } else {
       e
diff --git a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
index 2c2e3fd6..8c158da9 100644
--- a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
+++ b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
@@ -119,24 +119,24 @@ object RemoveCHIRRTL extends Pass {
       val mem = DefMemory(s.info, s.name, s.tpe, s.size, 1, if (s.seq) 1 else 0,
                   rds map (_.name), wrs map (_.name), rws map (_.name))
       Block(mem +: stmts)
-    case (s: CDefMPort) => {
+    case (s: CDefMPort) =>
       types(s.name) = types(s.mem)
       val addrs = ArrayBuffer[String]()
       val clks = ArrayBuffer[String]()
       val ens = ArrayBuffer[String]()
       s.direction match {
         case MReadWrite =>
-          refs(s.name) = DataRef(SubField(Reference(s.mem, ut), s.name, ut), "rdata", "wdata", "wmask", true)
+          refs(s.name) = DataRef(SubField(Reference(s.mem, ut), s.name, ut), "rdata", "wdata", "wmask", rdwrite = true)
           addrs += "addr"
           clks += "clk"
           ens += "en"
         case MWrite =>
-          refs(s.name) = DataRef(SubField(Reference(s.mem, ut), s.name, ut), "data", "data", "mask", false)
+          refs(s.name) = DataRef(SubField(Reference(s.mem, ut), s.name, ut), "data", "data", "mask", rdwrite = false)
           addrs += "addr"
           clks += "clk"
           ens += "en"
         case MRead =>
-          refs(s.name) = DataRef(SubField(Reference(s.mem, ut), s.name, ut), "data", "data", "blah", false)
+          refs(s.name) = DataRef(SubField(Reference(s.mem, ut), s.name, ut), "data", "data", "blah", rdwrite = false)
           addrs += "addr"
           clks += "clk"
           s.exps.head match {
@@ -149,7 +149,6 @@ object RemoveCHIRRTL extends Pass {
         (addrs map (x => Connect(s.info, SubField(SubField(Reference(s.mem, ut), s.name, ut), x, ut), s.exps.head))) ++
         (clks map (x => Connect(s.info, SubField(SubField(Reference(s.mem, ut), s.name, ut), x, ut), s.exps(1)))) ++
         (ens map (x => Connect(s.info,SubField(SubField(Reference(s.mem,ut), s.name, ut), x, ut), one))))
-    }
     case (s) => s map collect_refs(mports, smems, types, refs, raddrs)
   }
 
diff --git a/src/main/scala/firrtl/passes/RemoveEmpty.scala b/src/main/scala/firrtl/passes/RemoveEmpty.scala
index 225e2222..3909eefd 100644
--- a/src/main/scala/firrtl/passes/RemoveEmpty.scala
+++ b/src/main/scala/firrtl/passes/RemoveEmpty.scala
@@ -13,5 +13,5 @@ object RemoveEmpty extends Pass {
       case m: ExtModule => m
     }
   }
-  def run(c: Circuit): Circuit = Circuit(c.info, c.modules.map(onModule _), c.main)
+  def run(c: Circuit): Circuit = Circuit(c.info, c.modules.map(onModule), c.main)
 }
diff --git a/src/main/scala/firrtl/passes/RemoveValidIf.scala b/src/main/scala/firrtl/passes/RemoveValidIf.scala
index e0a4b621..3b4daee2 100644
--- a/src/main/scala/firrtl/passes/RemoveValidIf.scala
+++ b/src/main/scala/firrtl/passes/RemoveValidIf.scala
@@ -23,5 +23,5 @@ object RemoveValidIf extends Pass {
       }
    }
 
-   def run(c: Circuit): Circuit = Circuit(c.info, c.modules.map(onModule _), c.main)
+   def run(c: Circuit): Circuit = Circuit(c.info, c.modules.map(onModule), c.main)
 }
diff --git a/src/main/scala/firrtl/passes/ReplSeqMem.scala b/src/main/scala/firrtl/passes/ReplSeqMem.scala
index 0933eefe..3b51d73f 100644
--- a/src/main/scala/firrtl/passes/ReplSeqMem.scala
+++ b/src/main/scala/firrtl/passes/ReplSeqMem.scala
@@ -49,7 +49,7 @@ class ConfWriter(filename: String) {
     val ports = (writers ++ readers ++ readwriters) mkString ","
     val maskGranConf = maskGran match { case None => "" case Some(p) => s"mask_gran $p" }
     val width = bitWidth(m.dataType)
-    val conf = s"name ${m.name} depth ${m.depth} width ${width} ports ${ports} ${maskGranConf} \n"
+    val conf = s"name ${m.name} depth ${m.depth} width $width ports $ports $maskGranConf \n"
     outputBuffer.append(conf)
   }
   def serialize() = {
diff --git a/src/main/scala/firrtl/passes/ReplaceSubAccess.scala b/src/main/scala/firrtl/passes/ReplaceAccesses.scala
index ce95be13..ce95be13 100644
--- a/src/main/scala/firrtl/passes/ReplaceSubAccess.scala
+++ b/src/main/scala/firrtl/passes/ReplaceAccesses.scala
diff --git a/src/main/scala/firrtl/passes/ReplaceMemMacros.scala b/src/main/scala/firrtl/passes/ReplaceMemMacros.scala
index 33a371a0..2342b193 100644
--- a/src/main/scala/firrtl/passes/ReplaceMemMacros.scala
+++ b/src/main/scala/firrtl/passes/ReplaceMemMacros.scala
@@ -85,8 +85,8 @@ class ReplaceMemMacros(writer: ConfWriter) extends Pass {
                      (s: Statement): Statement = s match {
     case m: DefMemory if containsInfo(m.info, "useMacro") => 
       if (!containsInfo(m.info, "maskGran")) {
-        m.writers foreach { w => memPortMap(s"${m.name}.${w}.mask") = EmptyExpression }
-        m.readwriters foreach { w => memPortMap(s"${m.name}.${w}.wmask") = EmptyExpression }
+        m.writers foreach { w => memPortMap(s"${m.name}.$w.mask") = EmptyExpression }
+        m.readwriters foreach { w => memPortMap(s"${m.name}.$w.wmask") = EmptyExpression }
       }
       val info = getInfo(m.info, "info") match {
         case None => NoInfo
@@ -118,7 +118,7 @@ class ReplaceMemMacros(writer: ConfWriter) extends Pass {
     val memMods = new Modules
     val modules = c.modules map updateMemMods(namespace, memMods)
     // print conf
-    writer.serialize
+    writer.serialize()
     c copy (modules = modules ++ memMods)
   }  
 }
diff --git a/src/main/scala/firrtl/passes/SplitExpressions.scala b/src/main/scala/firrtl/passes/SplitExpressions.scala
index 31306046..5c41a1f7 100644
--- a/src/main/scala/firrtl/passes/SplitExpressions.scala
+++ b/src/main/scala/firrtl/passes/SplitExpressions.scala
@@ -19,21 +19,18 @@ object SplitExpressions extends Pass {
         // Splits current expression if needed
         // Adds named temporaries to v
         def split(e: Expression): Expression = e match {
-          case e: DoPrim => {
+          case e: DoPrim =>
             val name = namespace.newTemp
             v += DefNode(get_info(s), name, e)
             WRef(name, e.tpe, kind(e), gender(e))
-          }
-          case e: Mux => {
+          case e: Mux =>
             val name = namespace.newTemp
             v += DefNode(get_info(s), name, e)
             WRef(name, e.tpe, kind(e), gender(e))
-          }
-          case e: ValidIf => {
+          case e: ValidIf =>
             val name = namespace.newTemp
             v += DefNode(get_info(s), name, e)
             WRef(name, e.tpe, kind(e), gender(e))
-          }
           case e => e
         }
 
diff --git a/src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala b/src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala
index 5b420591..675494b4 100644
--- a/src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala
+++ b/src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala
@@ -78,7 +78,7 @@ object MemTransformUtils {
       for ((p, i) <- ports.zipWithIndex; f <- fields) {
         val newPort = createSubField(createRef(m.name), portType+i)        
         val field = createSubField(newPort, f)
-        memPortMap(s"${m.name}.${p}.${f}") = field
+        memPortMap(s"${m.name}.$p.$f") = field
       }
     updateMemPortMap(m.readers, rFields, "R")
     updateMemPortMap(m.writers, wFields, "W")