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| author | chick | 2016-09-25 18:19:33 -0700 |
|---|---|---|
| committer | jackkoenig | 2016-09-27 13:06:52 -0700 |
| commit | 516339c30fd453ffa90dea6c0c255f84b0db567f (patch) | |
| tree | 18462b1c284e55afad8afb699461627a48cd8515 | |
| parent | 7478368f1701c329be06b0419c10dce6b640f997 (diff) | |
No return type for implicit function
| -rw-r--r-- | src/main/scala/firrtl/passes/VerilogMemDelays.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/VerilogMemDelays.scala b/src/main/scala/firrtl/passes/VerilogMemDelays.scala index 99f5b071..f6177606 100644 --- a/src/main/scala/firrtl/passes/VerilogMemDelays.scala +++ b/src/main/scala/firrtl/passes/VerilogMemDelays.scala @@ -39,7 +39,7 @@ object VerilogMemDelays extends Pass { def name = "Verilog Memory Delays" val ug = UNKNOWNGENDER type Netlist = collection.mutable.HashMap[String, Expression] - implicit def expToString(e: Expression) = e.serialize + implicit def expToString(e: Expression): String = e.serialize private def NOT(e: Expression) = DoPrim(Not, Seq(e), Nil, BoolType) private def AND(e1: Expression, e2: Expression) = DoPrim(And, Seq(e1, e2), Nil, BoolType) |
