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2021-05-04Fix SBT deprecation warnings (#2214)Jack Koenig
2021-03-09Create annotation to allow inline readmem in Verilog (#2107)Carlos Eduardo
This PR adds a new annotation allowing inline loading for memory files in Verilog code.
2020-07-13add .bloop and .metals to .gitignore (#1761)Albert Chen
* add .bloop and .metals to .gitignore * add project/metals.sbt to .gitignore
2020-06-09Refactor benchmark_code_compile.py to have job running utilityJack Koenig
This provides a common Python interfaces for monitoring resource usage of subprocesses Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-13Add new test jar to .gitignore (#1520)Albert Magyar
2020-02-13Mill support (#1368)Sequencer
2018-01-15WiringTransform Refactor (#648)Schuyler Eldridge
Massive refactoring to WiringTransform with the use of a new EulerTour class to speed things up via fast least common ancestor (LCA) queries. Changes include (but are not limited to): * Use lowest common ancestor when wiring * Add EulerTour class with naive and Berkman-Vishkin RMQ * Adds LCA method for Instance Graph * Enables "Two Sources" using "Top" wiring test as this is now valid * Remove TopAnnotation from WiringTransform * Represent WiringTransform sink as `Seq[Named]` * Remove WiringUtils.countInstances, fix imports * Support sources under sinks in WiringTransform * Enable internal module wiring * Support Wiring of Aggregates h/t @edcote fixes #728 Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Reviewed-by: Jack Koenig<jack.koenig3@gmail.com>
2017-07-26Flatten transformation (#631)Andrey Ayupov
* initial implementation of InlineDeepTransformation * rewrote transformation to not have any side effects in terms on inlining that was not annotated to be inlined * minor rewrites * renamed transformations to Flatten * fixes according to review * added more comments and fixed formating/style * fixed spacing, minor style fixes
2017-01-31Replace createTempDirectory with createTestDirectory (#427)Jack Koenig
Will place tests in ./test_run_dir/ instead of /tmp/
2016-10-17Add fixed point type (#322)Adam Izraelevitz
* WIP: Adding FixedType to Firrtl proper Got simple example running through width inference Checks should be ok Need to look into FixedLiteral more * Added simple test for fixed types * Added asFixedPoint to primops * Added tail case for FixedType * Added ConvertFixedToSInt.scala Added pass to MiddleToLowerFirrtl transform * Replace AsFixedType with AsSInt in fixed removal * Bugfix: constant from asFixed not deleted * Added unit test for bulk connect * Fixed partial connect bug #241 * Fixed missing case for FixedPoint in legalizeConnect * Add FixedMathSpec that demonstrates some problems with FixedPointMath * Fixed test and ConvertToSInt to pass. Negative binary points not easily supported, needs much more time to implement. * Refactored checking neg widths Make checking for negative binary points easier * Added tests for inferring many FixedType ops shl, shr, cat, bits, head, tail, setbp, shiftbp * Handle bpshl, bpshr, bpset in ConvertFixedToSInt Changed name from shiftbp -> bpshl, bpshr Change name from setbp -> bpset Added more tests * Added set binary point test that fails * Added simple test for zero binary point * gitignore fixes for antlr intermediate dir and intellij dir * removed unused imports retool the fixed point with zero binary point test * simplified example of inability to set binary point to zero * Temporary fix for zero-width binary point This fix allows for all widths to be zero, but since this is a feature I am working on next, I'm not going to bother with a more stringent check. * change version for dsp tools * Removed extra temporary file * Fixed merge bug * Fixed another merge bug * Removed commented out/unrelated files * Removed snake case
2016-02-09WIP. Got to-working-ir workingazidar
2016-01-16Ignore eclipse .projectducky
2016-01-16Default platform-agnostic, ignore platform-specific FileCheckducky
2016-01-16Added a bunch of tests and added firrtl-stanza and firrtl-scala to .gitignoreazidar
2015-10-08Install Stanza as a dependency of anything that uses itPalmer Dabbelt
This way I don't have to type "make install-linux" whenever a new Stanza zip drops.
2015-10-02Merged in Scala implementation of FIRRTL IR, parser, and serialization (ie. ↵Jack
AST -> String). Uses ANTLRv4 to generate concrete syntax parser
2015-08-26Added regression testazidar
2015-08-20Updated .gitignoreazidar
2015-05-18First pass at a Verilog Backend. Not tested, but compiles and generates ↵azidar
reasonable verilog. Requires inlining, future versions will instantiate modules
2015-05-02Added a infrastructure for check passes, and wrote a fewazidar
2015-04-20Fixed tests to use new execution arguments. Added and fixed chisel3 bugsazidar
2015-04-08Finished expand whens. started infer widths. added pdf for people to viewazidar
2015-03-04Finished infer-types passazidar
2015-02-24Updated tests, and included a check for the name of the pass, whichazidar
allows the compiler to print after each pass to ease debugging
2015-02-20Rewrote the initialize-register pass, now correctly implementedazidar
with a new IR construct - Null. LetRec is not implemented, but is marked with a TODO. Test cases for this pass are now located in test/passes/initialize-register
2015-02-19Added compiler flags to allow tests to select which passes they test.azidar
Changed package names from chipper to firrtl
2015-02-18Added more testing infrastructre, and Makefile to build firrtlazidar
2015-02-18Reimplemented to-working-ir. Changed Command to Stmt. Modified printing of ↵azidar
IR to match parser.
2015-02-13First commit.azidar
Added stanza as a .zip, changed names from ch to firrtl, and spec.tex is included. need to add installation instructions. TODO's included in README
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