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-rw-r--r--test/passes/expand-whens/bundle-init.fir27
-rw-r--r--test/passes/expand-whens/nested-whens.fir33
-rw-r--r--test/passes/expand-whens/partial-init.fir34
-rw-r--r--test/passes/expand-whens/reg-and-when.fir160
-rw-r--r--test/passes/expand-whens/reg-dwc.fir25
-rw-r--r--test/passes/expand-whens/reg-wdc.fir26
6 files changed, 0 insertions, 305 deletions
diff --git a/test/passes/expand-whens/bundle-init.fir b/test/passes/expand-whens/bundle-init.fir
deleted file mode 100644
index 333619d9..00000000
--- a/test/passes/expand-whens/bundle-init.fir
+++ /dev/null
@@ -1,27 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p cd 2>&1 | tee %s.out | FileCheck %s
-; CHECK: Expand Whens
-circuit top :
- module top :
- input clk : Clock
- input reset : UInt<1>
- wire w : { x : UInt, y : UInt}
- reg r : { x : UInt, y : UInt},clk with :
- reset => (reset,w)
- wire a : UInt
- wire b : UInt
- a <= UInt(1)
- b <= UInt(2)
-
- w.x <= b
- w.y <= a
- r.x <= a
- r.y <= b
-
-; CHECK: w.x <= b
-; CHECK: w.y <= a
-; CHECK: r.x <= a
-; CHECK: r.y <= b
-; CHECK: a <= UInt<1>("h1")
-; CHECK: b <= UInt<2>("h2")
-
-; CHECK: Finished Expand Whens
diff --git a/test/passes/expand-whens/nested-whens.fir b/test/passes/expand-whens/nested-whens.fir
deleted file mode 100644
index 68409931..00000000
--- a/test/passes/expand-whens/nested-whens.fir
+++ /dev/null
@@ -1,33 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-; CHECK: Expand Whens
-circuit top :
- module top :
- input clk : Clock
- input reset : UInt<1>
- wire p : UInt
- wire q : UInt
- wire a : UInt
- wire b : UInt
- wire x : UInt
- wire y : UInt
- wire z : UInt
- wire w : UInt
- reg r : UInt, clk with :
- reset => (reset, w)
- p <= UInt(1)
- q <= UInt(1)
- a <= UInt(1)
- b <= UInt(1)
- x <= UInt(1)
- y <= UInt(1)
- z <= UInt(1)
- w <= UInt(1)
-
- when p :
- r <= a
- when q :
- r <= b
- r <= z
-; CHECK: r <= z
-; CHECK: Finished Expand Whens
-; CHECK: Done!
diff --git a/test/passes/expand-whens/partial-init.fir b/test/passes/expand-whens/partial-init.fir
deleted file mode 100644
index 2fb54717..00000000
--- a/test/passes/expand-whens/partial-init.fir
+++ /dev/null
@@ -1,34 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-
-; CHECK: Expand Whens
-circuit top :
- module top :
- input clk : Clock
- input reset : UInt<1>
- poison x : UInt<1>
- wire init : UInt<1>[10]
- init[0] <= x
- init[1] <= x
- init[2] <= x
- init[3] <= UInt(3)
- init[4] <= x
- init[5] <= x
- init[6] <= x
- init[7] <= x
- init[8] <= x
- init[9] <= x
- reg r : UInt<1>[10],clk with :
- reset => (reset,init)
- r[0] <= UInt(1)
- r[1] <= UInt(1)
- r[2] <= UInt(1)
- r[3] <= UInt(1)
- r[4] <= UInt(1)
- r[5] <= UInt(1)
- r[6] <= UInt(1)
- r[7] <= UInt(1)
- r[8] <= UInt(1)
- r[9] <= UInt(1)
-
-; CHECK: Finished Expand Whens
-; CHECK: Done!
diff --git a/test/passes/expand-whens/reg-and-when.fir b/test/passes/expand-whens/reg-and-when.fir
deleted file mode 100644
index 97b96735..00000000
--- a/test/passes/expand-whens/reg-and-when.fir
+++ /dev/null
@@ -1,160 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p cd 2>&1 | tee %s.out ; cat %s.v | FileCheck %s
-; CHECK: out__slow__bits <= fromhost__q$deq$valid ? fromhost__q$deq$bits : tohost__q$deq$bits;
-circuit Top :
- module Top :
- input clock : Clock
- input reset : UInt<1>
- input out_fast : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}
- output out_slow : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}
- output in_fast : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}
- input in_slow : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}
- output clk_slow : UInt<1>
- input set_divisor : {valid : UInt<1>, bits : UInt<32>}
- output divisor : UInt<32>
-
- out_fast.ready <= UInt<1>("h00")
- out_slow.bits <= UInt<1>("h00")
- out_slow.valid <= UInt<1>("h00")
- in_fast.bits <= UInt<1>("h00")
- in_fast.valid <= UInt<1>("h00")
- in_slow.ready <= UInt<1>("h00")
- clk_slow <= UInt<1>("h00")
- divisor <= UInt<1>("h00")
-
- inst fromhost_q of Queue_50
- fromhost_q.reset <= UInt<1>("h00")
- fromhost_q.enq.bits <= UInt<1>("h00")
- fromhost_q.enq.valid <= UInt<1>("h00")
- fromhost_q.deq.ready <= UInt<1>("h00")
- fromhost_q.clock <= clock
- fromhost_q.reset <= reset
-
- inst tohost_q of Queue_51
- tohost_q.reset <= UInt<1>("h00")
- tohost_q.enq.bits <= UInt<1>("h00")
- tohost_q.enq.valid <= UInt<1>("h00")
- tohost_q.deq.ready <= UInt<1>("h00")
- tohost_q.clock <= clock
- tohost_q.reset <= reset
-
- reg out_slow_bits : UInt<17>, clock, reset
- out_slow_bits <= tohost_q.deq.bits
- when fromhost_q.deq.valid :
- out_slow_bits <= fromhost_q.deq.bits
-
- module Queue_50 :
- input clock : Clock
- input reset : UInt<1>
- input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}
- output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}
- output count : UInt<1>
-
- enq.ready <= UInt<1>("h00")
- deq.bits <= UInt<1>("h00")
- deq.valid <= UInt<1>("h00")
- count <= UInt<1>("h00")
-
- cmem ram : UInt<17>[1], clock
- reg maybe_full : UInt<1>, clock, reset
- onreset maybe_full <= UInt<1>("h00")
- node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00"))
- node T_115167 = eq(maybe_full, UInt<1>("h00"))
- node empty = and(ptr_match, T_115167)
- node full = and(ptr_match, maybe_full)
- node maybe_flow = and(UInt<1>("h00"), empty)
- node do_flow = and(maybe_flow, deq.ready)
- node T_115173 = and(enq.ready, enq.valid)
- node T_115175 = eq(do_flow, UInt<1>("h00"))
- node do_enq = and(T_115173, T_115175)
- node T_115177 = and(deq.ready, deq.valid)
- node T_115179 = eq(do_flow, UInt<1>("h00"))
- node do_deq = and(T_115177, T_115179)
- when do_enq :
- infer accessor T_115181 = ram[UInt<1>("h00")]
- T_115181 <= enq.bits
- skip
- when do_deq :
- skip
- node T_115184 = neq(do_enq, do_deq)
- when T_115184 :
- maybe_full <= do_enq
- skip
- node T_115186 = eq(empty, UInt<1>("h00"))
- node T_115188 = and(UInt<1>("h00"), enq.valid)
- node T_115189 = or(T_115186, T_115188)
- deq.valid <= T_115189
- node T_115191 = eq(full, UInt<1>("h00"))
- node T_115193 = and(UInt<1>("h00"), deq.ready)
- node T_115194 = or(T_115191, T_115193)
- enq.ready <= T_115194
- infer accessor T_115195 = ram[UInt<1>("h00")]
- wire T_115197 : UInt<17>
- T_115197 <= T_115195
- when maybe_flow :
- T_115197 <= enq.bits
- skip
- deq.bits <= T_115197
- node ptr_diff = subw(UInt<1>("h00"), UInt<1>("h00"))
- node T_115199 = and(maybe_full, ptr_match)
- node T_115200 = T_115199
- node T_115201 = cat(T_115200, ptr_diff)
- count <= T_115201
-
- module Queue_51 :
- input clock : Clock
- input reset : UInt<1>
- input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}
- output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}
- output count : UInt<1>
-
- enq.ready <= UInt<1>("h00")
- deq.bits <= UInt<1>("h00")
- deq.valid <= UInt<1>("h00")
- count <= UInt<1>("h00")
-
- cmem ram : UInt<17>[1], clock
- reg maybe_full : UInt<1>, clock, reset
- onreset maybe_full <= UInt<1>("h00")
- node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00"))
- node T_115235 = eq(maybe_full, UInt<1>("h00"))
- node empty = and(ptr_match, T_115235)
- node full = and(ptr_match, maybe_full)
- node maybe_flow = and(UInt<1>("h00"), empty)
- node do_flow = and(maybe_flow, deq.ready)
- node T_115241 = and(enq.ready, enq.valid)
- node T_115243 = eq(do_flow, UInt<1>("h00"))
- node do_enq = and(T_115241, T_115243)
- node T_115245 = and(deq.ready, deq.valid)
- node T_115247 = eq(do_flow, UInt<1>("h00"))
- node do_deq = and(T_115245, T_115247)
- when do_enq :
- infer accessor T_115249 = ram[UInt<1>("h00")]
- T_115249 <= enq.bits
- skip
- when do_deq :
- skip
- node T_115252 = neq(do_enq, do_deq)
- when T_115252 :
- maybe_full <= do_enq
- skip
- node T_115254 = eq(empty, UInt<1>("h00"))
- node T_115256 = and(UInt<1>("h00"), enq.valid)
- node T_115257 = or(T_115254, T_115256)
- deq.valid <= T_115257
- node T_115259 = eq(full, UInt<1>("h00"))
- node T_115261 = and(UInt<1>("h00"), deq.ready)
- node T_115262 = or(T_115259, T_115261)
- enq.ready <= T_115262
- infer accessor T_115263 = ram[UInt<1>("h00")]
- wire T_115265 : UInt<17>
- T_115265 <= T_115263
- when maybe_flow :
- T_115265 <= enq.bits
- skip
- deq.bits <= T_115265
- node ptr_diff = subw(UInt<1>("h00"), UInt<1>("h00"))
- node T_115267 = and(maybe_full, ptr_match)
- node T_115268 = T_115267
- node T_115269 = cat(T_115268, ptr_diff)
- count <= T_115269
-
diff --git a/test/passes/expand-whens/reg-dwc.fir b/test/passes/expand-whens/reg-dwc.fir
deleted file mode 100644
index 6713b1f2..00000000
--- a/test/passes/expand-whens/reg-dwc.fir
+++ /dev/null
@@ -1,25 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-circuit top :
- module top :
- input clk : Clock
- input reset : UInt<1>
- wire p : UInt
- p <= UInt(1)
- reg r : UInt,clk with :
- reset => (reset,r)
- when p :
- r <= UInt(2)
-
-; CHECK: Expand Whens
-
-; CHECK: circuit top :
-; CHECK: module top :
-; CHECK: wire p : UInt
-; CHECK: reg r : UInt
-; CHECK: p <= UInt<1>("h1")
-; CHECK: r <= mux(p, UInt<2>("h2"), r)
-
-; CHECK: Finished Expand Whens
-
-; CHECK: Done!
-
diff --git a/test/passes/expand-whens/reg-wdc.fir b/test/passes/expand-whens/reg-wdc.fir
deleted file mode 100644
index 6e8e7c04..00000000
--- a/test/passes/expand-whens/reg-wdc.fir
+++ /dev/null
@@ -1,26 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-circuit top :
- module top :
- input clk : Clock
- input reset : UInt<1>
- wire p : UInt
- p <= UInt(1)
- when p :
- reg r : UInt,clk with :
- reset => (reset,r)
- r <= UInt(2)
-
-; CHECK: Expand Whens
-
-; CHECK: circuit top :
-; CHECK: module top :
-; CHECK: wire p : UInt
-; CHECK: reg r : UInt<2>, clk with :
-; CHECK: reset => (reset, r)
-; CHECK: p <= UInt<1>("h1")
-; CHECK-NOT: r <= mux(p, UInt<2>("h2"), r)
-; CHECK: r <= UInt<2>("h2")
-
-; CHECK: Finished Expand Whens
-
-; CHECK: Done!
generated by cgit v1.2.3 (git 2.25.1) at 2026-03-09 03:53:40 +0000