diff options
Diffstat (limited to 'src/main/stanza')
| -rw-r--r-- | src/main/stanza/bigint2.stanza | 228 | ||||
| -rw-r--r-- | src/main/stanza/chirrtl.stanza | 463 | ||||
| -rw-r--r-- | src/main/stanza/compilers.stanza | 235 | ||||
| -rw-r--r-- | src/main/stanza/custom-compiler.stanza | 71 | ||||
| -rw-r--r-- | src/main/stanza/custom-passes.stanza | 248 | ||||
| -rw-r--r-- | src/main/stanza/errors.stanza | 1032 | ||||
| -rw-r--r-- | src/main/stanza/firrtl-ir.stanza | 238 | ||||
| -rw-r--r-- | src/main/stanza/firrtl-lexer.stanza | 596 | ||||
| -rw-r--r-- | src/main/stanza/firrtl-main.stanza | 57 | ||||
| -rw-r--r-- | src/main/stanza/firrtl-test-main.stanza | 177 | ||||
| -rw-r--r-- | src/main/stanza/firrtl.stanza | 45 | ||||
| -rw-r--r-- | src/main/stanza/flo.stanza | 228 | ||||
| -rw-r--r-- | src/main/stanza/ir-parser.stanza | 409 | ||||
| -rw-r--r-- | src/main/stanza/ir-utils.stanza | 981 | ||||
| -rw-r--r-- | src/main/stanza/passes.stanza | 2930 | ||||
| -rw-r--r-- | src/main/stanza/primop.stanza | 280 | ||||
| -rw-r--r-- | src/main/stanza/symbolic-value.stanza | 95 | ||||
| -rw-r--r-- | src/main/stanza/widthsolver.stanza | 322 |
18 files changed, 0 insertions, 8635 deletions
diff --git a/src/main/stanza/bigint2.stanza b/src/main/stanza/bigint2.stanza deleted file mode 100644 index e64cd9b6..00000000 --- a/src/main/stanza/bigint2.stanza +++ /dev/null @@ -1,228 +0,0 @@ -;Copyright (c) 2014 - 2016 The Regents of the University of -;California (Regents). All Rights Reserved. Redistribution and use in -;source and binary forms, with or without modification, are permitted -;provided that the following conditions are met: -; * Redistributions of source code must retain the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer. -; * Redistributions in binary form must reproduce the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer in the documentation and/or other materials -; provided with the distribution. -; * Neither the name of the Regents nor the names of its contributors -; may be used to endorse or promote products derived from this -; software without specific prior written permission. -;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, -;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF -;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT -;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF -;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION -;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR -;MODIFICATIONS. - -defpackage bigint2 : - import core - import verse - -;============ Big Int Library ============= - -; d contains the Array<Int>, stored so the least significant word is at -; index 0. - -;------------ Helper Functions ------------ -public defn pow (x:Int,y:Int) -> Int : - var x* = 1 - var y* = y - while y* != 0 : - x* = times(x*,x) - y* = minus(y*,1) - x* - -public defn pow (x:Long,y:Long) -> Long : - var x* = to-long(1) - var y* = y - while y* != to-long(0) : - x* = times(x*,x) - y* = minus(y*,to-long(1)) - x* -public defn to-int (x:Long) -> Int : - if x > to-long(2147483647) or x < to-long(-2147483648) : error("Long too big to convert to Int") - else : to-int(to-string(x)) - -public defn to-int (x:BigInt) -> Int : - if length(d(x)) > 1 : error("BigInt too big to convert to Int") - else : d(x)[0] - -public defn req-num-bits (i: Int) -> Int : - val i* = - if i < 0 : ((-1 * i) - 1) - else : i - ceil-log2(i* + 1) + 1 -val word-size = 32 -val all-digits = "0123456789abcdef" - -defn as-digit (c: Char) -> Int : - index-of(all-digits, c) as Int - -defn num-words (b:BigInt) : length(d(b)) - -defn shamt (c:Char) : - if c == 'b': 1 - else if c == 'h': 4 - else: error("Unsupported BigInt base.") - -defn req-words (num-bits:Int) : (num-bits + word-size - 1) / word-size - -defn to-hex (b:BigInt) -> String : - defn as-hex (i: Int) -> String : substring(all-digits,i,i + 1) - var li = List<String>() - val tib = num-bits(b) % 4 - for i in 0 to num-bits(b) by 4 do : - val word-index = i / 32 - val bit-index = i % 32 - var mask = 15 - - val digit = - if (i + tib) == num-bits(b) : - (d(b)[word-index] >> bit-index) & (pow(2,tib) - 1) - else : - (d(b)[word-index] >> bit-index) & 15 - li = List(as-hex(digit),li) - var saw-not-zero? = false - val li* = Vector<String>() - for i in 0 to length(li) do : - val x = li[i] - if saw-not-zero? == false and x == "0" and i < length(li) - 1 : false - else : - saw-not-zero? = true - add(li*,x) - - string-join([ '\"' 'h' string-join(li*) '\"']) - -defn to-bin (b:BigInt) -> String : - string-join $ generate<Char> : - defn* loop (pos:Int) : - if (pos >= 0) : - yield(if (d(b)[pos / 32] >> (pos % 32))&1 == 1: '1' else: '0') - loop(pos - 1) - loop(num-bits(b) - 1) - -defn check-index (index:Int) -> False : - if index < 0 : error("Bit index cannot be negative") - false - -defn check-bit (bit:Int) -> False : - if bit != 0 and bit != 1 : error("Cannot set a bit other than 0 or 1") - -;------------ Library ---------------- -public defstruct BigInt <: Gettable & Settable : - d : Array<Int> - num-bits : Int -with : - constructor => #BigInt - -public defn BigInt (d:Array<Int>, num-bits:Int) : - check-index(num-bits) - if num-bits > length(d) * word-size : - error("Number of bits greater than size of BigInt") - val msw-index = req-words(num-bits) - 1 - val msb-index = num-bits % word-size - ;Zero out all bits above num-bits - if msb-index != 0 : - d[msw-index] = d[msw-index] & (2 ^ msb-index - 1) - for x in (msw-index + 1) to length(d) do : - d[msw-index] = 0 - #BigInt(d,num-bits) - -public defmethod get (b:BigInt, index:Int) -> Int : - check-index(index) - if index >= num-bits(b) : error("Bit index is too high") - val word-index = index / 32 - val bit-index = index % 32 - (d(b)[word-index] >> bit-index) & 1 - -defmethod set (b:BigInt, index:Int, bit:Int) -> False : - check-index(index) - check-bit(bit) - val word-index = index / 32 - val bit-index = index % 32 - d(b)[word-index] = ((bit & 1) << bit-index) | d(b)[word-index] - -public defmethod to-string (b:BigInt) : to-hex(b) - ;string-join([to-hex(b) "'" num-bits(b)]) - -public defmethod print (o:OutputStream, b:BigInt) : - print(o, to-string(b)) - -public defn req-num-bits (b:BigInt) -> Int : - var msb = 0 - var seen? = false - for i in 0 to num-bits(b) do : - val index = num-bits(b) - 1 - i - if b[index] != 0 and seen? == false : - msb = index - seen? = true - msb + 1 - -public defn BigIntZero (num-bits:Int) -> BigInt : - val num-words = (num-bits + word-size - 1) / word-size - val d = Array<Int>(num-words) - for i in 0 to length(d) do : - d[i] = 0 - BigInt(d,num-bits) - -public defn BigIntLit (data:Int) -> BigInt : - BigIntLit(data,req-num-bits(data)) - -public defn BigIntLit (data:Int, num-bits:Int) -> BigInt : - val b = BigIntZero(num-bits) - d(b)[0] = data - b - -public defn BigIntLit (data:String) -> BigInt : - val num-bits = (length(data) - 1) * shamt(data[0]) - BigIntLit(data,num-bits) - -public defn BigIntLit (data:String, num-bits:Int) -> BigInt : - val lit = BigIntZero(num-bits) - val digits = substring(data, 1) - ;; println-all(["BASE " base " SHAMT " shamt " DIGITS " digits]) - for i in 0 to num-words(lit) do : - d(lit)[i] = 0 - for i in 0 to length(digits) do : - val off = (length(digits) - 1 - i) * shamt(data[0]) - val wi = off / word-size - val bi = off % word-size - d(lit)[wi] = d(lit)[wi] | (as-digit(digits[i]) << bi) - ;; println-all(["OFF " off " wi " wi " bi " bi " lit[wi] " lit[wi] " => " lit]) - ;; println-all(["RES = " lit]) - lit - -;------------------- Library API ----------------- - - -;High is NOT inclusive -public defn bits (b:BigInt, high:Int, low:Int) -> BigInt : - check-index(high) - check-index(low) - if high <= low : error("High bit is less than or equal to low bit") - val b* = BigIntZero(high - low) - for i in 0 to num-bits(b*) do : - b*[i] = b[i + low] - b* - -public defn bit (b:BigInt, index:Int) -> BigInt : - check-index(index) - val b* = BigIntZero(1) - b*[0] = b[index] - b* - -public defn rsh (b:BigInt, amount:Int) -> BigInt : - check-index(amount) - bits(b,num-bits(b), amount) - - - diff --git a/src/main/stanza/chirrtl.stanza b/src/main/stanza/chirrtl.stanza deleted file mode 100644 index 43e6d2d6..00000000 --- a/src/main/stanza/chirrtl.stanza +++ /dev/null @@ -1,463 +0,0 @@ -;Copyright (c) 2014 - 2016 The Regents of the University of -;California (Regents). All Rights Reserved. Redistribution and use in -;source and binary forms, with or without modification, are permitted -;provided that the following conditions are met: -; * Redistributions of source code must retain the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer. -; * Redistributions in binary form must reproduce the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer in the documentation and/or other materials -; provided with the distribution. -; * Neither the name of the Regents nor the names of its contributors -; may be used to endorse or promote products derived from this -; software without specific prior written permission. -;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, -;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF -;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT -;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF -;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION -;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR -;MODIFICATIONS. -defpackage firrtl/chirrtl : - import core - import verse - import firrtl/ir2 - import firrtl/ir-utils - import firrtl/primops - - -; =============================== -public val chirrtl-passes = to-list $ [ - CInferTypes() - CInferMDir() - RemoveCHIRRTL() - FromCHIRRTL() -] -; =============================== - - -; CHIRRTL Additional IR Nodes -public definterface MPortDir -public val MInfer = new MPortDir -public val MRead = new MPortDir -public val MWrite = new MPortDir -public val MReadWrite = new MPortDir - -defmethod print (o:OutputStream, m:MPortDir) : - switch { m == _ } : - MInfer : print(o,"infer") - MRead : print(o,"read") - MWrite : print(o,"write") - MReadWrite : print(o,"rdwr") - -public defstruct CDefMemory <: Stmt : ;LOW - info: FileInfo with: (as-method => true) - name: Symbol - type: Type - size: Int - seq?: True|False -public defstruct CDefMPort <: Stmt : - info: FileInfo with: (as-method => true) - name: Symbol - type: Type - mem: Symbol - exps: List<Expression> - direction: MPortDir - -defmethod print (o:OutputStream,c:CDefMemory) : - if seq?(c) : print-all(o, ["smem " name(c) " : " type(c) "[" size(c) "]"]) - else : print-all(o, ["cmem " name(c) " : " type(c) "[" size(c) "]"]) -defmethod map (f: Type -> Type, c:CDefMemory) -> CDefMemory : - CDefMemory(info(c),name(c),f(type(c)),size(c),seq?(c)) -defmethod map (f: Symbol -> Symbol, c:CDefMemory) -> CDefMemory : - CDefMemory(info(c),f(name(c)),type(c),size(c),seq?(c)) - -defmethod print (o:OutputStream,c:CDefMPort) : - print-all(o, [direction(c) " mport " name(c) " = " mem(c) "[" exps(c)[0] "], " exps(c)[1]]) -defmethod map (f: Expression -> Expression, c:CDefMPort) -> CDefMPort : - CDefMPort(info(c),name(c),type(c),mem(c),map(f,exps(c)),direction(c)) -defmethod map (f: Type -> Type, c:CDefMPort) -> CDefMPort : - CDefMPort(info(c),name(c),f(type(c)),mem(c),exps(c),direction(c)) -defmethod map (f: Symbol -> Symbol, c:CDefMPort) -> CDefMPort : - CDefMPort(info(c),f(name(c)),type(c),mem(c),exps(c),direction(c)) - - -;======================= Infer Chirrtl Types ====================== -public defstruct CInferTypes <: Pass -public defmethod pass (b:CInferTypes) -> (Circuit -> Circuit) : infer-types -public defmethod name (b:CInferTypes) -> String : "CInfer Types" -public defmethod short-name (b:CInferTypes) -> String : "cinfertypes" - -;--------------- Utils ----------------- - -defn set-type (s:Stmt,t:Type) -> Stmt : - match(s) : - (s:DefWire) : DefWire(info(s),name(s),t) - (s:DefRegister) : DefRegister(info(s),name(s),t,clock(s),reset(s),init(s)) - (s:CDefMemory) : CDefMemory(info(s),name(s),t,size(s),seq?(s)) - (s:CDefMPort) : CDefMPort(info(s),name(s),t,mem(s),exps(s),direction(s)) - (s:DefNode) : s - (s:DefPoison) : DefPoison(info(s),name(s),t) - -defn to-field (p:Port) -> Field : - if direction(p) == OUTPUT : Field(name(p),DEFAULT,type(p)) - else if direction(p) == INPUT : Field(name(p),REVERSE,type(p)) - else : error("Shouldn't be here") -defn module-type (m:Module) -> Type : - BundleType(for p in ports(m) map : to-field(p)) -defn field-type (v:Type,s:Symbol) -> Type : - match(v) : - (v:BundleType) : - val ft = for p in fields(v) find : name(p) == s - if ft != false : type(ft as Field) - else : UnknownType() - (v) : UnknownType() -defn sub-type (v:Type) -> Type : - match(v) : - (v:VectorType) : type(v) - (v) : UnknownType() - -;--------------- Pass ----------------- - -defn infer-types (c:Circuit) -> Circuit : - val module-types = HashTable<Symbol,Type>(symbol-hash) - defn infer-types (m:Module) -> Module : - val types = HashTable<Symbol,Type>(symbol-hash) - defn infer-types-e (e:Expression) -> Expression : - match(map(infer-types-e,e)) : - (e:Ref) : Ref(name(e), get?(types,name(e),UnknownType())) - (e:SubField) : SubField(exp(e),name(e),field-type(type(exp(e)),name(e))) - (e:SubIndex) : SubIndex(exp(e),value(e),sub-type(type(exp(e)))) - (e:SubAccess) : SubAccess(exp(e),index(e),sub-type(type(exp(e)))) - (e:DoPrim) : set-primop-type(e) - (e:Mux) : Mux(cond(e),tval(e),fval(e),mux-type(tval(e),tval(e))) - (e:ValidIf) : ValidIf(cond(e),value(e),type(value(e))) - (e:UIntValue|SIntValue) : e - defn infer-types-s (s:Stmt) -> Stmt : - match(s) : - (s:DefRegister) : - types[name(s)] = type(s) - map(infer-types-e,s) - s - (s:DefWire|DefPoison) : - types[name(s)] = type(s) - s - (s:DefNode) : - val s* = map(infer-types-e,s) - val t = type(value(s*)) - types[name(s*)] = t - s* - (s:DefMemory) : - types[name(s)] = get-type(s) - s - (s:CDefMPort) : - val t = get?(types,mem(s),UnknownType()) - types[name(s)] = t - CDefMPort(info(s),name(s),t,mem(s),exps(s),direction(s)) - (s:CDefMemory) : - types[name(s)] = type(s) - s - (s:DefInstance) : - types[name(s)] = get?(module-types,module(s),UnknownType()) - s - (s) : map{infer-types-e,_} $ map(infer-types-s,s) - for p in ports(m) do : - types[name(p)] = type(p) - match(m) : - (m:InModule) : - InModule(info(m),name(m),ports(m),infer-types-s(body(m))) - (m:ExModule) : m - - ; MAIN - for m in modules(c) do : - module-types[name(m)] = module-type(m) - Circuit{info(c), _, main(c) } $ - for m in modules(c) map : - infer-types(m) - -;========================================== - -public defstruct CInferMDir <: Pass -public defmethod pass (b:CInferMDir) -> (Circuit -> Circuit) : infer-mdir -public defmethod name (b:CInferMDir) -> String : "CInfer MDir" -public defmethod short-name (b:CInferMDir) -> String : "cinfermdir" - -defn infer-mdir (c:Circuit) -> Circuit : - defn infer-mdir (m:Module) -> Module : - val mports = HashTable<Symbol,MPortDir>(symbol-hash) - defn infer-mdir-e (e:Expression,dir:MPortDir) -> Expression : - match(map(infer-mdir-e{_,dir},e)) : - (e:Ref) : - if key?(mports,name(e)) : - val new_mport_dir = - switch fn ([x,y]) : mports[name(e)] == x and dir == y : - [MInfer,MInfer] : error("Shouldn't be here") - [MInfer,MWrite] : MWrite - [MInfer,MRead] : MRead - [MInfer,MReadWrite] : MReadWrite - [MWrite,MInfer] : error("Shouldn't be here") - [MWrite,MWrite] : MWrite - [MWrite,MRead] : MReadWrite - [MWrite,MReadWrite] : MReadWrite - [MRead,MInfer] : error("Shouldn't be here") - [MRead,MWrite] : MReadWrite - [MRead,MRead] : MRead - [MRead,MReadWrite] : MReadWrite - [MReadWrite,MInfer] : error("Shouldn't be here") - [MReadWrite,MWrite] : MReadWrite - [MReadWrite,MRead] : MReadWrite - [MReadWrite,MReadWrite] : MReadWrite - mports[name(e)] = new_mport_dir - e - (e) : e - defn infer-mdir-s (s:Stmt) -> Stmt : - match(s) : - (s:CDefMPort) : - mports[name(s)] = direction(s) - map(infer-mdir-e{_,MRead},s) - (s:Connect|BulkConnect) : - infer-mdir-e(exp(s),MRead) - infer-mdir-e(loc(s),MWrite) - s - (s) : map{infer-mdir-e{_,MRead},_} $ map(infer-mdir-s,s) - defn set-mdir-s (s:Stmt) -> Stmt : - match(s) : - (s:CDefMPort) : - CDefMPort(info(s),name(s),type(s),mem(s),exps(s),mports[name(s)]) - (s) : map(set-mdir-s,s) - match(m) : - (m:InModule) : - infer-mdir-s(body(m)) - InModule(info(m),name(m),ports(m),set-mdir-s(body(m))) - (m:ExModule) : m - - ; MAIN - Circuit{info(c), _, main(c) } $ - for m in modules(c) map : - infer-mdir(m) - -;========================================== -public defstruct RemoveCHIRRTL <: Pass -public defmethod pass (b:RemoveCHIRRTL) -> (Circuit -> Circuit) : remove-chirrtl -public defmethod name (b:RemoveCHIRRTL) -> String : "Remove CHIRRTL" -public defmethod short-name (b:RemoveCHIRRTL) -> String : "removechirrtl" - -defstruct MPort : - name : Symbol - clk : Expression -defstruct MPorts : - readers : Vector<MPort> - writers : Vector<MPort> - readwriters : Vector<MPort> -defstruct DataRef : - exp : Expression - male : Symbol - female : Symbol - mask : Symbol - rdwrite? : True|False - -public definterface Gender -public val MALE = new Gender -public val FEMALE = new Gender - -defn create-exps (e:Expression) -> List<Expression> : - match(e) : - (e:Mux) : - for (e1 in create-exps(tval(e)), e2 in create-exps(fval(e))) map : - Mux(cond(e),e1,e2,mux-type(e1,e2)) - (e:ValidIf) : - for e1 in create-exps(value(e)) map : - ValidIf(cond(e),e1,type(e1)) - (e) : - match(type(e)) : - (t:UIntType|SIntType|ClockType) : list(e) - (t:BundleType) : - for f in fields(t) map-append : - create-exps(SubField(e,name(f),type(f))) - (t:VectorType) : - for i in 0 to size(t) map-append : - create-exps(SubIndex(e,i,type(t))) - (t:UnknownType) : list(e) - -defn remove-chirrtl (c:Circuit) : - defn remove-chirrtl-m (m:InModule) -> InModule : - val hash = HashTable<Symbol,MPorts>(symbol-hash) - val sh = get-sym-hash(m,keys(v-keywords)) - val repl = HashTable<Symbol,DataRef>(symbol-hash) - val ut = UnknownType() - val mport-types = HashTable<Symbol,Type>(symbol-hash) - defn EMPs () -> MPorts : - MPorts(Vector<MPort>(),Vector<MPort>(),Vector<MPort>()) - defn collect-mports (s:Stmt) -> Stmt : - match(s) : - (s:CDefMPort) : - val mports = get?(hash,mem(s),EMPs()) - switch { _ == direction(s) } : - MRead : add(readers(mports),MPort(name(s),exps(s)[1])) - MWrite : add(writers(mports),MPort(name(s),exps(s)[1])) - MReadWrite : add(readwriters(mports),MPort(name(s),exps(s)[1])) - hash[mem(s)] = mports - s - (s) : map(collect-mports,s) - defn collect-refs (s:Stmt) -> Stmt : - match(s) : - (s:CDefMemory) : - mport-types[name(s)] = type(s) - val stmts = Vector<Stmt>() - ;val naddr = firrtl-gensym(`GEN,sh) - val taddr = UIntType(IntWidth(max(1,ceil-log2(size(s))))) - ;add(stmts,DefPoison(info(s),naddr,taddr)) - ;val ndata = firrtl-gensym(`GEN,sh) - val tdata = type(s) - ;add(stmts,DefPoison(info(s),ndata,tdata)) - defn set-poison (vec:List<MPort>,addr:Symbol) -> False : - for r in vec do : - add(stmts,IsInvalid(info(s),SubField(SubField(Ref(name(s),ut),name(r),ut),addr,taddr))) - add(stmts,Connect(info(s),SubField(SubField(Ref(name(s),ut),name(r),ut),`clk,taddr),clk(r))) - defn set-enable (vec:List<MPort>,en:Symbol) -> False: - for r in vec do : - add(stmts,Connect(info(s),SubField(SubField(Ref(name(s),ut),name(r),ut),en,taddr),zero)) - defn set-wmode (vec:List<MPort>,wmode:Symbol) -> False: - for r in vec do : - add(stmts,Connect(info(s),SubField(SubField(Ref(name(s),ut),name(r),ut),wmode,taddr),zero)) - defn set-write (vec:List<MPort>,data:Symbol,mask:Symbol) -> False : - val tmask = create-mask(type(s)) - for r in vec do : - add(stmts,IsInvalid(info(s),SubField(SubField(Ref(name(s),ut),name(r),ut),data,tdata))) - for x in create-exps(SubField(SubField(Ref(name(s),ut),name(r),ut),mask,tmask)) do : - add(stmts,Connect(info(s),x,zero)) - - val rds = to-list $ readers $ get?(hash,name(s),EMPs()) - set-poison(rds,`addr) - set-enable(rds,`en) - val wrs = to-list $ writers $ get?(hash,name(s),EMPs()) - set-poison(wrs,`addr) - set-enable(wrs,`en) - set-write(wrs,`data,`mask) - val rws = to-list $ readwriters $ get?(hash,name(s),EMPs()) - set-poison(rws,`addr) - set-wmode(rws,`wmode) - set-enable(rws,`en) - set-write(rws,`data,`mask) - val read-l = - if seq?(s) : 1 - else : 0 - val mem = DefMemory(info(s),name(s),type(s),size(s),1,read-l,map(name,rds),map(name,wrs),map(name,rws)) - Begin $ List(mem,to-list(stmts)) - (s:CDefMPort) : - mport-types[name(s)] = mport-types[mem(s)] - val addrs = Vector<Symbol>() - val ens = Vector<Symbol>() - val masks = Vector<Symbol>() - switch { _ == direction(s) } : - MReadWrite : - repl[name(s)] = DataRef(SubField(Ref(mem(s),ut),name(s),ut),`rdata,`data,`mask,true) - add(addrs,`addr) - add(ens,`en) - add(masks,`mask) - MWrite : - repl[name(s)] = DataRef(SubField(Ref(mem(s),ut),name(s),ut),`data,`data,`mask,false) - add(addrs,`addr) - add(ens,`en) - add(masks,`mask) - else : - repl[name(s)] = DataRef(SubField(Ref(mem(s),ut),name(s),ut),`data,`data,`blah,false) - add(addrs,`addr) - add(ens,`en) - - val stmts = Vector<Stmt>() - for x in addrs do : - add(stmts,Connect(info(s),SubField(SubField(Ref(mem(s),ut),name(s),ut),x,ut),exps(s)[0])) - for x in ens do : - add(stmts,Connect(info(s),SubField(SubField(Ref(mem(s),ut),name(s),ut),x,ut),one)) - Begin $ to-list $ stmts - (s) : map(collect-refs,s) - defn remove-chirrtl-s (s:Stmt) -> Stmt : - var has-write-mport? = false - var has-readwrite-mport? = false - defn remove-chirrtl-e (e:Expression,g:Gender) -> Expression : - match(e) : - (e:Ref) : - if key?(repl,name(e)) : - val vt = repl[name(e)] - switch {g == _ }: - MALE : SubField(exp(vt),male(vt),type(e)) - FEMALE : - has-write-mport? = true - if rdwrite?(vt) == true : - has-readwrite-mport? = SubField(exp(vt),`wmode,UIntType(IntWidth(1))) - SubField(exp(vt),female(vt),type(e)) - else : e - (e:SubAccess) : SubAccess(remove-chirrtl-e(exp(e),g),remove-chirrtl-e(index(e),MALE),type(e)) - (e) : map(remove-chirrtl-e{_,g},e) - defn get-mask (e:Expression) -> Expression : - match(map(get-mask,e)) : - (e:Ref) : - if key?(repl,name(e)) : - val vt = repl[name(e)] - val t = create-mask(type(e)) - SubField(exp(vt),mask(vt),t) - else : e - (e) : e - match(s) : - (s:Connect) : - val stmts = Vector<Stmt>() - val roc* = remove-chirrtl-e(exp(s),MALE) - val loc* = remove-chirrtl-e(loc(s),FEMALE) - add(stmts,Connect(info(s),loc*,roc*)) - if has-write-mport? : - val e = get-mask(loc(s)) - for x in create-exps(e) do : - add(stmts,Connect(info(s),x,one)) - if has-readwrite-mport? != false : - val wmode = has-readwrite-mport? as Expression - add(stmts,Connect(info(s),wmode,one)) - if length(stmts) > 1 : Begin(to-list(stmts)) - else : stmts[0] - (s:BulkConnect) : - val stmts = Vector<Stmt>() - val loc* = remove-chirrtl-e(loc(s),FEMALE) - val roc* = remove-chirrtl-e(exp(s),MALE) - add(stmts,BulkConnect(info(s),loc*,roc*)) - if has-write-mport? != false : - val ls = get-valid-points(type(loc(s)),type(exp(s)),DEFAULT,DEFAULT) - val locs = create-exps(get-mask(loc(s))) - for x in ls do : - val loc* = locs[x[0]] - add(stmts,Connect(info(s),loc*,one)) - if has-readwrite-mport? != false : - val wmode = has-readwrite-mport? as Expression - add(stmts,Connect(info(s),wmode,one)) - if length(stmts) > 1 : Begin(to-list(stmts)) - else : stmts[0] - (s) : map(remove-chirrtl-e{_,MALE}, map(remove-chirrtl-s,s)) - collect-mports(body(m)) - val s* = collect-refs(body(m)) - InModule(info(m),name(m), ports(m), remove-chirrtl-s(s*)) - Circuit(info(c),modules*, main(c)) where : - val modules* = - for m in modules(c) map : - match(m) : - (m:InModule) : remove-chirrtl-m(m) - (m:ExModule) : m - - -;============ FromCHIRRTL ============== - -public defstruct FromCHIRRTL <: Pass -public defmethod pass (b:FromCHIRRTL) -> (Circuit -> Circuit) : from-chirrtl -public defmethod name (b:FromCHIRRTL) -> String : "From CHIRRTL" -public defmethod short-name (b:FromCHIRRTL) -> String : "from-chirrtl" - -defn from-chirrtl (c:Circuit) -> Circuit : - val c1 = infer-types(c) - ;println(c1) - val c2 = infer-mdir(c1) - ;println(c2) - val c3 = remove-chirrtl(c2) - ;println(c3) - c3 diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza deleted file mode 100644 index 1054b622..00000000 --- a/src/main/stanza/compilers.stanza +++ /dev/null @@ -1,235 +0,0 @@ -;Copyright (c) 2014 - 2016 The Regents of the University of -;California (Regents). All Rights Reserved. Redistribution and use in -;source and binary forms, with or without modification, are permitted -;provided that the following conditions are met: -; * Redistributions of source code must retain the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer. -; * Redistributions in binary form must reproduce the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer in the documentation and/or other materials -; provided with the distribution. -; * Neither the name of the Regents nor the names of its contributors -; may be used to endorse or promote products derived from this -; software without specific prior written permission. -;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, -;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF -;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT -;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF -;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION -;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR -;MODIFICATIONS. -defpackage firrtl/compiler : - import core - import verse - import firrtl/passes - import firrtl/chirrtl - import firrtl/errors - ;import firrtl/flo - ;import firrtl/verilog - import firrtl/ir2 - import firrtl/ir-utils - import firrtl/firrtl - -;public defstruct StandardFlo <: Compiler : -; with-output : (() -> False) -> False with: (as-method => true) -;public defmethod passes (c:StandardFlo) -> List<Pass> : -; to-list $ [ -; RemoveSpecialChars() -; RemoveScopes() -; CheckHighForm() -; ;; TempElimination() -; ToWorkingIR() -; ResolveKinds() -; CheckKinds() -; InferTypes() -; CheckTypes() -; ResolveGenders() -; CheckGenders() -; ExpandAccessors() -; LowerToGround() -; InlineIndexed() -; ExpandWhens() -; InferWidths() -; Pad() -; Inline() -; SplitExp() -; ToRealIR() -; CheckWidths() -; ;RemoveSpecialChars() -; CheckHighForm() -; CheckLowForm() -; Flo(with-output(c)) -; ] - -public defstruct StandardVerilog <: Compiler : - with-output : (() -> False) -> False with: (as-method => true) -public defmethod backend (c:StandardVerilog) -> List<Pass> : - to-list $ [ Verilog(with-output(c)) ] -public defmethod passes (c:StandardVerilog) -> List<Pass> : - to-list $ [ - ;RemoveSpecialChars() - ;TempElimination() ; Needs to check number of uses - ;=============== - CInferTypes() - CInferMDir() - RemoveCHIRRTL() - ;=============== - ToWorkingIR() - ;=============== - CheckHighForm() - ;=============== - ResolveKinds() - InferTypes() - CheckTypes() - ResolveGenders() - CheckGenders() - InferWidths() - CheckWidths() - ;=============== - PullMuxes() - ;=============== - ExpandConnects() - ;=============== - RemoveAccesses() - ;=============== - ExpandWhens() - ;=============== - CheckInitialization() - ;=============== - ConstProp() - ;=============== - ResolveKinds() - InferTypes() - CheckTypes() - ResolveGenders() - CheckGenders() - InferWidths() - CheckWidths() - ;=============== - LowerTypes() - ;=============== - ResolveKinds() - InferTypes() - CheckTypes() - ResolveGenders() - CheckGenders() - InferWidths() - CheckWidths() - ;=============== - VerilogWrap() - SplitExp() - VerilogRename() - Verilog(with-output(c)) - ;=============== - ;ToRealIR() - ;Pad() - ;CheckWidths() - ;CheckHighForm() - ;CheckLowForm() - ;Verilog(with-output(c)) - ] - -public defstruct StandardFIRRTL <: Compiler : - with-output : (() -> False) -> False with: (as-method => true) -public defmethod backend (c:StandardFIRRTL) -> List<Pass> : - to-list $ [ FIRRTL(with-output(c)) ] -public defmethod passes (c:StandardFIRRTL) -> List<Pass> : - to-list $ [ - FIRRTL(with-output(c)) - ] - -public defstruct StandardLoFIRRTL <: Compiler : - with-output : (() -> False) -> False with: (as-method => true) -public defmethod backend (c:StandardLoFIRRTL) -> List<Pass> : - to-list $ [ FIRRTL(with-output(c)) ] -public defmethod passes (c:StandardLoFIRRTL) -> List<Pass> : - to-list $ [ - ;=============== - RemoveCHIRRTL() - ;=============== - CheckHighForm() - ;=============== - ToWorkingIR() - ;=============== - ResolveKinds() - InferTypes() - CheckTypes() - ResolveGenders() - CheckGenders() - InferWidths() - CheckWidths() - ;=============== - Resolve() - ;=============== - ExpandConnects() - ;=============== - RemoveAccesses() - ;=============== - ExpandWhens() - ;=============== - CheckInitialization() - ;=============== - ConstProp() - ;=============== - ResolveKinds() - InferTypes() - CheckTypes() - ResolveGenders() - CheckGenders() - InferWidths() - CheckWidths() - ;=============== - LowerTypes() - ;=============== - ResolveKinds() - InferTypes() - CheckTypes() - ResolveGenders() - CheckGenders() - InferWidths() - CheckWidths() - ;=============== - SplitExp() - ;=============== - FIRRTL(with-output(c)) - ] - -;============= DRIVER ====================================== -public defn run-backend (c:Circuit,pass:Pass) : - run-passes(c,list(pass)) -public defn run-passes (c:Circuit,comp:Compiler) -> Circuit: - run-passes(c,passes(comp)) -public defn run-passes (c:Circuit,ls:List<Pass>) -> Circuit: - var c*:Circuit = c - println("Compiling!") - if PRINT-CIRCUITS : println("Original Circuit") - if PRINT-CIRCUITS : print(c) - ;val start-time = current-time-us() - val start-time = to-int(to-string(current-time-us() / to-long(1000))) - var t = start-time - val time-table = Vector<[String,Int]>() - for p in ls do : - println-all(["Starting " name(p)]) - if PRINT-CIRCUITS : println(name(p)) - c* = pass(p)(c*) - if PRINT-CIRCUITS : print(c*) - val current-time = to-int(to-string(current-time-us() / to-long(1000))) - println-all(["Finished " name(p)]) - println-all(["Milliseconds since start: " current-time - start-time]) - println-all(["Milliseconds for this pass: " current-time - t]) - println-all(["\n"]) - ;println-all([current-time - t]) - add(time-table,[name(p), current-time - t]) - t = current-time - - println("===== Time Breakdown =====") - for x in time-table do : - println-all([x[0] " --- " to-float(x[1] as Int * 100) / to-float(t - start-time) "%" " --- " to-float(x[1] as Int * 100) "ms"]) - println-all(["Total Time --- " to-float(t - start-time) "ms"]) - println("==========================") - println("Done!") - c* diff --git a/src/main/stanza/custom-compiler.stanza b/src/main/stanza/custom-compiler.stanza deleted file mode 100644 index 95686189..00000000 --- a/src/main/stanza/custom-compiler.stanza +++ /dev/null @@ -1,71 +0,0 @@ -;Copyright (c) 2014 - 2016 The Regents of the University of -;California (Regents). All Rights Reserved. Redistribution and use in -;source and binary forms, with or without modification, are permitted -;provided that the following conditions are met: -; * Redistributions of source code must retain the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer. -; * Redistributions in binary form must reproduce the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer in the documentation and/or other materials -; provided with the distribution. -; * Neither the name of the Regents nor the names of its contributors -; may be used to endorse or promote products derived from this -; software without specific prior written permission. -;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, -;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF -;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT -;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF -;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION -;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR -;MODIFICATIONS. -;defpackage firrtl/custom-compiler : -; import core -; import verse -; import firrtl/ir-utils -; import firrtl/ir2 -; import firrtl/passes -; import firrtl/errors -; import firrtl/verilog -; import firrtl/custom-passes -; -;public defstruct InstrumentedVerilog <: Compiler : -; with-output: (() -> False) -> False with: (as-method => true) -; args: List<String> -;public defmethod passes (c:InstrumentedVerilog) -> List<Pass> : -; to-list $ [ -; WhenCoverage(args(c)[0],args(c)[1]) -; RemoveSpecialChars() -; RemoveScopes() -; CheckHighForm() -; TempElimination() -; ToWorkingIR() -; ;; MakeExplicitReset() -; ResolveKinds() -; CheckKinds() -; InferTypes() -; CheckTypes() -; ResolveGenders() -; CheckGenders() -; ExpandAccessors() -; LowerToGround() -; InlineIndexed() -; InferTypes() -; CheckGenders() -; ExpandWhens() -; InferWidths() -; ;Pad() -; ConstProp() -; SplitExp() -; ToRealIR() -; ;RemoveSpecialChars() -; CheckHighForm() -; CheckLowForm() -; CheckInitialization() -; Verilog(with-output(c)) -; ] -; -; diff --git a/src/main/stanza/custom-passes.stanza b/src/main/stanza/custom-passes.stanza deleted file mode 100644 index 089b9318..00000000 --- a/src/main/stanza/custom-passes.stanza +++ /dev/null @@ -1,248 +0,0 @@ -;Copyright (c) 2014 - 2016 The Regents of the University of -;California (Regents). All Rights Reserved. Redistribution and use in -;source and binary forms, with or without modification, are permitted -;provided that the following conditions are met: -; * Redistributions of source code must retain the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer. -; * Redistributions in binary form must reproduce the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer in the documentation and/or other materials -; provided with the distribution. -; * Neither the name of the Regents nor the names of its contributors -; may be used to endorse or promote products derived from this -; software without specific prior written permission. -;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, -;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF -;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT -;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF -;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION -;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR -;MODIFICATIONS. -;defpackage firrtl/custom-passes : -; import core -; import verse -; import firrtl/ir-utils -; import firrtl/ir2 -; import bigint2 -; -;;============ When Coverage ============= -;public defstruct WhenCoverage <: Pass : -; port-name : String -; reg-name : String -;public defmethod pass (b:WhenCoverage) -> (Circuit -> Circuit) : when-coverage{port-name(b),reg-name(b),_} -;public defmethod name (b:WhenCoverage) -> String : "When Coverage" -;public defmethod short-name (b:WhenCoverage) -> String : "when-coverage" -; -;;============ Utilz ============= -;defn concat-all (ls:List<Expression>) -> Expression : -; if length(ls) == 0 : error("Shouldn't be here") -; if length(ls) == 1 : head(ls) -; else : DoPrim( CONCAT-OP, -; list(head(ls),concat-all(tail(ls))), -; list(), -; UIntType(UnknownWidth())) -; -;;============ When Coverage Pass ============= -;;port width = 1 bit per scope + portwidths of all instances -; -;defn needs-instrumentation (m:Module,ms:List<Module>,instrument?:HashTable<Symbol,True|False>) -> False : -; defn needs-instrumentation-s (s:Stmt) -> False : -; match(s) : -; (s:Conditionally) :instrument?[name(m)] = true -; (s:DefInstance) : -; val module-of-inst = for x in ms find : name(x) == name(module(s) as Ref) -; if module-of-inst != false : -; needs-instrumentation(module-of-inst as Module,ms,instrument?) -; instrument?[name(m)] = instrument?[name(module-of-inst as Module)] -; (s) : false -; do(needs-instrumentation-s,s) -; -; match(m) : -; (m:InModule) : do(needs-instrumentation-s,body(m)) -; (m:ExModule) : false -; -;defn when-coverage (port-name:Symbol, reg-name:Symbol, instrument?:HashTable<Symbol,True|False>, m:InModule) -> InModule : -; val when-bits = Vector<Ref>() -; val inst-bits = Vector<Ref>() -; val sym = HashTable<Symbol,Int>(symbol-hash) -; val w1 = LongWidth(1) -; val t1 = UIntType(w1) -; val u1 = UIntValue(BigIntLit("h1"),w1) -; defn when-coverage (s:Stmt) -> Stmt : -; match(s) : -; (s:Conditionally) : -; val ref = Ref(firrtl-gensym(reg-name,sym),t1) -; add(when-bits,ref) -; val conseq* = Begin(list(Connect(FileInfo()ref,u1),conseq(s))) -; map(when-coverage,Conditionally(info(s),pred(s),conseq*,alt(s))) -; (s:DefInstance) : -; if instrument?[name(module(s) as Ref)] : -; val ref = Ref(firrtl-gensym(port-name,sym),UIntType(UnknownWidth())) -; add(inst-bits,ref) -; val sfld = Subfield(Ref(name(s),UnknownType()),port-name,UnknownType()) -; Begin(list(s,Connect(FileInfo(),ref,sfld))) -; else : s -; (s) : map(when-coverage,s) -; -; val body* = when-coverage(body(m)) -; val logic = Vector<Stmt>() -; val port-ref = Ref(port-name,UIntType(UnknownWidth())) -; -; val w-ls = to-list $ when-bits -; if length(w-ls) != 0 : -; val reg-ref = Ref(reg-name,UIntType(LongWidth(length(w-ls)))) -; ;add{logic,_} $ DefRegister(FileInfo(),name(reg-ref),type(reg-ref)) TODO add clock and reset -; for (x in w-ls, i in 0 to false) do : -; add{logic,_} $ DefWire(FileInfo(),name(x),type(x)) -; add{logic,_} $ Connect(FileInfo(),x,DoPrim(BIT-SELECT-OP,list(reg-ref),list(i),UIntType(w1))) -; add{logic,_} $ Connect(FileInfo(),reg-ref,concat-all(w-ls)) -; add{logic,_} $ OnReset(FileInfo(),reg-ref,UIntValue(BigIntLit("h0"),LongWidth(length(w-ls)))) -; -; val i-ls = to-list $ inst-bits -; if length(i-ls) != 0 : -; for (x in i-ls, i in 0 to false) do : -; add{logic,_} $ DefWire(FileInfo(),name(x),type(x)) -; add{logic,_} $ Connect(FileInfo(),x,UIntValue(BigIntLit("h0"),UnknownWidth())) -; -; if instrument?[name(m)] : add{logic,_} $ Connect(FileInfo(),port-ref,concat-all(append(w-ls,i-ls))) -; -; if length(logic) != 0 : -; val ports* = List(Port(FileInfo(),port-name,OUTPUT,UIntType(UnknownWidth())),ports(m)) -; val body** = Begin(list(Begin(to-list $ logic),body*)) -; InModule(info(m),name(m),ports*,body**) -; else : m -; -;public defn when-coverage (port-name:String, reg-name:String, c:Circuit) : -; val instrument? = HashTable<Symbol,True|False>(symbol-hash) -; for m in modules(c) do : -; instrument?[name(m)] = false -; val top = for m in modules(c) find : name(m) == main(c) -; if top != false : needs-instrumentation(top as Module,modules(c),instrument?) -; -; val modules* = for m in modules(c) map : -; match(m) : -; (m:InModule) : -; when-coverage(to-symbol $ port-name,to-symbol $ reg-name,instrument?,m) -; (m:ExModule) : m -; Circuit(info(c),modules*,main(c)) -; -;;;============ Temporal Check ============= -;;public defstruct TemporalAssert : -;; module : String -;; name : String -;; value : Int -;; cycle : Int -;;public defstruct InsertTemporalAsserts <: Pass : -;; asserts : List<TemporalAssert> -;;public defmethod pass (b:InsertTemporalAsserts) -> (Circuit -> Circuit) : insert-temporal-assert{asserts(b),_} -;;public defmethod name (b:InsertTemporalAsserts) -> String : "Insert Temporal Assert" -;;public defmethod short-name (b:InsertTemporalAsserts) -> String : "insert-temporal-assert" -;; -;;;============ Utilz ============= -;;defn concat-all (ls:List<Expression>) -> Expression : -;; if length(ls) == 0 : error("Shouldn't be here") -;; if length(ls) == 1 : head(ls) -;; else : DoPrim( CONCAT-OP, -;; list(head(ls),concat-all(tail(ls))), -;; list(), -;; UIntType(UnknownWidth())) -;; -;;;============ Insert Temporal Asserts Pass ============= -;; -;; -;;public defn insert-temporal-assert (asserts:List<TemporalAssert>,m:Module) -> Module : -;; -;; for statement in body(m) do : -;; -;; for a in asserts do : -;; val mod* = for m in modules(c) find : name(m) == module(a) -;; match(mod*) : -;; (m:False) : error("Module not found") -;; (m:Module) : -;; -;; -;;defn needs-ita-instrumentation (m:Module,ms:List<Module>,instrument?:HashTable<Symbol,True|False>,asserts:List<TemporalAssert>) -> False : -;; defn needs-instrumentation-s (s:Stmt) -> False : -;; match(s) : -;; (s:DefWire|DefRegister) : instrument?[name(m)] = contains?(name(s),map(name,asserts)) -;; (s:DefInstance) : -;; val module-of-inst = for x in ms find : name(x) == name(module(s) as Ref) -;; if module-of-inst != false : -;; needs-ita-instrumentation(module-of-inst as Module,ms,instrument?,asserts) -;; instrument?[name(m)] = instrument?[name(module-of-inst as Module)] -;; (s) : false -;; do(needs-instrumentation-s,s) -;; -;; match(m) : -;; (m:InModule) : do(needs-instrumentation-s,body(m)) -;; (m:ExModule) : false -;; -;;defn insert-temporal-asserts (port-name:Symbol,assert-name:Symbol,asserts:List<TemporalAssert>,instrument?:HashTable<Symbol,True|False>, m:InModule) -> InModule : -;; val when-bits = Vector<Ref>() -;; val inst-bits = Vector<Ref>() -;; val sym = HashTable<Symbol,Int>(symbol-hash) -;; val w1 = LongWidth(1) -;; val t1 = UIntType(w1) -;; val u1 = UIntValue(to-long $ 1,w1) -;; defn insert-temporal-asserts (s:Stmt) -> Stmt : -;; match(s) : -;; (s:DefWire|DefRegister) : -;; val ref = Ref(firrtl-gensym(name(s),sym),t1) -;; add(when-bits,ref) -;; val conseq* = Begin(list(Connect(FileInfo()ref,u1),conseq(s))) -;; map(when-coverage,Conditionally(info(s),pred(s),conseq*,alt(s))) -;; (s:DefInstance) : -;; if instrument?[name(module(s) as Ref)] : -;; val ref = Ref(firrtl-gensym(port-name,sym),UIntType(UnknownWidth())) -;; add(inst-bits,ref) -;; val sfld = Subfield(Ref(name(s),UnknownType()),port-name,UnknownType()) -;; Begin(list(s,Connect(FileInfo(),ref,sfld))) -;; else : s -;; (s) : map(when-coverage,s) -;; -;; val body* = when-coverage(body(m)) -;; val logic = Vector<Stmt>() -;; val port-ref = Ref(port-name,UIntType(UnknownWidth())) -;; -;; val w-ls = to-list $ when-bits -;; if length(w-ls) != 0 : -;; val reg-ref = Ref(reg-name,UIntType(LongWidth(length(w-ls)))) -;; add{logic,_} $ DefRegister(FileInfo(),name(reg-ref),type(reg-ref)) -;; add{logic,_} $ OnReset(FileInfo(),reg-ref,UIntValue(to-long $ 0,LongWidth(length(w-ls)))) -;; for (x in w-ls, i in 0 to false) do : -;; add{logic,_} $ DefWire(FileInfo(),name(x),type(x)) -;; add{logic,_} $ Connect(FileInfo(),x,DoPrim(BIT-SELECT-OP,list(reg-ref),list(i),UIntType(w1))) -;; add{logic,_} $ Connect(FileInfo(),reg-ref,concat-all(w-ls)) -;; -;; val i-ls = to-list $ inst-bits -;; if length(i-ls) != 0 : -;; for (x in i-ls, i in 0 to false) do : -;; add{logic,_} $ DefWire(FileInfo(),name(x),type(x)) -;; add{logic,_} $ Connect(FileInfo(),x,UIntValue(to-long $ 0,UnknownWidth())) -;; -;; if instrument?[name(m)] : add{logic,_} $ Connect(FileInfo(),port-ref,concat-all(append(w-ls,i-ls))) -;; -;; if length(logic) != 0 : -;; val ports* = List(Port(FileInfo(),port-name,OUTPUT,UIntType(UnknownWidth())),ports(m)) -;; val body** = Begin(list(Begin(to-list $ logic),body*)) -;; InModule(info(m),name(m),ports*,body**) -;; else : m -;; -;;public defn when-coverage (port-name:String, reg-name:String, c:Circuit) : -;; val instrument? = HashTable<Symbol,True|False>(symbol-hash) -;; for m in modules(c) do : -;; instrument?[name(m)] = false -;; val top = for m in modules(c) find : name(m) == main(c) -;; if top != false : needs-instrumentation(top as Module,modules(c),instrument?) -;; -;; val modules* = for m in modules(c) map : -;; match(m) : -;; (m:InModule) : -;; when-coverage(to-symbol $ port-name,to-symbol $ reg-name,instrument?,m) -;; (m:ExModule) : m -;; Circuit(info(c),modules*,main(c)) -;; diff --git a/src/main/stanza/errors.stanza b/src/main/stanza/errors.stanza deleted file mode 100644 index 6d702e9b..00000000 --- a/src/main/stanza/errors.stanza +++ /dev/null @@ -1,1032 +0,0 @@ -;Copyright (c) 2014 - 2016 The Regents of the University of -;California (Regents). All Rights Reserved. Redistribution and use in -;source and binary forms, with or without modification, are permitted -;provided that the following conditions are met: -; * Redistributions of source code must retain the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer. -; * Redistributions in binary form must reproduce the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer in the documentation and/or other materials -; provided with the distribution. -; * Neither the name of the Regents nor the names of its contributors -; may be used to endorse or promote products derived from this -; software without specific prior written permission. -;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, -;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF -;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT -;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF -;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION -;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR -;MODIFICATIONS. -defpackage firrtl/errors : - import core - import verse - import firrtl/ir2 - import firrtl/ir-utils - import firrtl/primops - import firrtl/passes - import firrtl-main - import bigint2 - -; TODO -; make sure it compiles, write tests, look over code to make sure its right -;========== ALL CHECKS ================= -;PARSER CHECK -; * No nested modules <- parser -; * Only modules in circuit (no statements or expressions) <- parser -; * Module must be a reference in inst declaration - -;AFTER ?????? -; o No combinational loops - -;================= High Form Check ========================== -; * Subexps of Subfield and Index can only be subfields, index, or refs -; * Can only connect to a Ref or Subfield or Index or WritePort -; * A module has the same name as main of circuit -; * mems cannot be a bundle with flips -; * instance module must have the same name as a defined module -; * Unique names per module -; * No name can be a prefix of any other name. -; * all references are declared -; * UInt only has positive ints -; * Vector types has positive size -; * Width sizes are positive -; * Primops have the correct number of arguments - -public defstruct CheckHighForm <: Pass -public defmethod pass (b:CheckHighForm) -> (Circuit -> Circuit) : check-high-form -public defmethod name (b:CheckHighForm) -> String : "High Form Check" -public defmethod short-name (b:CheckHighForm) -> String : "high-form-check" - -var sinfo! = FileInfo() - -;----------------- Errors ------------------------ -defn NotUnique (name:Symbol) : - PassException $ string-join $ - [sinfo! ": [module " mname "] Reference " name " does not have a unique name."] - -defn IsPrefix (prefix:Symbol) : - PassException $ string-join $ - [sinfo! ": [module " mname "] Symbol " prefix " is a prefix."] - -defn InvalidLOC () : - PassException $ string-join $ - [sinfo! ": [module " mname "] Invalid connect to an expression that is not a reference or a WritePort."] - -defn NegUInt () : - PassException $ string-join $ - [sinfo! ": [module " mname "] UIntValue cannot be negative."] - -defn UndeclaredReference (name:Symbol) : - PassException $ string-join $ - [sinfo! ": [module " mname "] Reference " name " is not declared."] - -defn PoisonWithFlip (name:Symbol) : - PassException $ string-join $ - [sinfo! ": [module " mname "] Poison " name " cannot be a bundle type with flips."] - -defn MemWithFlip (name:Symbol) : - PassException $ string-join $ - [sinfo! ": [module " mname "] Memory " name " cannot be a bundle type with flips."] - -defn InvalidAccess () : - PassException $ string-join $ - [sinfo! ": [module " mname "] Invalid access to non-reference."] - -defn NoTopModule (name:Symbol) : - PassException $ string-join $ - [sinfo! ": A single module must be named " name "."] - -defn ModuleNotDefined (name:Symbol) : - PassException $ string-join $ - [sinfo! ": Module " name " is not defined."] - -defn IncorrectNumArgs (op:Symbol, n:Int) : - PassException $ string-join $ - [sinfo! ": [module " mname "] Primop " op " requires " n " expression arguments."] - -defn IncorrectNumConsts (op:Symbol, n:Int) : - PassException $ string-join $ - [sinfo! ": [module " mname "] Primop " op " requires " n " integer arguments."] - -defn NegWidth () : - PassException $ string-join $ - [sinfo! ": [module " mname "] Width cannot be negative or zero."] - -defn NegVecSize () : - PassException $ string-join $ - [sinfo! ": [module " mname "] Vector type size cannot be negative."] - -defn NegMemSize () : - PassException $ string-join $ - [sinfo! ": [module " mname "] Memory size cannot be negative or zero."] - -defn IllegalUnknownWidth () : - PassException $ string-join $ - [sinfo! ": [module " mname "] Widths must be defined for memories and poison nodes."] - -defn BadPrintf (x:Char) : - PassException $ string-join $ - [sinfo! ": [module " mname "] Bad printf format: \"%" x "\""];" - -defn BadPrintfTrailing () : - PassException $ string-join $ - [sinfo! ": [module " mname "] Bad printf format: trailing \"%\""];" - -defn BadPrintfIncorrectNum () : - PassException $ string-join $ - [sinfo! ": [module " mname "] Bad printf format: incorrect number of arguments"];" - - -;---------------- Helper Functions -------------- -defn has-flip? (t:Type) -> True|False : - var has? = false - defn find-flip (t:Type) -> Type : - match(t) : - (t:BundleType) : - for f in fields(t) do : - if flip(f) == REVERSE : has? = true - t - (t) : t - find-flip(t) - map(find-flip,t) - has? - -defn contains?<?T> (c:?T,cs:Streamable<?T>) -> True|False : - label<True|False> myret : - for x in cs do : - if x == c : myret(true) - false - -;--------------- Prefix Checker -------------------- - -defstruct Trie : - children : HashTable<Symbol,Trie> - end? : True|False with: (setter => set-end) - -defmethod print (o:OutputStream,t:Trie) : - print-all(o,["[end?:" end?(t) ",children:" children(t) "]"]) - -defn split (s:Symbol) -> List<Symbol> : - map(to-symbol,split(to-string(s),'$')) - -defn contains? (t:Trie,s:Symbol) -> True|False : - key?(children(t),s) - -defn empty? (t:Trie) -> True|False : - length(children(t)) == 0 - -defn add (t:Trie,ls:List<Symbol>) -> True|False : - var t*:Trie = t - var saw-end? = false - for x in ls do : - if end?(t*) : saw-end? = true - if contains?(t*,x) : t* = children(t*)[x] - else : - val temp = Trie(HashTable<Symbol,Trie>(symbol-hash),false) - children(t*)[x] = temp - t* = temp - set-end(t*,true) - saw-end? or not empty?(t*) - -defn contains? (t:Trie,ls:List<Symbol>) -> True|False : - var t*:Trie = t - label<True|False> myret : - for x in ls do : - if contains?(t*,x) : t* = children(t*)[x] - else : myret(false) - myret(end?(t*)) - -;--------------- Check High Form Pass ------------------- -public defn check-high-form (c:Circuit) -> Circuit : - val errors = Vector<PassException>() - defn check-high-form-primop (e:DoPrim) -> False : - defn correct-num (ne:Int|False,nc:Int) -> False : - if not (ne typeof False) : - if length(args(e)) != ne as Int : add(errors,IncorrectNumArgs(to-symbol(op(e)),ne as Int)) - if length(consts(e)) != nc : add(errors,IncorrectNumConsts(to-symbol $ op(e),nc)) - - switch {op(e) == _} : - ADD-OP : correct-num(2,0) - SUB-OP : correct-num(2,0) - MUL-OP : correct-num(2,0) - DIV-OP : correct-num(2,0) - REM-OP : correct-num(2,0) - LESS-OP : correct-num(2,0) - LESS-EQ-OP : correct-num(2,0) - GREATER-OP : correct-num(2,0) - GREATER-EQ-OP : correct-num(2,0) - EQUAL-OP : correct-num(2,0) - NEQUAL-OP : correct-num(2,0) - PAD-OP : correct-num(1,1) - AS-UINT-OP : correct-num(1,0) - AS-SINT-OP : correct-num(1,0) - AS-CLOCK-OP : correct-num(1,0) - SHIFT-LEFT-OP : correct-num(1,1) - SHIFT-RIGHT-OP : correct-num(1,1) - DYN-SHIFT-LEFT-OP : correct-num(2,0) - DYN-SHIFT-RIGHT-OP : correct-num(2,0) - CONVERT-OP : correct-num(1,0) - NEG-OP : correct-num(1,0) - NOT-OP : correct-num(1,0) - AND-OP : correct-num(2,0) - OR-OP : correct-num(2,0) - XOR-OP : correct-num(2,0) - AND-REDUCE-OP : correct-num(false,0) - OR-REDUCE-OP : correct-num(false,0) - XOR-REDUCE-OP : correct-num(false,0) - CONCAT-OP : correct-num(2,0) - BITS-SELECT-OP : correct-num(1,2) - HEAD-OP : correct-num(1,1) - TAIL-OP : correct-num(1,1) - - defn check-fstring (s:String,i:Int) -> False : - val valid-formats = "bedxs" - var percent = false - var ret = true - var npercents = 0 - for x in s do : - if (not contains?(valid-formats,x)) and percent : - add(errors,BadPrintf(x)) - if x == '%' : npercents = npercents + 1 - percent = x == '%' - if percent : add(errors,BadPrintfTrailing()) - if npercents != i : add(errors,BadPrintfIncorrectNum()) - defn check-valid-loc (e:Expression) -> False : - match(e) : - (e:UIntValue|SIntValue|DoPrim) : - add(errors,InvalidLOC()) - (e) : false - defn check-high-form-w (w:Width) -> Width : - match(w) : - (w:IntWidth) : - if width(w) <= to-long(0) : - add(errors,NegWidth()) - w - (w) : w - defn check-high-form-t (t:Type) -> Type : - match(map(check-high-form-t,t)) : - (t:VectorType) : - if size(t) < 0 : add(errors,NegVecSize()) - (t) : false - map(check-high-form-w,t) - - defn check-high-form-m (m:Module) -> Module : - val names = HashTable<Symbol,True>(symbol-hash) - val mnames = HashTable<Symbol,True>(symbol-hash) - val tries = Trie(HashTable<Symbol,Trie>(symbol-hash),false) - defn check-high-form-e (e:Expression) -> Expression : - defn valid-subexp (e:Expression) -> Expression : - match(e) : - (e:WRef|WSubField|WSubIndex|WSubAccess|Mux|ValidIf) : false - (e) : add(errors,InvalidAccess()) - e - match(map(check-high-form-e,e)) : - (e:WRef) : - if not key?(names,name(e)) : - add(errors,UndeclaredReference(name(e))) - (e:DoPrim) : check-high-form-primop(e) - (e:Mux|ValidIf) : e - (e:UIntValue) : false - (e:WSubAccess) : - valid-subexp(exp(e)) - e - (e) : map(valid-subexp,e) - map(check-high-form-w,e) - map(check-high-form-t,e) - e - defn check-high-form-s (s:Stmt) -> Stmt : - defn check-name (name:Symbol) -> Symbol : - if key?(names,name) : add(errors,NotUnique(name)) - else : names[name] = true - val ls = split(name) - if add(tries,ls) : add(errors,IsPrefix(name)) - name - sinfo! = info(s) - map(check-name,s) - map(check-high-form-t,s) - map(check-high-form-e,s) - match(s) : - (s:DefWire|DefRegister|DefNode|Conditionally|Stop|Begin) : false - (s:DefPoison) : - if has-flip?(type(s)) : add(errors, PoisonWithFlip(name(s))) - check-high-form-t(type(s)) - (s:DefMemory) : - if has-flip?(data-type(s)) : add(errors, MemWithFlip(name(s))) - if depth(s) <= 0 : add(errors,NegMemSize()) - (s:WDefInstance) : - if not contains?(module(s),map(name,modules(c))) : - add(errors, ModuleNotDefined(module(s))) - (s:Connect) : check-valid-loc(loc(s)) - (s:Print) : check-fstring(string(s),length(args(s))) - (s:BulkConnect) : check-valid-loc(loc(s)) - (s) : false - - map(check-high-form-s,s) - - mname = name(m) - for m in modules(c) do : - mnames[name(m)] = true - for p in ports(m) do : - names[name(p)] = true - map(check-high-form-t,type(p)) - map(check-high-form-w,type(p)) - - match(m) : - (m:ExModule) : false - (m:InModule) : check-high-form-s(body(m)) - m - - var number-top-m = 0 - for m in modules(c) do : - if name(m) == main(c) : number-top-m = number-top-m + 1 - check-high-form-m(m) - sinfo! = info!(c) - if number-top-m != 1 : add(errors,NoTopModule(main(c))) - throw(PassExceptions(errors)) when not empty?(errors) - c - -;==================== CHECK TYPES ===================== -; o Subfields are only on bundles, before type inference <- need to not error, just do unknown-type -; o Indexes are only on vectors -; o pred in conditionally must be of type UInt -; o enable/index in read/writeports must be UInt -; o node's value cannot be a bundle with a flip in it -; o := has same types -; o 2nd arg in dshr/l must be UInt, in general do primops -; o clock must be ClockType -; o reset must be UInt<1> - -public defstruct CheckTypes <: Pass -public defmethod pass (b:CheckTypes) -> (Circuit -> Circuit) : check-types -public defmethod name (b:CheckTypes) -> String : "Check Types" -public defmethod short-name (b:CheckTypes) -> String : "check-types" - -;----------------- Errors --------------------- -defn SubfieldNotInBundle (info:FileInfo, name:Symbol) : - PassException $ string-join $ - [info ": [module " mname "] Subfield " name " is not in bundle."] - -defn SubfieldOnNonBundle (info:FileInfo, name:Symbol) : - PassException $ string-join $ - [info ": [module " mname "] Subfield " name " is accessed on a non-bundle."] - -defn IndexTooLarge (info:FileInfo, value:Int) : - PassException $ string-join $ - [info ": [module " mname "] Index with value " value " is too large."] - -defn IndexOnNonVector (info:FileInfo) : - PassException $ string-join $ - [info ": [module " mname "] Index illegal on non-vector type."] - -defn AccessIndexNotUInt (info:FileInfo) : - PassException $ string-join $ - [info ": [module " mname "] Access index must be a UInt type."] - -defn IndexNotUInt (info:FileInfo) : - PassException $ string-join $ - [info ": [module " mname "] Index is not of UIntType."] - -defn EnableNotUInt (info:FileInfo) : - PassException $ string-join $ - [info ": [module " mname "] Enable is not of UIntType."] - -defn InvalidConnect (info:FileInfo) : - PassException $ string-join $ - [info ": [module " mname "] Type mismatch."] - -defn PrintfArgNotGround (info:FileInfo) : - PassException $ string-join $ - [info ": [module " mname "] Printf arguments must be either UIntType or SIntType."] - -defn ReqClk (info:FileInfo) : - PassException $ string-join $ - [info ": [module " mname "] Requires a clock typed signal."] - -defn EnNotUInt (info:FileInfo) : - PassException $ string-join $ - [info ": [module " mname "] Enable must be a UIntType typed signal."] - -defn PredNotUInt (info:FileInfo) : - PassException $ string-join $ - [info ": [module " mname "] Predicate not a UIntType."] - -defn OpNotGround (info:FileInfo, op:Symbol) : - PassException $ string-join $ - [info ": [module " mname "] Primop " op " cannot operate on non-ground types."] - -defn OpNotUInt (info:FileInfo, op:Symbol,e:Symbol) : - PassException $ string-join $ - [info ": [module " mname "] Primop " op " requires argument " e " to be a UInt type."] - -defn OpNotAllUInt (info:FileInfo, op:Symbol) : - PassException $ string-join $ - [info ": [module " mname "] Primop " op " requires all arguments to be UInt type."] - -defn OpNotAllSameType (info:FileInfo, op:Symbol) : - PassException $ string-join $ - [info ": [module " mname "] Primop " op " requires all operands to have the same type."] - -defn NodePassiveType (info:FileInfo) : - PassException $ string-join $ - [info ": [module " mname "] Node must be a passive type."] - -defn MuxSameType (info:FileInfo) : - PassException $ string-join $ - [info ": [module " mname "] Must mux between equivalent types."] - -defn MuxPassiveTypes (info:FileInfo) : - PassException $ string-join $ - [info ": [module " mname "] Must mux between passive types."] - -defn MuxCondUInt (info:FileInfo) : - PassException $ string-join $ - [info ": [module " mname "] A mux condition must be of type UInt."] - -defn ValidIfPassiveTypes (info:FileInfo) : - PassException $ string-join $ - [info ": [module " mname "] Must validif a passive type."] - -defn ValidIfCondUInt (info:FileInfo) : - PassException $ string-join $ - [info ": [module " mname "] A validif condition must be of type UInt."] - -;---------------- Helper Functions -------------- -defmethod equal? (t1:Type,t2:Type) -> True|False : - match(t1,t2) : - (t1:ClockType,t2:ClockType) : true - (t1:UIntType,t2:UIntType) : true - (t1:SIntType,t2:SIntType) : true - (t1:BundleType,t2:BundleType) : - var same? = true - for (f1 in fields(t1),f2 in fields(t2)) do : - if flip(f1) != flip(f2) : same? = false - if name(f1) != name(f2) : same? = false - if type(f1) != type(f2) : same? = false - same? - (t1:VectorType,t2:VectorType) : - if type(t1) == type(t2) and size(t1) == size(t2) : true - else : false - (t1,t2) : false - -defn ut () -> UIntType : UIntType(UnknownWidth()) -defn st () -> SIntType : SIntType(UnknownWidth()) - -defn check-types-primop (e:DoPrim, errors:Vector<PassException>,info:FileInfo) -> False : - defn all-same-type (ls:List<Expression>) -> False : - var error? = false - for x in ls do : - if type(head(ls)) != type(x) : - error? = true - if error? : add(errors,OpNotAllSameType(info,to-symbol $ op(e))) - defn all-ground (ls:List<Expression>) -> False : - var error? = false - for x in ls do : - if not (type(x) typeof UIntType or type(x) typeof SIntType) : - error? = true - if error? : add(errors,OpNotGround(info,to-symbol $ op(e))) - defn all-uint (ls:List<Expression>) -> False : - var error? = false - for x in ls do : - if not (type(x) typeof UIntType) : - error? = true - if error? : add(errors,OpNotAllUInt(info,to-symbol $ op(e))) - defn is-uint (x:Expression) -> False : - var error? = false - if not (type(x) typeof UIntType) : - error? = true - if error? : add(errors,OpNotUInt(info,to-symbol $ op(e),to-symbol(x))) - - switch {op(e) == _} : - AS-UINT-OP : false - AS-SINT-OP : false - AS-CLOCK-OP : false - DYN-SHIFT-LEFT-OP : (is-uint(args(e)[1]) all-ground(args(e))) - DYN-SHIFT-RIGHT-OP : (is-uint(args(e)[1]) all-ground(args(e))) - ADD-OP : all-ground(args(e)) - SUB-OP : all-ground(args(e)) - MUL-OP : all-ground(args(e)) - DIV-OP : all-ground(args(e)) - REM-OP : all-ground(args(e)) - LESS-OP : all-ground(args(e)) - LESS-EQ-OP : all-ground(args(e)) - GREATER-OP : all-ground(args(e)) - GREATER-EQ-OP : all-ground(args(e)) - EQUAL-OP : all-ground(args(e)) - NEQUAL-OP : all-ground(args(e)) - PAD-OP : all-ground(args(e)) - SHIFT-LEFT-OP : all-ground(args(e)) - SHIFT-RIGHT-OP : all-ground(args(e)) - CONVERT-OP : all-ground(args(e)) - NEG-OP : all-ground(args(e)) - NOT-OP : all-ground(args(e)) - AND-OP : all-ground(args(e)) - OR-OP : all-ground(args(e)) - XOR-OP : all-ground(args(e)) - AND-REDUCE-OP : all-ground(args(e)) - OR-REDUCE-OP : all-ground(args(e)) - XOR-REDUCE-OP : all-ground(args(e)) - CONCAT-OP : all-ground(args(e)) - BITS-SELECT-OP : all-ground(args(e)) - HEAD-OP : all-ground(args(e)) - TAIL-OP : all-ground(args(e)) - -;----------------- Check Types Pass --------------------- -public defn check-types (c:Circuit) -> Circuit : - val errors = Vector<PassException>() - defn passive? (t:Type) -> True|False : - match(t) : - (t:UIntType|SIntType) : true - (t:VectorType) : passive?(type(t)) - (t:BundleType) : - var p? = true - for x in fields(t) do : - if (flip(x) == REVERSE) : p? = false - if not passive?(type(x)) : p? = false - p? - (t) : true - defn check-types-e (info:FileInfo,e:Expression) -> Expression : - match(map(check-types-e{info,_},e)) : - (e:WRef) : e - (e:WSubField) : - match(type(exp(e))) : - (t:BundleType) : - val ft = for p in fields(t) find : name(p) == name(e) - if ft == false : add(errors,SubfieldNotInBundle(info,name(e))) - (t) : add(errors,SubfieldOnNonBundle(info,name(e))) - (e:WSubIndex) : - match(type(exp(e))) : - (t:VectorType) : - if value(e) >= size(t) : add(errors,IndexTooLarge(info,value(e))) - (t) : add(errors,IndexOnNonVector(info)) - (e:WSubAccess) : - match(type(exp(e))) : - (t:VectorType) : false - (t) : add(errors,IndexOnNonVector(info)) - match(type(index(e))) : - (t:UIntType) : false - (t) : add(errors,AccessIndexNotUInt(info)) - (e:DoPrim) : check-types-primop(e,errors,info) - (e:Mux) : - if type(tval(e)) != type(fval(e)) : add(errors,MuxSameType(info)) - if not passive?(type(e)) : add(errors,MuxPassiveTypes(info)) - if not passive?(type(e)) : add(errors,MuxPassiveTypes(info)) - if not (type(cond(e)) typeof UIntType) : add(errors,MuxCondUInt(info)) - (e:ValidIf) : - if not passive?(type(e)) : add(errors,ValidIfPassiveTypes(info)) - if not (type(cond(e)) typeof UIntType) : add(errors,ValidIfCondUInt(info)) - (e:UIntValue|SIntValue) : false - e - - defn bulk-equals? (t1:Type,t2:Type) -> True|False : - match(t1,t2) : - (t1:BundleType,t2:BundleType) : - var same? = true - for (f1 in fields(t1),f2 in fields(t2)) do : - if name(f1) == name(f2) : - if flip(f1) != flip(f2) : same? = false - if not bulk-equals?(type(f1),type(f2)) : same? = false - same? - (t1:ClockType,t2:ClockType) : true - (t1:UIntType,t2:UIntType) : true - (t1:SIntType,t2:SIntType) : true - (t1:VectorType,t2:VectorType) : - if bulk-equals?(type(t1),type(t2)) : true - else : false - (t1,t2) : false - - defn check-types-s (s:Stmt) -> Stmt : - map{check-types-s,_} $ { - match(map(check-types-e{info(s),_},s)) : - (s:Connect) : - if type(loc(s)) != type(exp(s)) : add(errors,InvalidConnect(info(s))) - (s:BulkConnect) : - if not bulk-equals?(type(loc(s)),type(exp(s))) : - add(errors,InvalidConnect(info(s))) - (s:Stop) : - if type(clk(s)) != ClockType() : add(errors,ReqClk(info(s))) - if type(en(s)) != ut() : add(errors,EnNotUInt(info(s))) - (s:Print) : - for x in args(s) do : - if type(x) != ut() and type(x) != st(): - add(errors,PrintfArgNotGround(info(s))) - if type(clk(s)) != ClockType() : add(errors,ReqClk(info(s))) - if type(en(s)) != ut() : add(errors,EnNotUInt(info(s))) - (s:Conditionally) : - if type(pred(s)) != ut() : add(errors,PredNotUInt(info(s))) - (s:DefNode) : - if not passive?(type(value(s))) : - add(errors,NodePassiveType(info(s))) - (s) : false - s }() - - for m in modules(c) do : - mname = name(m) - match(m) : - (m:ExModule) : false - (m:InModule) : check-types-s(body(m)) - throw(PassExceptions(errors)) when not empty?(errors) - c - -;================= GENDER CHECK ========================== -; o Nodes always male -; o Accessors only have one gender, unless rdwr -; o output/input only one gender -; o correctly check for the base bundle - -public defstruct CheckGenders <: Pass -public defmethod pass (b:CheckGenders) -> (Circuit -> Circuit) : check-genders -public defmethod name (b:CheckGenders) -> String : "Check Genders" -public defmethod short-name (b:CheckGenders) -> String : "check-genders" - -;----------------- Errors --------------------- -defn WrongGender (info:FileInfo,expr:Symbol,wrong:Symbol,right:Symbol) : - PassException $ string-join $ - [info ": [module " mname "] Expression " expr " is used as a " wrong " but can only be used as a " right "."] - -;---------------- Helper Functions -------------- -defn dir-to-gender (d:Direction) -> Gender : - switch {_ == d} : - INPUT : MALE - OUTPUT : FEMALE ;BI-GENDER - -defn as-srcsnk (g:Gender) -> Symbol : - switch {_ == g} : - MALE : `source - FEMALE : `sink - UNKNOWN-GENDER : `unknown - BI-GENDER : `sourceOrSink - -;----------------- Check Genders Pass --------------------- - -public defn check-genders (c:Circuit) -> Circuit : - val errors = Vector<PassException>() - defn get-kind (e:Expression) -> Kind : - match(e) : - (e:WRef) : kind(e) - (e:WSubField) : get-kind(exp(e)) - (e:WSubIndex) : get-kind(exp(e)) - (e:WSubAccess) : get-kind(exp(e)) - (e) : NodeKind() - - defn check-gender (info:FileInfo,genders:HashTable<Symbol,Gender>,e:Expression,desired:Gender) -> False : - val gender = get-gender(e,genders) - val kind* = get-kind(e) - defn flip? (t:Type) -> True|False : - var f? = false - defn flip-rec (t:Type,f:Flip) -> Type : - match(t) : - (t:BundleType) : - for field in fields(t) do : - flip-rec(type(field),f * flip(field)) - (t:VectorType) : flip-rec(type(t),f) - (t) : if f == REVERSE : f? = true - t - flip-rec(t,DEFAULT) - f? - - val has-flip? = flip?(type(e)) - ;println(e) - ;println(gender) - ;println(desired) - ;println(kind*) - ;println(desired == gender) - ;if gender != desired and gender != BI-GENDER: - switch fn ([x,y]) : gender == x and desired == y : - [MALE, FEMALE] : - add(errors,WrongGender(info,to-symbol(e),as-srcsnk(desired),as-srcsnk(gender))) - [FEMALE, MALE] : - if (kind* == PortKind() or kind* == InstanceKind()) and has-flip? == false : - ; OK! - false - else : - ; Not Ok! - add(errors,WrongGender(info,to-symbol(e),as-srcsnk(desired),as-srcsnk(gender))) - else : false - - defn get-gender (e:Expression,genders:HashTable<Symbol,Gender>) -> Gender : - match(e) : - (e:WRef) : genders[name(e)] - (e:WSubField) : - val f = {_ as Field} $ for f in fields(type(exp(e)) as BundleType) find : name(f) == name(e) - get-gender(exp(e),genders) * flip(f) - (e:WSubIndex) : get-gender(exp(e),genders) - (e:WSubAccess) : get-gender(exp(e),genders) - (e:DoPrim) : MALE - (e:UIntValue) : MALE - (e:SIntValue) : MALE - (e:Mux) : MALE - (e:ValidIf) : MALE - - defn check-genders-e (info:FileInfo,e:Expression,genders:HashTable<Symbol,Gender>) -> False : - do(check-genders-e{info,_,genders},e) - match(e) : - (e:WRef) : false - (e:WSubField) : false - (e:WSubIndex) : false - (e:WSubAccess) : false - (e:DoPrim) : - for e in args(e) do : - check-gender(info,genders,e,MALE) - (e:Mux) : do(check-gender{info,genders,_,MALE},e) - (e:ValidIf) : do(check-gender{info,genders,_,MALE},e) - (e:UIntValue) : false - (e:SIntValue) : false - - defn check-genders-s (s:Stmt,genders:HashTable<Symbol,Gender>) -> False : - do(check-genders-e{info(s),_:Expression,genders},s) - do(check-genders-s{_:Stmt,genders},s) - match(s) : - (s:DefWire) : genders[name(s)] = BI-GENDER - (s:DefPoison) : genders[name(s)] = MALE - (s:DefRegister) : genders[name(s)] = BI-GENDER - (s:DefNode) : - check-gender(info(s),genders,value(s),MALE) - genders[name(s)] = MALE - (s:DefMemory) : genders[name(s)] = MALE - (s:WDefInstance) : genders[name(s)] = MALE - (s:Connect) : - check-gender(info(s),genders,loc(s),FEMALE) - check-gender(info(s),genders,exp(s),MALE) - (s:Print) : - for x in args(s) do : - check-gender(info(s),genders,x,MALE) - check-gender(info(s),genders,en(s),MALE) - check-gender(info(s),genders,clk(s),MALE) - (s:BulkConnect) : - check-gender(info(s),genders,loc(s),FEMALE) - check-gender(info(s),genders,exp(s),MALE) - (s:Conditionally) : - check-gender(info(s),genders,pred(s),MALE) - (s:Empty) : false - (s:Stop) : - check-gender(info(s),genders,en(s),MALE) - check-gender(info(s),genders,clk(s),MALE) - (s:Begin|IsInvalid) : false - - for m in modules(c) do : - mname = name(m) - val genders = HashTable<Symbol,Gender>(symbol-hash) - for p in ports(m) do : - genders[name(p)] = dir-to-gender(direction(p)) - match(m) : - (m:ExModule) : false - (m:InModule) : check-genders-s(body(m),genders) - throw(PassExceptions(errors)) when not empty?(errors) - c - -;================= Width Check ========================== -;AFTER WIDTH INFERENCE -; * No names -; * No Unknowns -; * All widths are positive -; * widths are large enough to contain value - - -public defstruct CheckWidths <: Pass -public defmethod pass (b:CheckWidths) -> (Circuit -> Circuit) : check-width -public defmethod name (b:CheckWidths) -> String : "Width Check" -public defmethod short-name (b:CheckWidths) -> String : "width-check" - -;----------------- Errors ------------------------ - -defn UninferredWidth (info:FileInfo) : - PassException $ string-join $ - [info ": [module " mname "] Uninferred width."] - -defn WidthTooSmall (info:FileInfo,v:String) : - PassException $ string-join $ - [info ": [module " mname "] Width too small for constant " v "."] - -;---------------- Helper Functions -------------- - -;--------------- Check Width Pass ------------------- -public defn check-width (c:Circuit) -> Circuit : - val errors = Vector<PassException>() - - defn check-width-m (m:Module) -> False : - defn check-width-w (info:FileInfo,w:Width) -> Width : - match(w) : - (w:IntWidth) : - if width(w) <= to-long(0) : add(errors,NegWidth()) - (w) : - add(errors,UninferredWidth(info)) - w - - defn check-width-e (info:FileInfo,e:Expression) -> Expression : - match(map(check-width-e{info,_},e)) : - (e:UIntValue) : - match(width(e)) : - (w:IntWidth) : - if max(to-long(1),to-long(req-num-bits(value(e)) - 1)) > width(w) : - add(errors,WidthTooSmall(info,to-string(value(e)))) - (w) : add(errors,UninferredWidth(info)) - check-width-w(info,width(e)) - (e:SIntValue) : - match(width(e)) : - (w:IntWidth) : - if to-long(req-num-bits(value(e))) > width(w) : - add(errors,WidthTooSmall(info,to-string(value(e)))) - (w) : add(errors,UninferredWidth(info)) - check-width-w(info,width(e)) - (e:DoPrim) : false - (e) : false - - ;mapr(check-width-w{info,_},type(map(check-width-e{info,_},e))) - e - - defn check-width-s (s:Stmt) -> Stmt : - sinfo! = info(s) - map(check-width-e{info(s),_},map(check-width-s,s)) - map(mapr{check-width-w{info(s),_},_:Type},s) - - for p in ports(m) do : - mapr(check-width-w{info(p),_},type(p)) - - match(m) : - (m:ExModule) : false - (m:InModule) : check-width-s(body(m)) - false - - for m in modules(c) do : - mname = name(m) - check-width-m(m) - throw(PassExceptions(errors)) when not empty?(errors) - c - - -;================ Initialization Check ================== -; Error on all componenents that are not connected to. - -public defstruct CheckInitialization <: Pass -public defmethod pass (b:CheckInitialization) -> (Circuit -> Circuit) : check-init -public defmethod name (b:CheckInitialization) -> String : "Check Initialization" -public defmethod short-name (b:CheckInitialization) -> String : "check-init" - -;----------------- Errors ------------------------ - -defn RefNotInitialized (info:FileInfo, name:Symbol) : - PassException $ string-join $ - [info ": [module " mname "] Reference " name " is not fully initialized."] - -;------------ Helper Functions ------------- - -;------------ Pass ------------------ - -public defn check-init (c:Circuit) : - val errors = Vector<PassException>() - - defn check-init-m (m:InModule) : - defn get-name (e:Expression) -> Symbol : - match(e) : - (e:WRef) : name(e) - (e:WSubField) : symbol-join([get-name(exp(e)) `. name(e)]) - (e:WSubIndex) : symbol-join([get-name(exp(e)) to-symbol("[") value(e) to-symbol("]")]) - (e) : error("Shouldn't be here") - defn has-void? (e:Expression) -> True|False : - var void? = false - defn has-void (e:Expression) -> Expression : - match(e) : - (e:WVoid) : - void? = true - e - (e) : map(has-void,e) - has-void(e) - void? - defn check-init-s (s:Stmt) -> Stmt : - match(s) : - (s:Connect) : - if has-void?(exp(s)) : add(errors,RefNotInitialized(info(s),get-name(loc(s)))) - s - (s) : map(check-init-s,s) - - check-init-s(body(m)) - - for m in modules(c) do : - mname = name(m) - match(m) : - (m:InModule) : check-init-m(m) - (m) : false - - throw(PassExceptions(errors)) when not empty?(errors) - c - -;;================= Low Form Check ========================== -;;AFTER LOWERING -;; o All things connect to once -;; o no reg -;; o no accessors -;; o only vecs are for memories -;; o no bundles (future, will have them for mems) -;; o only predicated conditional connects -; -;public defstruct CheckLowForm <: Pass -;public defmethod pass (b:CheckLowForm) -> (Circuit -> Circuit) : check-low-form -;public defmethod name (b:CheckLowForm) -> String : "Low Form Check" -;public defmethod short-name (b:CheckLowForm) -> String : "low-form-check" -; -;;----------------- Errors ------------------------ -;defn InvalidVec (info:FileInfo,name:Symbol) : -; PassException $ string-join $ -; [info ": [module " mname "] Expression " name " has an illegal vector type."] -; -;defn InvalidBundle (info:FileInfo,name:Symbol) : -; PassException $ string-join $ -; [info ": [module " mname "] Expression " name " has an illegal bundle type."] -; -;defn NoWhen (info:FileInfo) : -; PassException $ string-join $ -; [info ": [module " mname "] Illegal when statement. No when statements with multiple statements are allowed in low firrtl."] -; -;defn SingleAssignment (info:FileInfo,name:Symbol) : -; PassException $ string-join $ -; [info ": [module " mname "] Illegal assignment to " name ". Wires can only be assigned to once."] -; -;defn NoOnReset (info:FileInfo) : -; PassException $ string-join $ -; [info ": [module " mname "] Invalid use of on-reset. No on-resets are allowed in low firrtl."] -; -;defn NoBulkConnect (info:FileInfo) : -; PassException $ string-join $ -; [info ": [module " mname "] Invalid use of <>. No <>'s are allowed in low firrtl."] -; -;;---------------- Helper Functions -------------- -; -;;--------------- Check Low Form Pass ------------------- -;public defn check-low-form (c:Circuit) -> Circuit : -; val errors = Vector<PassException>() -; -; defn check-low-form-t (info:FileInfo,t:Type,name:Symbol) -> False : -; match(t) : -; (t:VectorType) : add(errors,InvalidVec(info,name)) -; (t:BundleType) : add(errors,InvalidBundle(info,name)) -; (t) : false -; -; defn check-low-form-m (m:Module) -> False : -; for p in ports(m) do : -; check-low-form-t(info(p),type(p),name(p)) -; -; val assigned? = HashTable<Symbol,True>(symbol-hash) -; val insts = Vector<Symbol>() -; val mems = Vector<Symbol>() -; defn check-correct-exp (info:FileInfo,e:Expression) -> False : -; do(check-correct-exp{info,_:Expression},e) -; match(e) : -; (e:Ref) : -; if contains?(insts,name(e)) : -; for f in fields(type(e) as BundleType) do : -; check-low-form-t(info,type(f),name(e)) -; if contains?(mems,name(e)) : -; check-low-form-t(info,type(type(e) as VectorType),name(e)) -; (e) : false ;check-low-form-t(info,type(e),to-symbol $ to-string(e)) -; defn check-low-form-s (s:Stmt) -> False : -; match(s) : -; (s:DefWire) : -; check-low-form-t(info(s),type(s),name(s)) -; (s:DefPoison) : -; check-low-form-t(info(s),type(s),name(s)) -; (s:DefMemory) : -; check-low-form-t(info(s),type(s),name(s)) -; add(mems,name(s)) -; (s:DefInstance) : -; for f in fields(type(module(s)) as BundleType) do : -; check-low-form-t(info(s),type(f),name(s)) -; add(insts,name(s)) -; (s:DefNode) : -; check-correct-exp(info(s),value(s)) -; (s:Print) : -; for x in args(s) do : -; check-correct-exp(info(s),x) -; (s:DefRegister) : false -; (s:DefAccessor) : false -; (s:Conditionally) : -; if (not alt(s) typeof Empty) or (conseq(s) typeof Begin) : add(errors,NoWhen(info(s))) -; (s:OnReset) : add(errors,NoOnReset(info(s))) -; (s:BulkConnect) : add(errors,NoBulkConnect(info(s))) -; (s:Connect) : -; check-correct-exp(info(s),exp(s)) -; match(loc(s)) : -; (e:Ref|Subfield) : -; val n* = to-symbol $ to-string $ e -; if key?(assigned?,n*) : add(errors,SingleAssignment(info(s),n*)) -; else : assigned?[to-symbol $ to-string $ e] = true -; (e) : check-correct-exp(info(s),e) -; (s:Empty) : false -; (s:Stop) : false -; (s:Begin) : do(check-low-form-s,s) -; -; match(m) : -; (m:ExModule) : false -; (m:InModule) : check-low-form-s(body(m)) -; false -; -; for m in modules(c) do : -; mname = name(m) -; check-low-form-m(m) -; throw(PassExceptions(errors)) when not empty?(errors) -; c -; diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza deleted file mode 100644 index fdb7659a..00000000 --- a/src/main/stanza/firrtl-ir.stanza +++ /dev/null @@ -1,238 +0,0 @@ -;Copyright (c) 2014 - 2016 The Regents of the University of -;California (Regents). All Rights Reserved. Redistribution and use in -;source and binary forms, with or without modification, are permitted -;provided that the following conditions are met: -; * Redistributions of source code must retain the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer. -; * Redistributions in binary form must reproduce the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer in the documentation and/or other materials -; provided with the distribution. -; * Neither the name of the Regents nor the names of its contributors -; may be used to endorse or promote products derived from this -; software without specific prior written permission. -;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, -;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF -;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT -;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF -;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION -;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR -;MODIFICATIONS. -defpackage firrtl/ir2 : - import core - import verse - import bigint2 - -public defmulti info! (x:?) -> FileInfo -public defmethod info! (x:?) : FileInfo() - -public val vector-expand-delin = `$ -public val bundle-expand-delin = `$ -public val module-expand-delin = `$ -public val scope-delin = `_ -public val inline-delin = `_ -public val delin = `_ - -public definterface Direction -public val INPUT = new Direction -public val OUTPUT = new Direction - -public definterface Flip -public val DEFAULT = new Flip -public val REVERSE = new Flip - -public definterface Width -public defstruct UnknownWidth <: Width -public defn IntWidth (width:Int) : IntWidth(to-long(width)) -public defstruct IntWidth <: Width : - width: Long - -public definterface PrimOp -public val ADD-OP = new PrimOp -public val SUB-OP = new PrimOp -public val MUL-OP = new PrimOp -public val DIV-OP = new PrimOp -public val REM-OP = new PrimOp -public val LESS-OP = new PrimOp -public val LESS-EQ-OP = new PrimOp -public val GREATER-OP = new PrimOp -public val GREATER-EQ-OP = new PrimOp -public val NEQUAL-OP = new PrimOp -public val EQUAL-OP = new PrimOp -public val PAD-OP = new PrimOp -public val AS-UINT-OP = new PrimOp -public val AS-SINT-OP = new PrimOp -public val AS-CLOCK-OP = new PrimOp -public val SHIFT-LEFT-OP = new PrimOp -public val SHIFT-RIGHT-OP = new PrimOp -public val DYN-SHIFT-LEFT-OP = new PrimOp -public val DYN-SHIFT-RIGHT-OP = new PrimOp -public val NEG-OP = new PrimOp -public val CONVERT-OP = new PrimOp -public val NOT-OP = new PrimOp -public val AND-OP = new PrimOp -public val OR-OP = new PrimOp -public val XOR-OP = new PrimOp -public val AND-REDUCE-OP = new PrimOp -public val OR-REDUCE-OP = new PrimOp -public val XOR-REDUCE-OP = new PrimOp -public val CONCAT-OP = new PrimOp -public val BITS-SELECT-OP = new PrimOp -public val HEAD-OP = new PrimOp -public val TAIL-OP = new PrimOp - -public definterface Expression -public defmulti type (e:Expression) -> Type - -public defstruct Ref <: Expression : - name: Symbol - type: Type with: (as-method => true) -public defstruct SubField <: Expression : - exp: Expression - name: Symbol - type: Type with: (as-method => true) -public defstruct SubIndex <: Expression : - exp: Expression - value: Int - type: Type with: (as-method => true) -public defstruct SubAccess <: Expression : - exp: Expression - index: Expression - type: Type with: (as-method => true) -public defstruct Mux <: Expression : - cond: Expression - tval: Expression - fval: Expression - type: Type with: (as-method => true) -public defstruct ValidIf <: Expression : - cond: Expression - value: Expression - type: Type with: (as-method => true) -public defstruct UIntValue <: Expression : - value: BigInt - width: Width -public defstruct SIntValue <: Expression : - value: BigInt - width: Width -public defstruct DoPrim <: Expression : - op: PrimOp - args: List<Expression> - consts: List<Int> - type: Type with: (as-method => true) - -public definterface Stmt -public defmulti info (s:Stmt) -> FileInfo - -public defstruct DefWire <: Stmt : ;LOW - info: FileInfo with: (as-method => true) - name: Symbol - type: Type -public defstruct DefRegister <: Stmt : - info: FileInfo with: (as-method => true) - name: Symbol - type: Type - clock: Expression - reset: Expression - init: Expression -public defstruct DefInstance <: Stmt : ;LOW - info: FileInfo with: (as-method => true) - name: Symbol - module: Symbol -public defstruct DefMemory <: Stmt : ;LOW - info: FileInfo with: (as-method => true) - name: Symbol - data-type: Type - depth: Int - write-latency: Int - read-latency: Int - readers: List<Symbol> - writers: List<Symbol> - readwriters: List<Symbol> -public defstruct DefNode <: Stmt : ;LOW - info: FileInfo with: (as-method => true) - name: Symbol - value: Expression -public defstruct DefPoison <: Stmt : ;LOW - info: FileInfo with: (as-method => true) - name: Symbol - type: Type -public defstruct Conditionally <: Stmt : - info: FileInfo with: (as-method => true) - pred: Expression - conseq: Stmt - alt: Stmt -public defstruct Begin <: Stmt : ;LOW - body: List<Stmt> -public defstruct BulkConnect <: Stmt : - info: FileInfo with: (as-method => true) - loc: Expression - exp: Expression -public defstruct Connect <: Stmt : ;LOW - info: FileInfo with: (as-method => true) - loc: Expression - exp: Expression -public defstruct IsInvalid <: Stmt : ;LOW - info: FileInfo with: (as-method => true) - exp: Expression -public defstruct Stop <: Stmt : ;LOW - info: FileInfo with: (as-method => true) - ret: Int - clk: Expression - en: Expression -public defstruct Print <: Stmt : ;LOW - info: FileInfo with: (as-method => true) - string: String - args: List<Expression> - clk: Expression - en: Expression -public defstruct Empty <: Stmt ;LOW - - -public definterface Type -public defstruct UIntType <: Type : - width: Width -public defstruct SIntType <: Type : - width: Width -public defstruct BundleType <: Type : - fields: List<Field> -public defstruct VectorType <: Type : - type: Type - size: Int -public defstruct ClockType <: Type -public defstruct UnknownType <: Type - -public defstruct Field : - name: Symbol - flip: Flip - type: Type - -public defstruct Port : - info: FileInfo - name: Symbol - direction: Direction - type: Type - -public definterface Module -public defmulti name (m:Module) -> Symbol -public defmulti ports (m:Module) -> List<Port> -public defmulti info (m:Module) -> FileInfo - -public defstruct InModule <: Module : - info: FileInfo with: (as-method => true) - name: Symbol with: (as-method => true) - ports: List<Port> with: (as-method => true) - body: Stmt - -public defstruct ExModule <: Module : - info: FileInfo with: (as-method => true) - name: Symbol with: (as-method => true) - ports: List<Port> with: (as-method => true) - -public defstruct Circuit : - info: FileInfo - modules: List<Module> - main: Symbol diff --git a/src/main/stanza/firrtl-lexer.stanza b/src/main/stanza/firrtl-lexer.stanza deleted file mode 100644 index 1d119d00..00000000 --- a/src/main/stanza/firrtl-lexer.stanza +++ /dev/null @@ -1,596 +0,0 @@ -;Copyright (c) 2014 - 2016 The Regents of the University of -;California (Regents). All Rights Reserved. Redistribution and use in -;source and binary forms, with or without modification, are permitted -;provided that the following conditions are met: -; * Redistributions of source code must retain the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer. -; * Redistributions in binary form must reproduce the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer in the documentation and/or other materials -; provided with the distribution. -; * Neither the name of the Regents nor the names of its contributors -; may be used to endorse or promote products derived from this -; software without specific prior written permission. -;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, -;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF -;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT -;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF -;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION -;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR -;MODIFICATIONS. -defpackage firrtl/lexer : - import core - import core/stringeater - import verse - import bigint2 - -;=============== PUBLIC INTERFACE =========================== -public defn lex (text:String) -> List<Token> : - lex-all-forms(StringEater(text, "NOFILE")) - -public defn lex-file (filename:String) -> List<Token> : - println-all(["Reading " filename]) - val eater = StringEater(read-file(filename), filename) - lex-all-forms(eater) - -public defn lex-form (eater:StringEater) : - init-lexer(eater) - eat-lexeme() - while (EATER[0] != false) and not empty?(SCOPES) : - eat-lexeme() - val form = head(lex-all(group-all())) - throw(LexerExceptions(ERRORS)) when not empty?(ERRORS) - form - -public defn lex-all-forms (eater:StringEater) : - init-lexer(eater) - eat-all() - val grouped = group-all() - val form = lex-all(grouped) - throw(LexerExceptions(ERRORS)) when not empty?(ERRORS) - form - -;=============== TOKEN CLASSES ============================== -defstruct Indentation : - indent:Int -defmethod print (o:OutputStream, i:Indentation) : - print-all(o, ["[Indentation " indent(i) "]"]) - -defstruct OpenToken : - symbol:Symbol -defmethod print (o:OutputStream, t:OpenToken) : - print-all(o, ["OPEN[" symbol(t) "]"]) - -defstruct CloseToken : - symbol:Symbol -defmethod print (o:OutputStream, t:CloseToken) : - print-all(o, ["CLOSE[" symbol(t) "]"]) - -defstruct PuncToken : - symbol:Symbol -defmethod print (o:OutputStream, t:PuncToken) : - print-all(o, ["PUNC[" symbol(t) "]"]) - -;=============== LEXER STATE ================================ -var LEXEMES: Vector<Token> -var SCOPES: Vector<Symbol> -var ERRORS: Vector<LexerException> -var EATER: StringEater -var STAR?: True|False - -defn init-lexer (eater:StringEater) : - EATER = eater - LEXEMES = Vector<Token>() - SCOPES = Vector<Symbol>() - ERRORS = Vector<LexerException>() - STAR? = false - -;================= CHARACTER CLASSES ======================== -val CHAR-CLASSES = String(256, to-char(0)) -defn class? (c, bit:Int) -> True|False : - match(c) : - (c:Char) : - val mask = to-int(CHAR-CLASSES[to-int(c as Char)]) - bit-set?(mask, bit) - (c) : - false - -defn tag-class (class:String, bit:Int) : - val tag = 1 << bit - for c in class do : - val i = to-int(c) - val mask = to-int(CHAR-CLASSES[i]) - val c2 = to-char(mask | tag) - CHAR-CLASSES[i] = c2 - -val DIGIT-CHAR = 0 -val ALPHA-CHAR = 1 -val PUNC-CHAR = 2 -val OPEN-BRACE-CHAR = 3 -val CLOSE-BRACE-CHAR = 4 -val OPERATOR-CHAR = 5 -val SYMBOL-CHAR = 6 -val WHITESPACE-CHAR = 7 - -let : - val digits = "0123456789" - val letters = "abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ" - tag-class(letters, ALPHA-CHAR) - tag-class("_?", ALPHA-CHAR) - tag-class(digits, DIGIT-CHAR) - tag-class("`", PUNC-CHAR) - tag-class(" ,", WHITESPACE-CHAR) - tag-class("([{<", OPEN-BRACE-CHAR) - tag-class(")]}>", CLOSE-BRACE-CHAR) - tag-class("~!@#$%^*+-=/", OPERATOR-CHAR) - tag-class("~!@#$%^*+-=/", SYMBOL-CHAR) - tag-class(".:<&|", OPERATOR-CHAR) - tag-class("_?", SYMBOL-CHAR) - tag-class(letters, SYMBOL-CHAR) - tag-class(digits, SYMBOL-CHAR) - -;================ LOW LEVEL PREDICATES ===================== -;Lexer Predicates -defn whitespace? (c) : class?(c, WHITESPACE-CHAR) -defn digit? (c) : class?(c, DIGIT-CHAR) -defn alpha? (c) : class?(c, ALPHA-CHAR) -defn punc? (c) : class?(c, PUNC-CHAR) -defn open-brace? (c) : class?(c, OPEN-BRACE-CHAR) -defn close-brace? (c) : class?(c, CLOSE-BRACE-CHAR) -defn number-char? (c) : digit?(c) or (c == '.') -defn symbol-char? (c) : class?(c, SYMBOL-CHAR) -defn operator-char? (c) : - if c == '>' : - empty?(SCOPES) or (peek(SCOPES) != `>) - else : - class?(c, OPERATOR-CHAR) - -;================ EATING FUNCTIONS ========================= -defn update-stack (info:FileInfo, c:Symbol) : - defn pop-stack () : - if empty?(SCOPES) : - throw(ExtraClosingToken(info, c)) - else if peek(SCOPES) != c : - throw(WrongClosingToken(info, peek(SCOPES), c)) - else : - pop(SCOPES) - - switch {c == _} : - `\|<| : add(SCOPES, `\|>|) - `\|[| : add(SCOPES, `\|]|) - `\|{| : add(SCOPES, `\|}|) - `\|(| : add(SCOPES, `\|)|) - `\|*<| : add(SCOPES, `\|>|) - `\|*[| : add(SCOPES, `\|]|) - `\|*{| : add(SCOPES, `\|}|) - `\|*(| : add(SCOPES, `\|)|) - `\|>| : pop-stack() - `\|]| : pop-stack() - `\|}| : pop-stack() - `\|)| : pop-stack() - -defn token-eaten (t:Token) : - ;Update Lexemes - add(LEXEMES, t) - - ;Update the stack - match(item(t)) : - (x:OpenToken) : update-stack(info(t), symbol(x)) - (x:CloseToken) : update-stack(info(t), symbol(x)) - (x) : false - - ;Update STAR? - STAR? = - match(item(t)) : - (x:CloseToken) : true - (x:Int|Float|Char|String) : true - (x:True|False) : true - (x:Symbol) : any?(alpha?, to-string(x)) - (x) : false - - true - -defn escape-char (c:Char) -> Char : - switch {c == _} : - 'n' : '\n' - '\\' : c - '"' : c - '\'' : c - '|' : c - else : throw(InvalidEscapeChar(info(EATER), c)) - -defn eat-escaped-chars () : - val buf = StringBuffer() - val end-char = EATER[0] - val end = loop(1) where : - defn* loop (i:Int) : - val c1 = EATER[i] - val c2 = EATER[i + 1] - if c1 == false : - false - else if c1 == end-char : - i + 1 - else if c1 == '\\' and c2 != false : - add(buf, escape-char(c2 as Char)) - loop(i + 2) - else : - add(buf, c1 as Char) - loop(i + 1) - if end != false : - eat(EATER, end as Int) - to-string(buf) - -defn eat-comment () -> True|False : - if EATER[0] == ';' : - while (EATER[0] != false and EATER[0] != '\n') : - eat(EATER) - true - -defn eat-string () : - val info = info(EATER) - if EATER[0] == '"' : - match(eat-escaped-chars()) : - (s:String) : token-eaten(Token(s, info)) - (s:False) : throw(UnclosedString(info)) - -defn eat-char () : - val info = info(EATER) - if EATER[0] == '\'' : - match(eat-escaped-chars()) : - (s:String) : - if length(s) == 1 : token-eaten(Token(s[0], info)) - else : throw(InvalidCharString(info)) - (s:False) : throw(UnclosedCharString(info)) - -defn eat-escaped-symbol () : - val info = info(EATER) - if EATER[0] == '\\' and EATER[1] == '|' : - eat(EATER) - match(eat-escaped-chars()) : - (s:String) : token-eaten(Token(to-symbol(s), info)) - (s:False) : throw(UnclosedSymbol(info)) - -defn symbol-end (start:Int) -> False|Int : - defn length (a?:True|False, i:Int) : - if symbol-char?(EATER[i]) : - length(a? or alpha?(EATER[i]), i + 1) - else if a? : - i - length(false, start) - -defn eat-symbol () : - match(symbol-end(0)) : - (len:Int) : - val info = info(EATER) - val str = eat(EATER, len) - switch {str == _} : - "true" : token-eaten(Token(true, info)) - "false" : token-eaten(Token(false, info)) - else : token-eaten(Token(to-symbol(str), info)) - (len:False) : - false - -defn eat-operator () : - val len = look-forward(0) where : - defn* look-forward (i:Int) : - if operator-char?(EATER[i]) : look-forward(i + 1) - else if alpha?(EATER[i]) : look-back(i - 1) - else : i - defn* look-back (i:Int) : - if symbol-char?(EATER[i]) : look-back(i - 1) - else : i + 1 - if len > 0 : - val info = info(EATER) - token-eaten(Token(to-symbol(eat(EATER, len)), info)) - -defn* eat-indent () : - val info = info(EATER) - val len = find({EATER[_] != ' '}, 0 to length(EATER) + 1) as Int - eat(EATER, len) - val indent = Token(Indentation(len), info) - if eat-comment() : - eat-indent() - else if EATER[0] == '\n' : - eat(EATER) - eat-indent() - else : - token-eaten(indent) - -defn eat-number () : - if digit?(EATER[0]) or - (EATER[0] == '-' and digit?(EATER[1])) : - - val info = info(EATER) - val end = find({not number-char?(EATER[_])}, 1 to length(EATER) + 1) as Int - val str = eat(EATER, end) - if contains?(str, '.') : - match(to-float(str)) : - (f:Float) : token-eaten(Token(f, info)) - (f:False) : throw(InvalidNumber(info)) - else : token-eaten(Token(to-int(str), info)) - ;else : token-eaten(Token(BigIntLit(str),info)) - ;else : - ;match(to-long(str)) : - ; (l:Long) : - ; if l < (to-long("2147483647") as Long) and l > (to-long("-2147483648") as Long) : token-eaten(Token(to-int(str), info)) - ; else : token-eaten(Token(l, info)) - ; (l:False) : token-eaten(Token(to-int(str), info)) - -defn eat-here-string () : - if EATER[0] == '\\' and EATER[1] == '<' : - val info = info(EATER) - eat(EATER) - val tag-len = - match(find({EATER[_] == '>'}, 0 to length(EATER))) : - (i:Int) : i + 1 - (n:False) : throw(InvalidTag(info)) - defn tag? (i:Int) : - for j in 0 to tag-len all? : - EATER[i + j] == EATER[j] - val str-len = - match(find(tag?, tag-len to length(EATER))) : - (i:Int) : i - tag-len - (n:False) : throw(NoEndTagFound(info)) - eat(EATER, tag-len) - val str = eat(EATER, str-len) - eat(EATER, tag-len) - token-eaten(Token(str, info)) - -defn eat-structural-token () : - val info = info(EATER) - if open-brace?(EATER[0]) : - token-eaten(Token(OpenToken(to-symbol(eat(EATER))), info)) - else if close-brace?(EATER[0]) : - token-eaten(Token(CloseToken(to-symbol(eat(EATER))), info)) - else if punc?(EATER[0]) : - token-eaten(Token(PuncToken(to-symbol(eat(EATER))), info)) - -defn eat-star-token () : - val info = info(EATER) - if open-brace?(EATER[0]) : - token-eaten(Token(OpenToken(symbol-join(["*" eat(EATER)])), info)) - -defn eat-capture () : - if (EATER[0] == '?') : - match(symbol-end(1)) : - (end:Int) : - val pinfo = info(EATER) - token-eaten(Token(PuncToken(to-symbol(eat(EATER))), pinfo)) - val info = info(EATER) - token-eaten(Token(to-symbol(eat(EATER, end - 1)), info)) - (end:False) : - false - -defn eat-lexeme! () : - val ate? = - eat-capture() or - eat-here-string() or - eat-escaped-symbol() or - eat-char() or - eat-string() or - eat-number() or - eat-symbol() or - eat-operator() or - eat-structural-token() - if ate? : - eat-star-token() when STAR? - else : throw(InvalidToken(info(EATER))) - -defn eat-whitespace () : - if whitespace?(EATER[0]) : - while whitespace?(EATER[0]) : - eat(EATER) - STAR? = false - -defn eat-lexeme () : - eat-whitespace() - if EATER[0] != false : - if eat-comment() : - eat-lexeme() - else if EATER[0] == '\n' : - eat(EATER) - eat-indent() - else : - eat-lexeme!() - -defn eat-all () : - while EATER[0] != false : - eat-lexeme() - -;================ GROUPING ================================== -val OPEN-PAREN = `\|(| -val STAR-PAREN = `\|*(| -val CLOSE-PAREN = `\|)| -val OPEN-BRACKET = `\|{| -val STAR-BRACKET = `\|*{| -val CLOSE-BRACKET = `\|}| -val OPEN-BRACE = `\|[| -val STAR-BRACE = `\|*[| -val CLOSE-BRACE = `\|]| -val STAR-ANGLE = `\|*<| -val CLOSE-ANGLE = `\|>| -val COLON = `: -val QUESTION = `? -val BACKTICK = `\|`| - -defn matching-end (s:Symbol) : - if s == OPEN-PAREN : CLOSE-PAREN - else if s == STAR-PAREN : CLOSE-PAREN - else if s == OPEN-BRACKET : CLOSE-BRACKET - else if s == STAR-BRACKET : CLOSE-BRACKET - else if s == OPEN-BRACE : CLOSE-BRACE - else if s == STAR-BRACE : CLOSE-BRACE - else if s == STAR-ANGLE : CLOSE-ANGLE - else : error("No matching end") - -var START-INFO = false -var TOKEN-STREAM : Vector<Token> -defn group-all () -> List : - TOKEN-STREAM = Vector<Token>(length(LEXEMES)) - while not empty?(LEXEMES) : - add(TOKEN-STREAM, pop(LEXEMES)) - group-rest(false) - -defn group-rest (end) -> List : - if empty?(TOKEN-STREAM) : - match(end) : - (end:Symbol) : - throw(NoClosingToken(START-INFO as FileInfo, end)) - (end) : - List() - else : - val x = peek(TOKEN-STREAM) - match(item(x)) : - (t:CloseToken) : - match(end) : - (end:Symbol) : - pop(TOKEN-STREAM) - List() - (end:Indentation) : - List() - (t:OpenToken) : - pop(TOKEN-STREAM) - val old-info = START-INFO - START-INFO = info(x) - val g = group-rest(matching-end(symbol(t))) - START-INFO = old-info - List(List(x, g), group-rest(end)) - (t:PuncToken) : - pop(TOKEN-STREAM) - List(x, group-rest(end)) - (s:Symbol) : - pop(TOKEN-STREAM) - if s == COLON : - match(item(peek(TOKEN-STREAM))) : - (i:Indentation) : - val y = pop(TOKEN-STREAM) - val g = group-rest(i) - List(x, List(y, g), group-rest(end)) - (t) : - List(x, group-rest(end)) - else : - List(x, group-rest(end)) - (i:Indentation) : - if (end typeof Indentation) and - (indent(i) < indent(end as Indentation)) : - List() - else : - pop(TOKEN-STREAM) - group-rest(end) - (t) : - pop(TOKEN-STREAM) - List(x, group-rest(end)) - -;============== ADDING SHORTCUTS ============================ -defn indentation? (x) : - unwrap-token(x) typeof Indentation -defn opentoken? (x, s:Symbol) : - match(unwrap-token(x)) : - (x:OpenToken) : symbol(x) == s - (x) : false -defn opentoken? (x, s:Streamable<Symbol>) : - match(unwrap-token(x)) : - (x:OpenToken) : contains?(s, symbol(x)) - (x) : false -defn punctoken? (x, s:Symbol) : - match(unwrap-token(x)) : - (x:PuncToken) : symbol(x) == s - (x) : false -defn startoken-pending? (xs:List) : - if not empty?(xs) : - match(head(xs)) : - (x:FullList) : opentoken?(head(x), [STAR-PAREN, STAR-BRACE, STAR-BRACKET, STAR-ANGLE]) - (x) : false - -defn lex-atom (x) -> ? : - match(x) : - (x:Token) : - map(lex-atom, x) - (x:FullList) : - if indentation?(head(x)) : lex-all(tail(x)) - else if opentoken?(head(x), OPEN-PAREN) : lex-all(tail(x)) - else if opentoken?(head(x), OPEN-BRACE) : List(`@tuple, lex-all(tail(x))) - else if opentoken?(head(x), OPEN-BRACKET) : List(`@afn, lex-all(tail(x))) - else if opentoken?(head(x), STAR-PAREN) : List(`@do, lex-all(tail(x))) - else if opentoken?(head(x), STAR-BRACE) : List(`@get, lex-all(tail(x))) - else if opentoken?(head(x), STAR-BRACKET) : List(`@do-afn, lex-all(tail(x))) - else if opentoken?(head(x), STAR-ANGLE) : List(`@of, lex-all(tail(x))) - else : error(string-join(["Invalid grouped form: " x])) - (x) : x - -defn lex-all (xs:List) -> List : - if empty?(xs) : - xs - else if punctoken?(head(xs), QUESTION) : - val capped = list(OpenToken(`\|(|), `@cap, xs[1]) - lex-all(List(capped, tailn(xs, 2))) - else if punctoken?(head(xs), BACKTICK) : - if empty?(tail(xs)) : - `(@quote) - else : - val rest = lex-all(tail(xs)) - List(list(`@quote, head(rest)), tail(rest)) - else : - List(lex-atom(head(xs)), lex-all(tail(xs))) - -;============== LEXER ERRORS ================================ -definterface LexerException <: Exception -defn LexerException (s:String) : - new LexerException : - defmethod print (o:OutputStream, this) : - print(o, s) - -defn LexerExceptions (xs:Streamable<LexerException>) : - LexerException(string-join(xs, "\n")) - -defn NoClosingToken (info:FileInfo, end:Symbol) : - LexerException $ string-join $ - [info ": No closing token found. Expecting " end "."] - -defn InvalidNumber (info:FileInfo) : - LexerException $ string-join $ - [info ": Invalid number."] - -defn InvalidToken (info:FileInfo) : - LexerException $ string-join $ - [info ": Invalid token."] - -defn InvalidEscapeChar (info:FileInfo, c:Char) : - LexerException $ string-join $ - [info ": Invalid escape character: " c "."] - -defn UnclosedString (info:FileInfo) : - LexerException $ string-join $ - [info ": Unclosed string. "] - -defn UnclosedCharString (info:FileInfo) : - LexerException $ string-join $ - [info ": Unclosed character. "] - -defn UnclosedSymbol (info:FileInfo) : - LexerException $ string-join $ - [info ": Unclosed symbol. "] - -defn InvalidCharString (info:FileInfo) : - LexerException $ string-join $ - [info ": Invalid character string. Must have length 1."] - -defn WrongClosingToken (info:FileInfo, expected:Symbol, actual:Symbol) : - LexerException $ string-join $ - [info ": Wrong closing parenthesis. Expecting " expected " but got " actual "."] - -defn ExtraClosingToken (info:FileInfo, c:Symbol) : - LexerException $ string-join $ - [info ": Extra closing token found: " c "."] - -defn InvalidTag (info:FileInfo) : - LexerException $ string-join $ - [info ": Invalid tag for here string."] - -defn NoEndTagFound (info:FileInfo) : - LexerException $ string-join $ - [info ": No ending tag found for here string."] diff --git a/src/main/stanza/firrtl-main.stanza b/src/main/stanza/firrtl-main.stanza deleted file mode 100644 index 362961af..00000000 --- a/src/main/stanza/firrtl-main.stanza +++ /dev/null @@ -1,57 +0,0 @@ -;Copyright (c) 2014 - 2016 The Regents of the University of -;California (Regents). All Rights Reserved. Redistribution and use in -;source and binary forms, with or without modification, are permitted -;provided that the following conditions are met: -; * Redistributions of source code must retain the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer. -; * Redistributions in binary form must reproduce the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer in the documentation and/or other materials -; provided with the distribution. -; * Neither the name of the Regents nor the names of its contributors -; may be used to endorse or promote products derived from this -; software without specific prior written permission. -;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, -;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF -;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT -;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF -;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION -;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR -;MODIFICATIONS. -#include<"core/stringeater.stanza"> -#include<"core/macro-utils.stanza"> -#include<"compiler/stz-algorithms.stanza"> -#include<"compiler/stz-parser.stanza"> -#include<"compiler/stz-lexer.stanza"> -#include("firrtl-lexer.stanza") -#include("firrtl-ir.stanza") -#include("ir-utils.stanza") -#include("ir-parser.stanza") -#include("passes.stanza") -#include("primop.stanza") -#include("errors.stanza") -#include("symbolic-value.stanza") - -defpackage firrtl-main : - import core - import verse - import firrtl/parser - import firrtl/passes - import firrtl/lexer - import stz/parser - import firrtl/ir-utils - -defn main () : - val arg = commandline-arguments() - val args = split(arg,' ') - val lexed = lex-file(args[1]) - val c = parse-firrtl(lexed) - ;println(c) - run-passes(c,to-list(args[2])) - -main() - diff --git a/src/main/stanza/firrtl-test-main.stanza b/src/main/stanza/firrtl-test-main.stanza deleted file mode 100644 index 4fcc9dee..00000000 --- a/src/main/stanza/firrtl-test-main.stanza +++ /dev/null @@ -1,177 +0,0 @@ -;Copyright (c) 2014 - 2016 The Regents of the University of -;California (Regents). All Rights Reserved. Redistribution and use in -;source and binary forms, with or without modification, are permitted -;provided that the following conditions are met: -; * Redistributions of source code must retain the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer. -; * Redistributions in binary form must reproduce the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer in the documentation and/or other materials -; provided with the distribution. -; * Neither the name of the Regents nor the names of its contributors -; may be used to endorse or promote products derived from this -; software without specific prior written permission. -;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, -;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF -;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT -;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF -;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION -;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR -;MODIFICATIONS. -#include<"core/stringeater.stanza"> -#include<"core/macro-utils.stanza"> -#include<"compiler/stz-algorithms.stanza"> -#include<"compiler/stz-parser.stanza"> -#include<"compiler/stz-lexer.stanza"> -#include("bigint2.stanza") -#include("firrtl-lexer.stanza") -#include("firrtl-ir.stanza") -#include("ir-utils.stanza") -#include("ir-parser.stanza") -#include("passes.stanza") -#include("chirrtl.stanza") -#include("primop.stanza") -#include("errors.stanza") -#include("compilers.stanza") -#include("firrtl.stanza") -;#include("flo.stanza") -;#include("verilog.stanza") -;#include("symbolic-value.stanza") - -;Custom Packages -;#include("custom-passes.stanza") -;#include("custom-compiler.stanza") - -defpackage firrtl-main : - import core - import verse - import firrtl/parser - import firrtl/passes - import firrtl/ir2 - import firrtl/lexer - import stz/parser - import firrtl/ir-utils - import firrtl/compiler - import firrtl/chirrtl - import firrtl/firrtl - ;Custom Packages - ;import firrtl/custom-passes - ;import firrtl/custom-compiler - -defn set-printvars! (p:List<Char>) : - if contains(p,'t') : PRINT-TYPES = true - if contains(p,'k') : PRINT-KINDS = true - if contains(p,'w') : PRINT-WIDTHS = true - if contains(p,'T') : PRINT-TWIDTHS = true - if contains(p,'g') : PRINT-GENDERS = true - if contains(p,'c') : PRINT-CIRCUITS = true - if contains(p,'d') : PRINT-DEBUG = true - if contains(p,'i') : PRINT-INFO = true - -defn get-passes (pass-names:List<String>) -> List<Pass> : - for n in pass-names map : - val p = for p in append(standard-passes,chirrtl-passes) find : - n == short-name(p) - if p == false : - error(to-string $ ["Unrecognized pass flag: " n]) - p as Pass - -defn main () : - val args = commandline-arguments() - var input = false - var output = false - var firms = Vector<String>() - var compiler = false - val pass-names = Vector<String>() - val pass-args = Vector<String>() - var printvars = "" - var last-s = "" - var backend = false - - val prev-out = CURRENT-OUTPUT-STREAM - CURRENT-OUTPUT-STREAM = STANDARD-ERROR - - - for (s in args, i in 0 to false) do : - if s == "-i" : last-s = s - else if s == "-o" : last-s = s - else if s == "-x" : last-s = s - else if s == "-X" : last-s = s - else if s == "-p" : last-s = s - else if s == "-s" : last-s = s - else if s == "-m" : last-s = s - else if s == "-b" : last-s = s - else : - if last-s == "-i" : input = args[i] - if last-s == "-o" : output = args[i] - if last-s == "-x" : add(pass-names,args[i]) - if last-s == "-X" : compiler = args[i] - if last-s == "-p" : printvars = to-string([printvars args[i]]) - if last-s == "-s" : add(pass-args,args[i]) - if last-s == "-m" : add(firms,args[i]) - if last-s == "-b" : backend = args[i] - - var with-output = - fn (f:()->False) : - val prev-stream = CURRENT-OUTPUT-STREAM - CURRENT-OUTPUT-STREAM = STANDARD-OUTPUT - f() - CURRENT-OUTPUT-STREAM = prev-stream - - if input == false : - error("No input file provided. Use -i flag.") - if output != false and output != "-": - with-output = - fn (f:()->False) : - val prev-stream = CURRENT-OUTPUT-STREAM - val out-stream = FileOutputStream(output as String) - CURRENT-OUTPUT-STREAM = out-stream - f() - CURRENT-OUTPUT-STREAM = prev-stream - close(out-stream) - - if compiler == false and backend == false and length(pass-names) == 0 : - error("Must specify a compiler or a backend. Use -X flag or -b flag.") - - val lexed = lex-file(input as String) - val circuit = parse-firrtl(lexed) - - val modules* = Vector<Module>() - for m in modules(circuit) do : - add(modules*,m) - - val included-c = - for m in firms map : - val lexed = lex-file(m as String) - parse-firrtl(lexed) - - for c in included-c do : - for m in modules(c) do : - add(modules*,m) - - val circuit* = Circuit(info(circuit),to-list(modules*),main(circuit)) - - set-printvars!(to-list(printvars)) - - if compiler == false : - var c*:Circuit = run-passes(circuit*,get-passes(to-list(pass-names))) - switch {_ == backend} : - "verilog" : run-backend(c*,LoToVerilog(with-output)) - "firrtl" : run-backend(c*,FIRRTL(with-output)) - else : error("Invalid backend flag!") - else : - switch {_ == compiler} : - ;"flo" : error("Flo backend not currently supported.") - ; run-passes(circuit*,StandardFlo(with-output)) - "verilog" : run-passes(circuit*,StandardVerilog(with-output)) - "firrtl" : run-passes(circuit*,StandardFIRRTL(with-output)) - "lofirrtl" : run-passes(circuit*,StandardLoFIRRTL(with-output)) - ;"verilute" : run-passes(circuit*,InstrumentedVerilog(with-output,to-list $ pass-args)) - else : error("Invalid compiler flag") - - CURRENT-OUTPUT-STREAM = prev-out -main() diff --git a/src/main/stanza/firrtl.stanza b/src/main/stanza/firrtl.stanza deleted file mode 100644 index f51a13a6..00000000 --- a/src/main/stanza/firrtl.stanza +++ /dev/null @@ -1,45 +0,0 @@ -;Copyright (c) 2014 - 2016 The Regents of the University of -;California (Regents). All Rights Reserved. Redistribution and use in -;source and binary forms, with or without modification, are permitted -;provided that the following conditions are met: -; * Redistributions of source code must retain the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer. -; * Redistributions in binary form must reproduce the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer in the documentation and/or other materials -; provided with the distribution. -; * Neither the name of the Regents nor the names of its contributors -; may be used to endorse or promote products derived from this -; software without specific prior written permission. -;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, -;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF -;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT -;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF -;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION -;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR -;MODIFICATIONS. -defpackage firrtl/firrtl : - import core - import verse - import firrtl/ir-utils - import firrtl/ir2 - - -;============ FIRRTL ============== - -public defstruct FIRRTL <: Pass : - with-output: (() -> False) -> False -public defmethod pass (b:FIRRTL) -> (Circuit -> Circuit) : emit-firrtl{with-output(b),_} -public defmethod name (b:FIRRTL) -> String : "To FIRRTL" -public defmethod short-name (b:FIRRTL) -> String : "To FIRRTL" - -;============ Utilz ============= - -public defn emit-firrtl (with-output:(() -> False) -> False, c:Circuit) : - with-output $ fn () : - print(c) - c diff --git a/src/main/stanza/flo.stanza b/src/main/stanza/flo.stanza deleted file mode 100644 index ad04bb23..00000000 --- a/src/main/stanza/flo.stanza +++ /dev/null @@ -1,228 +0,0 @@ -;Copyright (c) 2014 - 2016 The Regents of the University of -;California (Regents). All Rights Reserved. Redistribution and use in -;source and binary forms, with or without modification, are permitted -;provided that the following conditions are met: -; * Redistributions of source code must retain the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer. -; * Redistributions in binary form must reproduce the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer in the documentation and/or other materials -; provided with the distribution. -; * Neither the name of the Regents nor the names of its contributors -; may be used to endorse or promote products derived from this -; software without specific prior written permission. -;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, -;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF -;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT -;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF -;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION -;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR -;MODIFICATIONS. -defpackage firrtl/flo : - import core - import verse - import firrtl/ir-utils - import firrtl/ir2 - import firrtl/passes - import bigint2 - -;============= Flo Backend ================ - -public defstruct Flo <: Pass : - with-output: (() -> False) -> False -public defmethod pass (b:Flo) -> (Circuit -> Circuit) : emit-flo{with-output(b),_} -public defmethod name (b:Flo) -> String : "To Flo" - -definterface FloKind -defstruct FRegKind <: FloKind -defstruct FWritePortKind <: FloKind : - mem: Expression - index: Expression -defstruct FOutputPortKind <: FloKind - -defn is-sint? (arg:Expression) -> True|False : type(arg) typeof SIntType -defn type (s:DefAccessor) -> Type : type(type(source(s)) as VectorType) - -defn flo-op-name (op:PrimOp, args:List<Expression>) -> String : - switch {op == _ } : - ADD-OP : "add" - ADD-WRAP-OP : "add" - SUB-OP : "sub" - SUB-WRAP-OP : "sub" - MUL-OP : "mul" ;; todo: signed version - DIV-OP : "div" ;; todo: signed version - REM-OP : "mod" ;; todo: signed version - QUO-OP : "div" ;; todo: signed version - REM-OP : "mod" ;; todo: signed version - LESS-OP : "lt" ;; todo: signed version - LESS-EQ-OP : "lte" ;; todo: swap args - GREATER-OP : "lt" ;; todo: swap args - GREATER-EQ-OP : "lte" ;; todo: signed version - NEQUIV-OP : "neq" - EQUIV-OP : "eq" - NEQUAL-OP : "neq" - EQUAL-OP : "eq" - MUX-OP : "mux" - NEG-OP : "neg" - AS-UINT-OP : "mov" - AS-SINT-OP : "mov" - SHIFT-LEFT-OP : "lsh" - SHIFT-RIGHT-OP : if is-sint?(args[0]): "arsh" else: "rsh" - DYN-SHIFT-LEFT-OP : "lsh" - DYN-SHIFT-RIGHT-OP : if is-sint?(args[0]): "arsh" else: "rsh" - PAD-OP : if is-sint?(args[0]): "arsh" else: "rsh" - CONVERT-OP : if is-sint?(args[0]): "arsh" else: "rsh" - BIT-AND-OP : "and" - BIT-NOT-OP : "not" - BIT-OR-OP : "or" - BIT-XOR-OP : "xor" - CONCAT-OP : "cat" - BIT-SELECT-OP : "rsh" - BITS-SELECT-OP : "rsh" - BIT-XOR-REDUCE-OP : "xorr" - else : - error $ string-join $ ["Unable to print Primop: " op] - -defn sane-width (wd:Width) -> Int|Long : - match(wd) : - (w:LongWidth) : max(to-long(1), width(w)) - (w) : error(string-join(["Unknown width: " w])) - -defn prim-width (type:Type) -> Int|Long : - match(type) : - (t:UIntType) : sane-width(width(t)) - (t:SIntType) : sane-width(width(t)) - (t:ClockType) : 1 - (t) : error("Bad prim width type") - -defn emit-all (es:Streamable, top:Symbol) : - for e in es do : - match(e) : - (ex:Expression) : emit!(ex,top) - (ex:String) : print(ex) - (ex:Symbol) : print(ex) - ;; (ex:Int) : print-all([ex "'" sizeof(ex)]) - (ex:Int) : print(ex) - (ex) : print(ex) - -defn emit! (e:Expression,top:Symbol) : - defn greater-op? (op: PrimOp) -> True|False : - contains?([GREATER-OP], op) - defn greater-eq-op? (op: PrimOp) -> True|False : - contains?([GREATER-EQ-OP], op) - defn less-eq-op? (op: PrimOp) -> True|False : - contains?([LESS-EQ-OP], op) - defn less-op? (op: PrimOp) -> True|False : - contains?([LESS-OP], op) - defn cmp-op? (op: PrimOp) -> True|False : - greater-op?(op) or greater-eq-op?(op) or less-op?(op) or less-eq-op?(op) or - contains?([EQUAL-OP NEQUAL-OP] op) - match(e) : - (e:Ref) : emit-all([top "::" name(e)], top) - (e:UIntValue) : emit-all([value(e) "'" sane-width(width(e))], top) - (e:SIntValue) : emit-all([value(e) "'" sane-width(width(e))], top) - (e:Subfield) : emit-all([exp(e) "/" name(e)], top) - (e:Index) : emit-all([exp(e) "/" value(e)], top) - (e:DoPrim) : - if cmp-op?(op(e)) : - emit-all([flo-op-name(op(e), args(e)) "'" prim-width(type(args(e)[0]))], top) - if greater-op?(op(e)) or greater-eq-op?(op(e)) : - emit-all([" " args(e)[1] " " args(e)[0]], top) - else : - emit-all([" " args(e)[0] " " args(e)[1]], top) - else if op(e) == BIT-SELECT-OP : - emit-all([flo-op-name(op(e), args(e)) "'1 " args(e)[0] " " consts(e)[0]], top) - else if op(e) == BITS-SELECT-OP : - val w = consts(e)[0] - consts(e)[1] + 1 - emit-all([flo-op-name(op(e), args(e)) "'" w " " args(e)[0] " " consts(e)[1]], top) - else if op(e) == CONCAT-OP : - val w = prim-width(type(args(e)[1])) - emit-all([flo-op-name(op(e), args(e)) "'" w " " args(e)[0] " " args(e)[1]], top) - else if op(e) == PAD-OP or op(e) == CONVERT-OP : - emit-all([flo-op-name(op(e), args(e)) "'" prim-width(type(e)) " " args(e)[0] " 0"], top) - else : - emit-all([flo-op-name(op(e), args(e)) "'" prim-width(type(e))], top) - for arg in args(e) do : - print(" ") - emit!(arg, top) - for const in consts(e) do : - print-all([" " const "'" req-num-bits(const)]) - (e) : error("SHOULDN'T EMIT THIS") ;; print-all(["EMIT(" e ")"]) - ;(e) : emit-all(["mov'" prim-width(type(e)) " " e], top) ;TODO, not sure which one is right - -defn maybe-mov (e:Expression) -> String : - val need-mov? = match(e) : - (e:Ref) : true - (e:UIntValue) : true - (e:SIntValue) : true - (e:Subfield) : true - (e:Index) : true - (e) : false - if need-mov?: "mov " else: "" - -defn emit-s (s:Stmt, flokinds:HashTable<Symbol,FloKind>, top:Symbol,sh:HashTable<Symbol,Int>) : - defn emit-connect (s:Connect, en:Expression) : - match(loc(s)) : - (r:Ref) : - val n = name(r) - if key?(flokinds,n) : - match(flokinds[n]) : - (k:FRegKind) : - emit-all(["reg'" prim-width(type(r)) " " en " " exp(s)], top) - (k:FWritePortKind) : - emit-all([top "::" n " = wr'" prim-width(type(r)) " " en " " mem(k) " " index(k) " " exp(s) "\n"], top) - (k:FOutputPortKind) : - emit-all([top "::" n " = out'" prim-width(type(r)) " " exp(s) "\n"], top) - (k) : error("Shouldn't be here") - else : - emit-all([top "::" n " = " maybe-mov(exp(s)) exp(s) "\n"], top) - (o) : - println-all(["CONNEcT LOC " loc(s)]) - error("Unknown Connect") - match(s) : - (s:DefWire) : "" - (s:DefPoison) : "" - (s:DefInstance) : error("Shouldn't be here") - (e:DefAccessor) : - if acc-dir == READ : - emit-all(["rd'" prim-width(type(e)) " " "1" " " source(e) " " index(e)], top) - (s:DefMemory) : - val vtype = type(s) as VectorType - emit-all([top "::" name(s) " = mem'" prim-width(type(vtype)) " " size(vtype) "\n"], top) - (s:DefNode) : - emit-all([top "::" name(s) " = " maybe-mov(value(s)) value(s) "\n"], top) - (s:Begin) : do(emit-s{_, flokinds, top,sh}, body(s)) - (s:Connect) : emit-connect(s,UIntValue(BigIntLit("1"),LongWidth(1))) - (s:Conditionally) : emit-connect(conseq(s) as Connect,pred(s)) - (s) : s - -defn emit-module (m:InModule,sh:HashTable<Symbol,Int>) : - val flokinds = HashTable<Symbol,FloKind>(symbol-hash) - defn build-table (s:Stmt) -> False : - do(build-table,s) - match(s) : - (s:DefRegister) : flokinds[name(s)] = FRegKind() - (s:DefAccessor) : - switch {_ == acc-dir(s)} : - WRITE : flokinds[name(s)] = FWritePortKind(source(s),index(s)) - else : false - (s) : false - - for port in ports(m) do : - if name(port) ==`reset : - emit-all([name(m) "::" name(port) " = rst'1\n"], name(m)) - else : switch {_ == direction(port)} : - INPUT : print-all([name(m) "::" name(port) " = " "in'" prim-width(type(port)) "\n"]) - OUTPUT : flokinds[name(port)] = FOutputPortKind() - emit-s(body(m), flokinds, name(m),sh) - -public defn emit-flo (with-output:(() -> False) -> False, c:Circuit) : - with-output $ { - emit-module(modules(c)[0] as InModule,get-sym-hash(modules(c)[0] as InModule)) - false - } - c diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza deleted file mode 100644 index 6bbfa432..00000000 --- a/src/main/stanza/ir-parser.stanza +++ /dev/null @@ -1,409 +0,0 @@ -;Copyright (c) 2014 - 2016 The Regents of the University of -;California (Regents). All Rights Reserved. Redistribution and use in -;source and binary forms, with or without modification, are permitted -;provided that the following conditions are met: -; * Redistributions of source code must retain the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer. -; * Redistributions in binary form must reproduce the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer in the documentation and/or other materials -; provided with the distribution. -; * Neither the name of the Regents nor the names of its contributors -; may be used to endorse or promote products derived from this -; software without specific prior written permission. -;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, -;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF -;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT -;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF -;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION -;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR -;MODIFICATIONS. -defpackage firrtl/parser : - import core - import verse - import firrtl/ir2 - import stz/parser - import firrtl/lexer - import bigint2 - import firrtl/ir-utils - import firrtl/chirrtl - -;======= Convenience Types =========== -definterface MStat -defstruct Reader <: MStat : - value: Symbol -defstruct Writer <: MStat : - value: Symbol -defstruct ReadWriter <: MStat : - value: Symbol -defstruct ReadLatency <: MStat : - value: Int -defstruct WriteLatency <: MStat : - value: Int -defstruct DataType <: MStat : - value: Type -defstruct Depth <: MStat : - value: Int -;======= Convenience Functions ======== -defn first-info? (form) -> FileInfo|False : - match(form) : - (form:Token) : info(form) - (form:List) : search(first-info?, form) - (form) : false - -defn first-info (form:List) : - match(first-info?(form)) : - (i:FileInfo) : i - (f:False) : FileInfo() - -defn FPE (form, x) : - throw $ new Exception : - defmethod print (o:OutputStream, this) : - print(o, "[~] FIRRTL Parsing Error: ~" << [first-info(form), x]) - -defn* apply-suffix-ops (x, fs:List) : - if empty?(fs) : x - else : apply-suffix-ops(head(fs)(x), tail(fs)) - -defn parse-stmts (forms:List) : - val cs = Vector<Stmt>() - defn* loop (forms:List) : - match-syntax(forms) : - () : to-list(cs) - (?s:#stmt ?rest ...) : (add(cs, s), loop(rest)) - (?rest ...) : FPE(rest, "Expected a statement here.") - loop(forms) - -;======== Parser Utilities ============== -defn atom? (x) : unwrap-token(x) not-typeof List - -defn primop (x:Symbol) : get?(OPERATORS, x, false) -val OPERATORS = HashTable<Symbol, PrimOp>(symbol-hash) -OPERATORS[`add] = ADD-OP -OPERATORS[`sub] = SUB-OP -OPERATORS[`mul] = MUL-OP -OPERATORS[`div] = DIV-OP -OPERATORS[`rem] = REM-OP -OPERATORS[`lt] = LESS-OP -OPERATORS[`leq] = LESS-EQ-OP -OPERATORS[`gt] = GREATER-OP -OPERATORS[`geq] = GREATER-EQ-OP -OPERATORS[`eq] = EQUAL-OP -OPERATORS[`neq] = NEQUAL-OP -OPERATORS[`pad] = PAD-OP -OPERATORS[`neg] = NEG-OP -OPERATORS[`asUInt] = AS-UINT-OP -OPERATORS[`asSInt] = AS-SINT-OP -OPERATORS[`asClock] = AS-CLOCK-OP -OPERATORS[`shl] = SHIFT-LEFT-OP -OPERATORS[`shr] = SHIFT-RIGHT-OP -OPERATORS[`dshl] = DYN-SHIFT-LEFT-OP -OPERATORS[`dshr] = DYN-SHIFT-RIGHT-OP -OPERATORS[`cvt] = CONVERT-OP -OPERATORS[`neg] = NEG-OP -OPERATORS[`not] = NOT-OP -OPERATORS[`and] = AND-OP -OPERATORS[`or] = OR-OP -OPERATORS[`xor] = XOR-OP -OPERATORS[`andr] = AND-REDUCE-OP -OPERATORS[`orr] = OR-REDUCE-OP -OPERATORS[`xorr] = XOR-REDUCE-OP -OPERATORS[`cat] = CONCAT-OP -OPERATORS[`bits] = BITS-SELECT-OP -OPERATORS[`head] = HEAD-OP -OPERATORS[`tail] = TAIL-OP - -;======== Parser Rules ================== -defsyntax firrtl : - ;Useful Atoms - defrule atoms : - ;Unconditionally parse next form as identifier. - id = (?x) when atom?(x) : - match(unwrap-token(x)) : - (x:Symbol) : x - (x) : FPE(form, "Expected an identifier here. Got ~ instead." << [x]) - - ;Parses next form if integer literal - int = (?x) when unwrap-token(x) typeof Int : - unwrap-token(x) - - string = (?x) when unwrap-token(x) typeof String : - unwrap-token(x) - - ;Parses next form if long literal - intorlong = (?x) when unwrap-token(x) typeof Int|Long : - unwrap-token(x) - - ;Parses next form if symbol - sym = (?x) when unwrap-token(x) typeof Symbol : - unwrap-token(x) - - ;Error Handling Productions - defrule : - ;Error if not an identifier - id! = (?x:#id) : x - id! != () : FPE(form, "Expected an identifier here.") - - ;Error if not => - =>! = (=>) : (`=>) - =>! != () : FPE(form, "Expected => here.") - - ;Error if not a colon - :! = (:) : (`:) - :! != () : FPE(form, "Expected a colon here.") - - ;Error if not 'of' keyword - of! = (of) : `of - of! != () : FPE(form, "Expected the 'of' keyword here.") - - ;Error if not a = - =! = (=) : `= - =! != () : FPE(form, "Expected a '=' here.") - - ;Error if not a single integer - int$ = (?i:#int ?rest ...) when empty?(rest) : i - int$ != () : FPE(form, "Expected a single integer literal here.") - - ;Error if not an integer - int! = (?i:#int) : i - int! != () : FPE(form, "Expected an integer literal here.") - - ;Error if not a single long integer - long$ = (?i:#intorlong ?rest ...) when empty?(rest) : - match(i) : - (i:Long) : i - (i) : to-long(i) - long$ != () : FPE(form, "Expected a single long integer literal here.") - - ;Error if not a single width - width$ = (?w:#width ?rest ...) when empty?(rest) : w - width$ != () : FPE(form, "Expected a single width specifier here.") - - ;Error if not a type - type! = (?t:#type) : t - type! != () : FPE(form, "Expected a type here.") - - ;Error if not a vec type - vectype! = (?t:#type!) : - FPE(form, "Expected a vector type here.") when t not-typeof VectorType - t - - ;Error if not an expression - exp! = (?e:#exp) : e - exp! != () : FPE(form, "Expected an expression here.") - - ;Error if not a single expression - exp$ = (?e:#exp ?rest ...) when empty?(rest) : e - exp$ != () : FPE(form, "Expected a single expression here.") - - ;Error if not a stmt - stmt! = (?s:#stmt) : s - stmt! != () : FPE(form, "Expected a statement here.") - - ;Error if not a reference expression - ref! = (?e:#exp!) : - FPE(form, "Expected a reference expression here.") when e not-typeof Ref - e - - ;Main Circuit Production - defrule circuit : - circuit = (circuit ?name:#id! #:! (?ms:#module ... ?rest ...)) : - if not empty?(rest) : - FPE(rest, "Expected a module declaration here.") - Circuit(first-info(form),ms, name) - circuit != (circuit) : - FPE(form, "Invalid syntax for circuit definition.") - - ;Main Module Production - defrule module : - ;module = (module ?name:#id! #:! (?ps:#port ... ?rest ...)) : - ; InModule(first-info(form), name, ps, Begin(parse-stmts(rest))) - module = (module ?name:#id! #:! (?ps:#port ... ?cs:#stmt ... ?rest ...)) : - if not empty?(rest) : - FPE(rest, "Expected a statement here.") - InModule(first-info(form),name, ps, Begin(cs)) - module = (extmodule ?name:#id! #:! (?ps:#port ... ?rest ...)) : - if not empty?(rest) : - FPE(rest, "Expected a port here.") - ExModule(first-info(form),name, ps) - module != (module) : - FPE(form, "Invalid syntax for module definition.") - module != (exmodule) : - FPE(form, "Invalid syntax for exmodule definition.") - - defrule port : - port = (input ?name:#id! #:! ?type:#type!) : Port(first-info(form),name, INPUT, type) - port = (output ?name:#id! #:! ?type:#type!) : Port(first-info(form),name, OUTPUT, type) - - ;Main Type Productions - defrule type : - inttype = (UInt<?w:#width$>) : UIntType(w) - inttype = (UInt) : UIntType(UnknownWidth()) - inttype = (SInt<?w:#width$>) : SIntType(w) - inttype = (SInt) : SIntType(UnknownWidth()) - - clktype = (Clock) : ClockType() - - type = (?t:#typeterm ?ops:#typeop ...) : apply-suffix-ops(t, ops) - type = (?t:#clktype) : t - typeop = ((@get ?size:#int$)) : (fn (t) : VectorType(t, size)) - - typeterm = (?t:#inttype) : t - typeterm = ({?fs:#field ... ?rest ...}) : - if not empty?(rest) : - FPE(rest, "Expected a bundle field declaration here.") - BundleType(fs) - - defrule field : - field = (flip ?name:#id! #:! ?type:#type!) : Field(name, REVERSE, type) - field = (?name:#id #:! ?type:#type!) : Field(name, DEFAULT, type) - - defrule width : - width = (?x:#int) : IntWidth(x) - width = (?) : UnknownWidth() - - ;Main Statement Productions - defrule mstat : - mstat = (reader #=>! ?name:#id!) : Reader(name) - mstat = (writer #=>! ?name:#id!) : Writer(name) - mstat = (readwriter #=>! ?name:#id!) : ReadWriter(name) - mstat = (read-latency #=>! ?i:#int!) : ReadLatency(i) - mstat = (write-latency #=>! ?i:#int!) : WriteLatency(i) - mstat = (data-type #=>! ?t:#type!) : DataType(t) - mstat = (depth #=>! ?i:#int!) : Depth(i) - defrule statements : - stmt = (skip) : Empty() - stmt = (wire ?name:#id! #:! ?t:#type!) : DefWire(first-info(form),name, t) - stmt = (reg ?name:#id! #:! ?t:#type! ?clk:#exp! with #:! ( reset => (?reset:#exp! ?init:#exp!))) : DefRegister(first-info(form),name,t,clk,reset,init) - stmt = (reg ?name:#id! #:! ?t:#type! ?clk:#exp!) : DefRegister(first-info(form),name,t,clk,zero,Ref(name,UnknownType())) - stmt = (cmem ?name:#id! #:! ?t:#vectype! ) : CDefMemory(first-info(form),name,type(t),size(t),false) - stmt = (smem ?name:#id! #:! ?t:#vectype! ) : CDefMemory(first-info(form),name,type(t),size(t),true) - - stmt = (read mport ?name:#id! #=! ?mem:#id! (@get ?index:#exp!) ?clk:#exp!) : - CDefMPort(first-info(form),name,UnknownType(),mem,list(index,clk),MRead) - stmt = (write mport ?name:#id! #=! ?mem:#id! (@get ?index:#exp!) ?clk:#exp!) : - CDefMPort(first-info(form),name,UnknownType(),mem,list(index,clk),MWrite) - stmt = (rdwr mport ?name:#id! #=! ?mem:#id! (@get ?index:#exp!) ?clk:#exp!) : - CDefMPort(first-info(form),name,UnknownType(),mem,list(index,clk),MReadWrite) - stmt = (infer mport ?name:#id! #=! ?mem:#id! (@get ?index:#exp!) ?clk:#exp!) : - CDefMPort(first-info(form),name,UnknownType(),mem,list(index,clk),MInfer) - - stmt = (mem ?name:#id! #:! (?ms:#mstat ...)) : - defn grab (f:MStat -> True|False) : - map(value,to-list(filter(f,ms))) as List - defn grab1 (f:MStat -> True|False,s:String) : - val ls = grab(f) - if length(ls) != 1 : FPE(form,"Must declare one ~." << [s]) - head(ls) - val readers = grab({_ typeof Reader}) - val writers = grab({_ typeof Writer}) - val readwriters = grab({_ typeof ReadWriter}) - val write-latency = grab1({_ typeof WriteLatency},"write-latency") - val read-latency = grab1({_ typeof ReadLatency},"read-latency") - val depth = grab1({_ typeof Depth},"depth") - val dt = grab1({_ typeof DataType},"data type") - DefMemory(first-info(form),name,dt,depth,write-latency,read-latency,readers,writers,readwriters) - stmt = (inst ?name:#id! #of! ?m:#id!) : DefInstance(first-info(form),name,m) - stmt = (node ?name:#id! #=! ?e:#exp!) : DefNode(first-info(form),name,e) - stmt = (poison ?name:#id! #:! ?t:#type!) : DefPoison(first-info(form),name, t) - stmt = (stop(?clk:#exp, ?en:#exp, ?ret:#int)) : Stop(first-info(form),ret,clk,en) - stmt = (printf(?clk:#exp ?en:#exp ?str:#string ?es:#exp ...)) : Print(first-info(form),str,es,clk,en) - stmt = (?s:#stmt/when) : s - - stmt = (?x:#exp <= ?y:#exp!) : Connect(first-info(form),x, y) ;> - stmt = (?x:#exp <- ?y:#exp!) : BulkConnect(first-info(form),x, y);> - stmt = (?x:#exp is invalid) : IsInvalid(first-info(form),x) - - ;stmt = ((?s:#stmt ?rest ...)) : - ; Begin(List(s, parse-stmts(rest))) - stmt = ((?s:#stmt ?ss:#stmt ... ?rest ...)) : - if not empty?(rest) : - FPE(rest, "Expected a statement here.") - Begin(List(s, ss)) - stmt = (()) : - Begin(List()) - - defrule stmt/when : - stmt/when = (when ?pred:#exp! #:! ?conseq:#stmt! else ?alt:#stmt/when) : - Conditionally(first-info(form),pred, conseq, alt) - stmt/when = (when ?pred:#exp! #:! ?conseq:#stmt! else #:! ?alt:#stmt!) : - Conditionally(first-info(form),pred, conseq, alt) - stmt/when = (when ?pred:#exp! #:! ?conseq:#stmt!) : - Conditionally(first-info(form),pred, conseq, Empty()) - - ;Main Expressions - defrule exp : - ;Suffix Operators - exp = (?x:#expterm ?ops:#expop ...) : apply-suffix-ops(x, ops) - expop = ((@get ?f:#int)) : (fn (x) : SubIndex(x, f, UnknownType())) - expop = ((@get ?f:#exp!)) : (fn (x) : SubAccess(x, f, UnknownType())) - expop = (. ?f:#id!) : (fn (x) : SubField(x, f, UnknownType())) - - ;Prefix Operators - expterm = (?t:#inttype(?v:#string)) : - val b = BigIntLit(v as String) - match(t) : - (t:UIntType) : - match(width(t)) : - (w:IntWidth) : - if to-long(req-num-bits(b)) > width(w) : - FPE(form, "Width too small for UIntValue.") - if width(w) == to-long(0) : println("is zero at") - UIntValue(b, w) - (w) : - ;UIntValue(b, w) - val num-bits = req-num-bits(b) - UIntValue(b,IntWidth(max(1,num-bits))) - (t:SIntType) : - match(width(t)) : - (w:IntWidth) : - if to-long(req-num-bits(b)) > width(w) : - FPE(form, "Width too small for SIntValue.") - SIntValue(b, w) - (w) : - SIntValue(b, w) - - expterm = (?t:#inttype(?v:#int$)) : - match(t) : - (t:UIntType) : - if (v as Int) < 0 : - FPE(form, "UIntValue cannot be negative.") - match(width(t)) : - (w:IntWidth) : - UIntValue(BigIntLit(v as Int,to-int(width(w)) + 1),w) - (w) : - val num-bits = req-num-bits(v as Int) - UIntValue(BigIntLit(v as Int,num-bits), IntWidth(max(1,num-bits - 1))) - (t:SIntType) : - match(width(t)) : - (w:IntWidth) : - SIntValue(BigIntLit(v as Int,to-int(width(w))),w) - (w) : - val num-bits = req-num-bits(v as Int) - SIntValue(BigIntLit(v as Int,num-bits), IntWidth(num-bits)) - - expterm = (mux(?cond:#exp ?tval:#exp ?fval:#exp)) : - Mux(cond,tval,fval,UnknownType()) - expterm = (validif(?cond:#exp ?value:#exp)) : - ValidIf(cond,value,UnknownType()) - expterm = (?op:#sym(?es:#exp ... ?ints:#int ... ?rest ...)) : - if not empty?(rest) : - FPE(rest, "Illegal operands to primitive operator.") - match(primop(op)) : - (p:PrimOp) : DoPrim(p, es, ints, UnknownType()) - (p:False) : FPE(form, "Unrecognized primitive operator '~'." << [op]) - expterm = (?op:#sym) : - Ref(op, UnknownType()) - -public defn parse-firrtl (forms:List) : - with-syntax(firrtl) : - match-syntax(forms) : - (?c:#circuit) : c - (_ ...) : FPE(form, "Invalid firrtl circuit.") - -public defn parse-firrtl-file (filename:String) : - parse-firrtl(lex-file(filename)) diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza deleted file mode 100644 index a96d7503..00000000 --- a/src/main/stanza/ir-utils.stanza +++ /dev/null @@ -1,981 +0,0 @@ -;Copyright (c) 2014 - 2016 The Regents of the University of -;California (Regents). All Rights Reserved. Redistribution and use in -;source and binary forms, with or without modification, are permitted -;provided that the following conditions are met: -; * Redistributions of source code must retain the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer. -; * Redistributions in binary form must reproduce the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer in the documentation and/or other materials -; provided with the distribution. -; * Neither the name of the Regents nor the names of its contributors -; may be used to endorse or promote products derived from this -; software without specific prior written permission. -;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, -;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF -;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT -;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF -;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION -;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR -;MODIFICATIONS. -defpackage firrtl/ir-utils : - import core - import verse - import firrtl/ir2 - import bigint2 - -;============== DEBUG STUFF ============================= - -public defmulti print-debug (o:OutputStream, e:Expression|Stmt|Type|Port|Field|Module|Circuit) -> False -public defmethod print-debug (o:OutputStream, e:Expression|Stmt|Type|Port|Field|Module|Circuit) -> False : false -public defmulti turn-off-debug (x:False) -> False -;public defmethod turn-off-debug (x:False) : false -public defmulti turn-on-debug (x:False) -;public defmethod turn-on-debug (x:False) : false - -;============== GENSYM STUFF ====================== - -defn generated? (s:String) -> False|Int : - for i in 1 to length(s) - 1 find : - val sub = substring(s,i + 1) - s[i] == '_' and digits?(sub) and s[i - 1] != '_' -defn digits? (s:String) -> True|False : - val digits = "0123456789" - var yes = true - for c in s do : - if not contains?(digits,c) : yes = false - yes - -val gen-names = HashTable<Symbol,Int>(symbol-hash) -public defn firrtl-gensym (s:Symbol) -> Symbol : - firrtl-gensym(s,HashTable<Symbol,Int>(symbol-hash)) -public defn firrtl-gensym (sym-hash:HashTable<Symbol,Int>) -> Symbol : - firrtl-gensym(`gen,sym-hash) -public defn firrtl-gensym (s:Symbol,sym-hash:HashTable<Symbol,Int>) -> Symbol : - defn get-name (s:Symbol) -> Symbol : - if key?(sym-hash,s) : - val num = sym-hash[s] + 1 - sym-hash[s] = num - symbol-join([s delin num]) - else : - sym-hash[s] = 0 - symbol-join([s delin 0]) - val s* = to-string(s) - val i* = generated?(s*) - val nex = match(i*) : - (i:False) : get-name(s) - (i:Int) : get-name(to-symbol(substring(s*,0,i))) - nex - -public defn get-sym-hash (m:InModule) -> HashTable<Symbol,Int> : - get-sym-hash(m,list()) -public defn get-sym-hash (m:InModule,keywords:Streamable<Symbol>) -> HashTable<Symbol,Int> : - val sym-hash = HashTable<Symbol,Int>(symbol-hash) - for k in keywords do : - sym-hash[k] = 0 - defn add-name (s:Symbol) -> Symbol : - val s* = to-string(s) - val i* = generated?(s*) - match(i*) : - (i:False) : - if key?(sym-hash,s) : - val num = sym-hash[s] - sym-hash[s] = max(num,0) - else : - sym-hash[s] = 0 - (i:Int) : - val name = to-symbol(substring(s*,0,i)) - val digit = to-int(substring(s*,i + 1)) - if key?(sym-hash,name) : - val num = sym-hash[name] - sym-hash[name] = max(num,digit) - else : - sym-hash[name] = digit - s - - defn to-port (p:Port) : add-name(name(p)) - defn to-stmt (s:Stmt) -> Stmt : - map{to-stmt,_} $ map(add-name,s) - - to-stmt(body(m)) - map(to-port,ports(m)) - sym-hash - -; ======== Expression Computation Library =========== - -public defn BoolType () : UIntType(IntWidth(1)) -public val zero = UIntValue(BigIntLit(0),IntWidth(1)) -public val one = UIntValue(BigIntLit(1),IntWidth(1)) -public defn uint (i:Int) -> UIntValue : - val num-bits = req-num-bits(i) - val w = IntWidth(max(1,num-bits - 1)) - UIntValue(BigIntLit(i),w) -public defn sint (i:Int) -> SIntValue : - val num-bits = req-num-bits(i) - val w = IntWidth(max(1,num-bits)) - SIntValue(BigIntLit(i),w) - -public defn AND (e1:Expression,e2:Expression) -> Expression : - if e1 == e2 : e1 - else if e1 == zero or e2 == zero : zero - else if e1 == one : e2 - else if e2 == one : e1 - else : DoPrim(AND-OP,list(e1,e2),list(),UIntType(IntWidth(1))) - -public defn OR (e1:Expression,e2:Expression) -> Expression : - if e1 == e2 : e1 - else if e1 == one or e2 == one : one - else if e1 == zero : e2 - else if e2 == zero : e1 - else : DoPrim(OR-OP,list(e1,e2),list(),UIntType(IntWidth(1))) - -public defn EQV (e1:Expression,e2:Expression) -> Expression : - DoPrim(EQUAL-OP,list(e1,e2),list(),type(e1)) - -public defn MUX (p:Expression,e1:Expression,e2:Expression) -> Expression : - Mux(p,e1,e2,mux-type(type(e1),type(e2))) - -public defn mux-type (e1:Expression,e2:Expression) -> Type : - mux-type(type(e1),type(e2)) -public defn mux-type (t1:Type,t2:Type) -> Type : - if t1 == t2 : - match(t1,t2) : - (t1:UIntType,t2:UIntType) : UIntType(UnknownWidth()) - (t1:SIntType,t2:SIntType) : SIntType(UnknownWidth()) - (t1:VectorType,t2:VectorType) : VectorType(mux-type(type(t1),type(t2)),size(t1)) - (t1:BundleType,t2:BundleType) : - BundleType $ for (f1 in fields(t1),f2 in fields(t2)) map : - Field(name(f1),flip(f1),mux-type(type(f1),type(f2))) - else : UnknownType() - -public defn CAT (e1:Expression,e2:Expression) -> Expression : - DoPrim(CONCAT-OP,list(e1,e2),list(),type(e1)) - -public defn NOT (e1:Expression) -> Expression : - if e1 == one : zero - else if e1 == zero : one - else : DoPrim(EQUAL-OP,list(e1,zero),list(),UIntType(IntWidth(1))) - -public defn children (e:Expression) -> List<Expression> : - val es = Vector<Expression>() - defn f (e:Expression) : - add(es,e) - e - map(f,e) - to-list(es) - -public var mname : Symbol = `blah -public defn exp-hash (e:Expression) -> Int : - turn-off-debug(false) - ;val i = symbol-hash(to-symbol(string-join(map(to-string,list(mname `.... e))))) - val i = symbol-hash(to-symbol(to-string(e))) - turn-on-debug(false) - i - -public defn type-hash (t:Type) -> Int : - symbol-hash(to-symbol(to-string(t))) - -public defn list-hash (l:List) -> Int : - turn-off-debug(false) - val i = symbol-hash(to-symbol(string-join(map(to-string,l)))) - turn-on-debug(false) - i - -;===== Type Expansion Algorithms ========= -public defn times (f1:Flip,f2:Flip) -> Flip : - switch {_ == f2} : - DEFAULT : f1 - REVERSE : swap(f1) -public defn swap (f:Flip) -> Flip : - switch {_ == f} : - DEFAULT : REVERSE - REVERSE : DEFAULT - -public defmulti get-type (s:Stmt) -> Type -public defmethod get-type (s:Stmt) -> Type : - match(s) : - (s:DefWire|DefPoison|DefRegister) : type(s) - (s:DefNode) : type(value(s)) - (s:DefMemory) : - val depth = depth(s) - ; Fields - val addr = Field(`addr,DEFAULT,UIntType(IntWidth(ceil-log2(depth)))) - val en = Field(`en,DEFAULT,BoolType()) - val clk = Field(`clk,DEFAULT,ClockType()) - val def-data = Field(`data,DEFAULT,data-type(s)) - val rev-data = Field(`data,REVERSE,data-type(s)) - val mask = Field(`mask,DEFAULT,create-mask(data-type(s))) - val wmode = Field(`wmode,DEFAULT,UIntType(IntWidth(1))) - val rdata = Field(`rdata,REVERSE,data-type(s)) - - val read-type = BundleType(to-list([rev-data,addr,en,clk])) - val write-type = BundleType(to-list([def-data,mask,addr,en,clk])) - val readwrite-type = BundleType(to-list([wmode,rdata,def-data,mask,addr,en,clk])) - - val mem-fields = Vector<Field>() - for x in readers(s) do : - add(mem-fields,Field(x,REVERSE,read-type)) - for x in writers(s) do : - add(mem-fields,Field(x,REVERSE,write-type)) - for x in readwriters(s) do : - add(mem-fields,Field(x,REVERSE,readwrite-type)) - BundleType(to-list(mem-fields)) - (s:DefInstance) : UnknownType() - (s:Begin|Connect|BulkConnect|Stop|Print|Empty|IsInvalid) : UnknownType() - -public defn get-size (t:Type) -> Int : - val x = match(t) : - (t:BundleType) : - var sum = 0 - for f in fields(t) do : - sum = sum + get-size(type(f)) - sum - (t:VectorType) : size(t) * get-size(type(t)) - (t) : 1 - x -public defn get-valid-points (t1:Type,t2:Type,flip1:Flip,flip2:Flip) -> List<[Int,Int]> : - ;println-all(["Inside with t1:" t1 ",t2:" t2 ",f1:" flip1 ",f2:" flip2]) - match(t1,t2) : - (t1:UIntType,t2:UIntType) : - if flip1 == flip2 : list([0, 0]) - else: list() - (t1:SIntType,t2:SIntType) : - if flip1 == flip2 : list([0, 0]) - else: list() - (t1:BundleType,t2:BundleType) : - val points = Vector<[Int,Int]>() - var ilen = 0 - var jlen = 0 - for i in 0 to length(fields(t1)) do : - for j in 0 to length(fields(t2)) do : - ;println(i) - ;println(j) - ;println(ilen) - ;println(jlen) - val f1 = fields(t1)[i] - val f2 = fields(t2)[j] - if name(f1) == name(f2) : - val ls = get-valid-points(type(f1),type(f2),flip1 * flip(f1), - flip2 * flip(f2)) - for x in ls do : - add(points,[x[0] + ilen, x[1] + jlen]) - ;println(points) - jlen = jlen + get-size(type(fields(t2)[j])) - ilen = ilen + get-size(type(fields(t1)[i])) - jlen = 0 - to-list(points) - (t1:VectorType,t2:VectorType) : - val points = Vector<[Int,Int]>() - var ilen = 0 - var jlen = 0 - for i in 0 to min(size(t1),size(t2)) do : - val ls = get-valid-points(type(t1),type(t2),flip1,flip2) - for x in ls do : - add(points,[x[0] + ilen, x[1] + jlen]) - ilen = ilen + get-size(type(t1)) - jlen = jlen + get-size(type(t2)) - to-list(points) - -;============= Useful functions ============== -public defn create-mask (dt:Type) -> Type : - match(dt) : - (t:VectorType) : VectorType(create-mask(type(t)),size(t)) - (t:BundleType) : - val fields* = for f in fields(t) map : - Field(name(f),flip(f),create-mask(type(f))) - BundleType(fields*) - (t:UIntType|SIntType) : BoolType() - -;============== Exceptions ===================== - -public definterface PassException <: Exception -public defn PassException (s:String) : - new PassException : - defmethod print (o:OutputStream, this) : - print(o, s) - -public defn PassExceptions (xs:Streamable<PassException>) : - PassException(string-join(xs, "\n")) - -;============== Pass/Compiler Structs ============ - -public definterface Compiler -public defmulti passes (c:Compiler) -> List<Pass> -public defmulti backend (c:Compiler) -> List<Pass> -defmethod passes (c:Compiler) : List<Pass>() -public defmulti with-output (c:Compiler) -> ((() -> False) -> False) -defmethod with-output (c:Compiler) : 1 as ? - -public definterface Pass -public defmulti pass (p:Pass) -> (Circuit -> Circuit) -public defmethod pass (p:Pass) : fn (c:Circuit) : c -public defmulti name (p:Pass) -> String -public defmethod name (p:Pass) -> String : "--" -public defmulti short-name (p:Pass) -> String -public defmethod short-name (p:Pass) -> String : "--" -public defmethod print (o:OutputStream, p:Pass) : - print(o,name(p)) - -;============== Various Useful Functions ============== - -public defn add-all (v1:Vector,v2:Vector) -> False : - for x in v2 do : - add(v1,x) - - -public defn ceil-log2 (i:Long) -> Long : - defn* loop (n:Long, l:Long) : - if n < i : - if l == 30 : to-long(31) - else : loop(n * to-long(2), l + to-long(1)) - else : l - error("Log of negative number!") when i < to-long(0) - loop(to-long $ 1, to-long $ 0) - - -public defn abs (x:Long) -> Long : - if x < to-long(0) : to-long(0) - x - else : x - -public defn max (x:Long,y:Long) -> Long : - if x < y : y - else : x - - -defn escape (s:String) -> String : - val s* = Vector<String>() - add(s*,"\"");" - for c in s do : - if c == '\n' : - add(s*,"\\n") - else : add(s*,to-string(c)) - add(s*,"\"");" - string-join(s*) - ;" - -;============== PRINTERS =================================== - -defmethod print (o:OutputStream, d:Flip) : - print{o, _} $ - switch {d == _} : - DEFAULT : "" - REVERSE: "flip" - -defmethod print (o:OutputStream, d:Direction) : - print{o, _} $ - switch {d == _} : - INPUT : "input" - OUTPUT: "output" - -defmethod print (o:OutputStream, w:Width) : - print{o, _} $ - match(w) : - (w:UnknownWidth) : "?" - (w:IntWidth) : width(w) - -defmethod print (o:OutputStream, op:PrimOp) : - print{o, _} $ - switch {op == _} : - ADD-OP : "add" - SUB-OP : "sub" - MUL-OP : "mul" - DIV-OP : "div" - REM-OP : "rem" - LESS-OP : "lt" - LESS-EQ-OP : "leq" - GREATER-OP : "gt" - GREATER-EQ-OP : "geq" - EQUAL-OP : "eq" - NEQUAL-OP : "neq" - PAD-OP : "pad" - AS-UINT-OP : "asUInt" - AS-SINT-OP : "asSInt" - AS-CLOCK-OP : "asClock" - SHIFT-LEFT-OP : "shl" - SHIFT-RIGHT-OP : "shr" - DYN-SHIFT-LEFT-OP : "dshl" - DYN-SHIFT-RIGHT-OP : "dshr" - CONVERT-OP : "cvt" - NEG-OP : "neg" - NOT-OP : "not" - AND-OP : "and" - OR-OP : "or" - XOR-OP : "xor" - AND-REDUCE-OP : "andr" - OR-REDUCE-OP : "orr" - XOR-REDUCE-OP : "xorr" - CONCAT-OP : "cat" - BITS-SELECT-OP : "bits" - HEAD-OP : "head" - TAIL-OP : "tail" - -defmethod print (o:OutputStream, e:Expression) : - match(e) : - (e:Ref) : print(o, name(e)) - (e:SubField) : print-all(o, [exp(e) "." name(e)]) - (e:SubIndex) : print-all(o, [exp(e) "[" value(e) "]"]) - (e:SubAccess) : print-all(o, [exp(e) "[" index(e) "]"]) - (e:UIntValue) : - print-all(o, ["UInt<" width(e) ">(" value(e) ")"]) - (e:SIntValue) : print-all(o, ["SInt<" width(e) ">(" value(e) ")"]) - (e:DoPrim) : - print-all(o, [op(e) "("]) - print-all(o, join(concat(args(e), consts(e)), ", ")) - print(o, ")") - (e:Mux) : - print-all(o, ["mux(" cond(e) ", " tval(e) ", " fval(e) ")"]) - (e:ValidIf) : - print-all(o, ["validif(" cond(e) ", " value(e) ")"]) - print-debug(o,e) - -defmethod print (o:OutputStream, c:Stmt) : - val io = IndentedStream(o, 3) - match(c) : - (c:DefPoison) : - print-all(o,["poison " name(c) " : " type(c)]) - (c:DefWire) : - print-all(o,["wire " name(c) " : " type(c)]) - (c:DefRegister) : - print-all(o,["reg " name(c) " : " type(c) ", " clock(c) " with :"]) - print-all(io,["\nreset => (" reset(c) ", " init(c) ")"]) - (c:DefMemory) : - print-all(o,["mem " name(c) " : "]) - print-debug(o,c) - print-all(io,["\ndata-type => " data-type(c)]) - print-all(io,["\ndepth => " depth(c)]) - print-all(io,["\nwrite-latency => " write-latency(c)]) - print-all(io,["\nread-latency => " read-latency(c)]) - for r in readers(c) do : print-all(io,["\nreader => " r]) - for w in writers(c) do : print-all(io,["\nwriter => " w]) - for rw in readwriters(c) do : print-all(io,["\nreadwriter => " rw]) - (c:DefInstance) : - print-all(o,["inst " name(c) " of " module(c)]) - (c:DefNode) : - print-all(o,["node " name(c) " = " value(c)]) - (c:Conditionally) : - if conseq(c) typeof Begin : - print-all(o, ["when " pred(c) " :"]) - print-debug(o,c) - print(o,"\n") - print(io,conseq(c)) - else : - print-all(o, ["when " pred(c) " : " conseq(c)]) - print-debug(o,c) - if alt(c) not-typeof Empty: - print(o, "\nelse :") - print(io, "\n") - print(io,alt(c)) - (c:Begin) : - do(print{o,_}, join(body(c), "\n")) - (c:Connect) : - print-all(o, [loc(c) " <= " exp(c)]) - (c:IsInvalid) : - print-all(o, [exp(c) " is invalid"]) - (c:BulkConnect) : - print-all(o, [loc(c) " <- " exp(c)]) - (c:Empty) : - print(o, "skip") - (c:Stop) : - print-all(o, ["stop(" clk(c) ", " en(c) ", " ret(c) ")"]) - (c:Print) : - print-all(o, ["printf(" clk(c) ", " en(c) ", "]) ;" - print-all(o, join(List(escape(string(c)),args(c)), ", ")) - print(o, ")") - - if not c typeof Conditionally|Begin|Empty: print-debug(o,c) - -defmethod print (o:OutputStream, t:Type) : - match(t) : - (t:UnknownType) : - print(o, "?") - (t:ClockType) : - print(o, "Clock") - (t:UIntType) : - match(width(t)) : - (w:IntWidth) : print-all(o, ["UInt<" width(t) ">"]) - (w) : print-all(o, ["UInt"]) - (t:SIntType) : - match(width(t)) : - (w:IntWidth) : print-all(o, ["SInt<" width(t) ">"]) - (w) : print-all(o, ["SInt"]) - (t:BundleType) : - print(o, "{") - print-all(o, join(fields(t), ", ")) - print(o, "}") - (t:VectorType) : - print-all(o, [type(t) "[" size(t) "]"]) - print-debug(o,t) - -defmethod print (o:OutputStream, f:Field) : - print-all(o, [flip(f) " " name(f) " : " type(f)]) - print-debug(o,f) - -defmethod print (o:OutputStream, p:Port) : - print-all(o, [direction(p) " " name(p) " : " type(p)]) - print-debug(o,p) - -defmethod print (o:OutputStream, m:InModule) : - print-all(o, ["module " name(m) " :"]) - print-debug(o,m) - print(o,"\n") - val io = IndentedStream(o, 3) - for p in ports(m) do : - println(io,p) - print(io,body(m)) - -defmethod print (o:OutputStream, m:ExModule) : - print-all(o, ["extmodule " name(m) " :"]) - print-debug(o,m) - print(o,"\n") - val io = IndentedStream(o, 3) - for p in ports(m) do : - println(io,p) - -defmethod print (o:OutputStream, c:Circuit) : - print-all(o, ["circuit " main(c) " :"]) - print-debug(o,c) - print(o,"\n") - val io = IndentedStream(o, 3) - for m in modules(c) do : - println(io, m) - -;=================== MAPPERS =============================== -public defn map<?T> (f: Type -> Type, t:?T&Type) -> T : - val type = - match(t) : - (t:T&BundleType) : - BundleType $ - for p in fields(t) map : - Field(name(p), flip(p), f(type(p))) - (t:T&VectorType) : - VectorType(f(type(t)), size(t)) - (t) : - t - type as T&Type - -public defmulti map<?T> (f: Expression -> Expression, e:?T&Expression) -> T -defmethod map (f: Expression -> Expression, e:Expression) -> Expression : - match(e) : - (e:SubField) : SubField(f(exp(e)), name(e), type(e)) - (e:SubIndex) : SubIndex(f(exp(e)), value(e), type(e)) - (e:SubAccess) : SubAccess(f(exp(e)), f(index(e)), type(e)) - (e:DoPrim) : DoPrim(op(e), map(f, args(e)), consts(e), type(e)) - (e:Mux) : Mux(f(cond(e)),f(tval(e)),f(fval(e)),type(e)) - (e:ValidIf) : ValidIf(f(cond(e)),f(value(e)),type(e)) - (e) : e - -public defmulti map<?T> (f: Symbol -> Symbol, c:?T&Stmt) -> T -defmethod map (f: Symbol -> Symbol, c:Stmt) -> Stmt : - match(c) : - (c:DefWire) : DefWire(info(c),f(name(c)),type(c)) - (c:DefPoison) : DefPoison(info(c),f(name(c)),type(c)) - (c:DefRegister) : DefRegister(info(c),f(name(c)), type(c), clock(c), reset(c), init(c)) - (c:DefMemory) : DefMemory(info(c),f(name(c)), data-type(c), depth(c), write-latency(c), read-latency(c), readers(c), writers(c), readwriters(c)) - (c:DefNode) : DefNode(info(c),f(name(c)),value(c)) - (c:DefInstance) : DefInstance(info(c),f(name(c)), module(c)) - (c) : c - -public defmulti map<?T> (f: Expression -> Expression, c:?T&Stmt) -> T -defmethod map (f: Expression -> Expression, c:Stmt) -> Stmt : - match(c) : - (c:DefRegister) : DefRegister(info(c),name(c), type(c), f(clock(c)), f(reset(c)), f(init(c))) - (c:DefNode) : DefNode(info(c),name(c), f(value(c))) - ;(c:DefInstance) : DefInstance(info(c),name(c), f(module(c))) - (c:Conditionally) : Conditionally(info(c),f(pred(c)), conseq(c), alt(c)) - (c:Connect) : Connect(info(c),f(loc(c)), f(exp(c))) - (c:BulkConnect) : BulkConnect(info(c),f(loc(c)), f(exp(c))) - (c:IsInvalid) : IsInvalid(info(c),f(exp(c))) - (c:Stop) : Stop(info(c),ret(c),f(clk(c)),f(en(c))) - (c:Print) : Print(info(c),string(c),map(f,args(c)),f(clk(c)),f(en(c))) - (c) : c - -public defmulti map<?T> (f: Stmt -> Stmt, c:?T&Stmt) -> T -defmethod map (f: Stmt -> Stmt, c:Stmt) -> Stmt : - match(c) : - (c:Conditionally) : Conditionally(info(c),pred(c), f(conseq(c)), f(alt(c))) - (c:Begin) : Begin(map(f, body(c))) - (c) : c - -public defmulti map<?T> (f: Width -> Width, c:?T&Expression) -> T -defmethod map (f: Width -> Width, c:Expression) -> Expression : - match(c) : - (c:UIntValue) : UIntValue(value(c),f(width(c))) - (c:SIntValue) : SIntValue(value(c),f(width(c))) - (c) : c - -public defmulti map<?T> (f: Width -> Width, c:?T&Type) -> T -defmethod map (f: Width -> Width, c:Type) -> Type : - match(c) : - (c:UIntType) : UIntType(f(width(c))) - (c:SIntType) : SIntType(f(width(c))) - (c) : c - -public defmulti map<?T> (f: Type -> Type, c:?T&Expression) -> T -defmethod map (f: Type -> Type, c:Expression) -> Expression : - match(c) : - (c:Ref) : Ref(name(c),f(type(c))) - (c:SubField) : SubField(exp(c),name(c),f(type(c))) - (c:SubIndex) : SubIndex(exp(c),value(c),f(type(c))) - (c:SubAccess) : SubAccess(exp(c),index(c),f(type(c))) - (c:DoPrim) : DoPrim(op(c),args(c),consts(c),f(type(c))) - (c:Mux) : Mux(cond(c),tval(c),fval(c),f(type(c))) - (c:ValidIf) : ValidIf(cond(c),value(c),f(type(c))) - (c) : c - -public defmulti map<?T> (f: Type -> Type, c:?T&Stmt) -> T -defmethod map (f: Type -> Type, c:Stmt) -> Stmt : - match(c) : - (c:DefPoison) : DefPoison(info(c),name(c),f(type(c))) - (c:DefWire) : DefWire(info(c),name(c),f(type(c))) - (c:DefRegister) : DefRegister(info(c),name(c),f(type(c)),clock(c),reset(c),init(c)) - (c:DefMemory) : DefMemory(info(c),name(c), f(data-type(c)), depth(c), write-latency(c), read-latency(c), readers(c), writers(c), readwriters(c)) - (c) : c - -public defmulti mapr<?T> (f: Width -> Width, t:?T&Type) -> T -defmethod mapr (f: Width -> Width, t:Type) -> Type : - defn apply-t (t:Type) -> Type : - map{f,_} $ map(apply-t,t) - apply-t(t) - -public defmulti mapr<?T> (f: Width -> Width, s:?T&Stmt) -> T -defmethod mapr (f: Width -> Width, s:Stmt) -> Stmt : - defn apply-t (t:Type) -> Type : mapr(f,t) - defn apply-e (e:Expression) -> Expression : - map{f,_} $ map{apply-t,_} $ map(apply-e,e) - defn apply-s (s:Stmt) -> Stmt : - map{apply-t,_} $ map{apply-e,_} $ map(apply-s,s) - apply-s(s) - - -;================= HELPER FUNCTIONS USING MAP =================== -public defmulti do (f:Expression -> ?, e:Expression) -> False -defmethod do (f:Expression -> ?, e:Expression) -> False : - defn f* (x:Expression) : - f(x) - x - map(f*,e) - false - -public defmulti do (f:Expression -> ?, s:Stmt) -> False -defmethod do (f:Expression -> ?, s:Stmt) -> False : - defn f* (x:Expression) : - f(x) - x - map(f*,s) - false - -public defmulti do (f:Stmt -> ?, s:Stmt) -> False -defmethod do (f:Stmt -> ?, s:Stmt) -> False : - defn f* (x:Stmt) : - f(x) - x - map(f*,s) - false - -; Not well defined - usually use dor on fields of a recursive type -;public defmulti dor (f:Expression -> ?, e:Expression) -> False -;defmethod dor (f:Expression -> ?, e:Expression) -> False : -; f(e) -; for x in e map : -; dor(f,x) -; x -; false -; -;public defmulti dor (f:Expression -> ?, s:Stmt) -> False -;defmethod dor (f:Expression -> ?, s:Stmt) -> False : -; defn f* (x:Expression) : -; dor(f,x) -; x -; map(f*,s) -; false -; -;public defmulti dor (f:Stmt -> ?, s:Stmt) -> False -;defmethod dor (f:Stmt -> ?, s:Stmt) -> False : -; f(s) -; defn f* (x:Stmt) : -; dor(f,x) -; x -; map(f*,s) -; false -; -;public defmulti sub-exps (s:Expression|Stmt) -> List<Expression> -;defmethod sub-exps (e:Expression) -> List<Expression> : -; val l = Vector<Expression>() -; defn f (x:Expression) : add(l,x) -; do(f,e) -; to-list(l) -;defmethod sub-exps (e:Stmt) -> List<Expression> : -; val l = Vector<Expression>() -; defn f (x:Expression) : add(l,x) -; do(f,e) -; to-list(l) -; -;public defmulti sub-stmts (s:Stmt) -> List<Stmt> -;defmethod sub-stmts (s:Stmt) : -; val l = Vector<Stmt>() -; defn f (x:Stmt) : add(l,x) -; do(f,s) -; to-list(l) - -;=================== ADAM OPS =============================== -public defn split (s:String,c:Char) -> List<String> : - if not contains(to-list(s),c) : list(s) - else : - val index = label<Int> ret : - var i = 0 - for c* in to-list(s) do : - if c* == c : ret(i) - else : - i = i + 1 - ret(0) - val h = substring(s,0,index) - val t = substring(s,index + 1,length(s)) - List(h,split(t,c)) - -public defn contains (l:List<Char>, c:Char) : - label<True|False> myret : - for x in l do : - if x == c : myret(true) - false - -public defn merge!<?K,?V> (a:HashTable<?K,?V>, b:HashTable<K,V>) : - for e in b do : - a[key(e)] = value(e) - - - -;=================== VERILOG KEYWORDS ======================= - -public val v-keywords = HashTable<Symbol,True>(symbol-hash) -v-keywords[`alias] = true -v-keywords[`always] = true -v-keywords[`always_comb] = true -v-keywords[`always_ff] = true -v-keywords[`always_latch] = true -v-keywords[`and] = true -v-keywords[`assert] = true -v-keywords[`assign] = true -v-keywords[`assume] = true -v-keywords[`attribute] = true -v-keywords[`automatic] = true -v-keywords[`before] = true -v-keywords[`begin] = true -v-keywords[`bind] = true -v-keywords[`bins] = true -v-keywords[`binsof] = true -v-keywords[`bit] = true -v-keywords[`break] = true -v-keywords[`buf] = true -v-keywords[`bufif0] = true -v-keywords[`bufif1] = true -v-keywords[`byte] = true -v-keywords[`case] = true -v-keywords[`casex] = true -v-keywords[`casez] = true -v-keywords[`cell] = true -v-keywords[`chandle] = true -v-keywords[`class] = true -v-keywords[`clocking] = true -v-keywords[`cmos] = true -v-keywords[`config] = true -v-keywords[`const] = true -v-keywords[`constraint] = true -v-keywords[`context] = true -v-keywords[`continue] = true -v-keywords[`cover] = true -v-keywords[`covergroup] = true -v-keywords[`coverpoint] = true -v-keywords[`cross] = true -v-keywords[`deassign] = true -v-keywords[`default] = true -v-keywords[`defparam] = true -v-keywords[`design] = true -v-keywords[`disable] = true -v-keywords[`dist] = true -v-keywords[`do] = true -v-keywords[`edge] = true -v-keywords[`else] = true -v-keywords[`end] = true -v-keywords[`endattribute] = true -v-keywords[`endcase] = true -v-keywords[`endclass] = true -v-keywords[`endclocking] = true -v-keywords[`endconfig] = true -v-keywords[`endfunction] = true -v-keywords[`endgenerate] = true -v-keywords[`endgroup] = true -v-keywords[`endinterface] = true -v-keywords[`endmodule] = true -v-keywords[`endpackage] = true -v-keywords[`endprimitive] = true -v-keywords[`endprogram] = true -v-keywords[`endproperty] = true -v-keywords[`endspecify] = true -v-keywords[`endsequence] = true -v-keywords[`endtable] = true -v-keywords[`endtask] = true -v-keywords[`enum] = true -v-keywords[`event] = true -v-keywords[`expect] = true -v-keywords[`export] = true -v-keywords[`extends] = true -v-keywords[`extern] = true -v-keywords[`final] = true -v-keywords[`first_match] = true -v-keywords[`for] = true -v-keywords[`force] = true -v-keywords[`foreach] = true -v-keywords[`forever] = true -v-keywords[`fork] = true -v-keywords[`forkjoin] = true -v-keywords[`function] = true -v-keywords[`generate] = true -v-keywords[`genvar] = true -v-keywords[`highz0] = true -v-keywords[`highz1] = true -v-keywords[`if] = true -v-keywords[`iff] = true -v-keywords[`ifnone] = true -v-keywords[`ignore_bins] = true -v-keywords[`illegal_bins] = true -v-keywords[`import] = true -v-keywords[`incdir] = true -v-keywords[`include] = true -v-keywords[`initial] = true -v-keywords[`initvar] = true -v-keywords[`inout] = true -v-keywords[`input] = true -v-keywords[`inside] = true -v-keywords[`instance] = true -v-keywords[`int] = true -v-keywords[`integer] = true -v-keywords[`interconnect] = true -v-keywords[`interface] = true -v-keywords[`intersect] = true -v-keywords[`join] = true -v-keywords[`join_any] = true -v-keywords[`join_none] = true -v-keywords[`large] = true -v-keywords[`liblist] = true -v-keywords[`library] = true -v-keywords[`local] = true -v-keywords[`localparam] = true -v-keywords[`logic] = true -v-keywords[`longint] = true -v-keywords[`macromodule] = true -v-keywords[`matches] = true -v-keywords[`medium] = true -v-keywords[`modport] = true -v-keywords[`module] = true -v-keywords[`nand] = true -v-keywords[`negedge] = true -v-keywords[`new] = true -v-keywords[`nmos] = true -v-keywords[`nor] = true -v-keywords[`noshowcancelled] = true -v-keywords[`not] = true -v-keywords[`notif0] = true -v-keywords[`notif1] = true -v-keywords[`null] = true -v-keywords[`or] = true -v-keywords[`output] = true -v-keywords[`package] = true -v-keywords[`packed] = true -v-keywords[`parameter] = true -v-keywords[`pmos] = true -v-keywords[`posedge] = true -v-keywords[`primitive] = true -v-keywords[`priority] = true -v-keywords[`program] = true -v-keywords[`property] = true -v-keywords[`protected] = true -v-keywords[`pull0] = true -v-keywords[`pull1] = true -v-keywords[`pulldown] = true -v-keywords[`pullup] = true -v-keywords[`pulsestyle_onevent] = true -v-keywords[`pulsestyle_ondetect] = true -v-keywords[`pure] = true -v-keywords[`rand] = true -v-keywords[`randc] = true -v-keywords[`randcase] = true -v-keywords[`randsequence] = true -v-keywords[`rcmos] = true -v-keywords[`real] = true -v-keywords[`realtime] = true -v-keywords[`ref] = true -v-keywords[`reg] = true -v-keywords[`release] = true -v-keywords[`repeat] = true -v-keywords[`return] = true -v-keywords[`rnmos] = true -v-keywords[`rpmos] = true -v-keywords[`rtran] = true -v-keywords[`rtranif0] = true -v-keywords[`rtranif1] = true -v-keywords[`scalared] = true -v-keywords[`sequence] = true -v-keywords[`shortint] = true -v-keywords[`shortreal] = true -v-keywords[`showcancelled] = true -v-keywords[`signed] = true -v-keywords[`small] = true -v-keywords[`solve] = true -v-keywords[`specify] = true -v-keywords[`specparam] = true -v-keywords[`static] = true -v-keywords[`strength] = true -v-keywords[`string] = true -v-keywords[`strong0] = true -v-keywords[`strong1] = true -v-keywords[`struct] = true -v-keywords[`super] = true -v-keywords[`supply0] = true -v-keywords[`supply1] = true -v-keywords[`table] = true -v-keywords[`tagged] = true -v-keywords[`task] = true -v-keywords[`this] = true -v-keywords[`throughout] = true -v-keywords[`time] = true -v-keywords[`timeprecision] = true -v-keywords[`timeunit] = true -v-keywords[`tran] = true -v-keywords[`tranif0] = true -v-keywords[`tranif1] = true -v-keywords[`tri] = true -v-keywords[`tri0] = true -v-keywords[`tri1] = true -v-keywords[`triand] = true -v-keywords[`trior] = true -v-keywords[`trireg] = true -v-keywords[`type] = true -v-keywords[`typedef] = true -v-keywords[`union] = true -v-keywords[`unique] = true -v-keywords[`unsigned] = true -v-keywords[`use] = true -v-keywords[`var] = true -v-keywords[`vectored] = true -v-keywords[`virtual] = true -v-keywords[`void] = true -v-keywords[`wait] = true -v-keywords[`wait_order] = true -v-keywords[`wand] = true -v-keywords[`weak0] = true -v-keywords[`weak1] = true -v-keywords[`while] = true -v-keywords[`wildcard] = true -v-keywords[`wire] = true -v-keywords[`with] = true -v-keywords[`within] = true -v-keywords[`wor] = true -v-keywords[`xnor] = true -v-keywords[`xor] = true -v-keywords[`SYNTHESIS] = true -v-keywords[`PRINTF_COND] = true -v-keywords[`VCS] = true diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza deleted file mode 100644 index e9abaf74..00000000 --- a/src/main/stanza/passes.stanza +++ /dev/null @@ -1,2930 +0,0 @@ -;Copyright (c) 2014 - 2016 The Regents of the University of -;California (Regents). All Rights Reserved. Redistribution and use in -;source and binary forms, with or without modification, are permitted -;provided that the following conditions are met: -; * Redistributions of source code must retain the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer. -; * Redistributions in binary form must reproduce the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer in the documentation and/or other materials -; provided with the distribution. -; * Neither the name of the Regents nor the names of its contributors -; may be used to endorse or promote products derived from this -; software without specific prior written permission. -;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, -;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF -;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT -;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF -;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION -;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR -;MODIFICATIONS. -defpackage firrtl/passes : - import core - import verse - import firrtl/ir2 - import firrtl/ir-utils - import firrtl/primops - import firrtl-main - import firrtl/errors - import bigint2 - -;============== Pass List ================ -public val standard-passes = to-list $ [ - CheckHighForm() - ToWorkingIR() - Resolve() - ResolveKinds() - InferTypes() - CheckTypes() - ResolveGenders() - CheckGenders() - InferWidths() - CheckWidths() - PullMuxes() - ExpandConnects() - RemoveAccesses() - ExpandWhens() - LowerTypes() - CheckInitialization() - ConstProp() - VerilogWrap() - SplitExp() - VerilogRename() - Resolve() -] -;=============== WORKING IR ================================ -public definterface Kind -public defstruct WireKind <: Kind -public defstruct PoisonKind <: Kind -public defstruct RegKind <: Kind -public defstruct InstanceKind <: Kind -public defstruct PortKind <: Kind -public defstruct NodeKind <: Kind -public defstruct MemKind <: Kind : - ports : List<Symbol> -public defstruct ExpKind <: Kind - -public definterface Gender -public val MALE = new Gender -public val FEMALE = new Gender -public val UNKNOWN-GENDER = new Gender -public val BI-GENDER = new Gender - -public defstruct WRef <: Expression : - name: Symbol - type: Type with: (as-method => true) - kind: Kind with: (as-method => true) - gender: Gender with: (as-method => true) -public defstruct WSubField <: Expression : - exp: Expression - name: Symbol - type: Type with: (as-method => true) - gender: Gender with: (as-method => true) -public defstruct WSubIndex <: Expression : - exp: Expression - value: Int - type: Type with: (as-method => true) - gender: Gender with: (as-method => true) -public defstruct WSubAccess <: Expression : - exp: Expression - index: Expression - type: Type with: (as-method => true) - gender: Gender with: (as-method => true) -public defstruct WVoid <: Expression -public defstruct WInvalid <: Expression -public defstruct WDefInstance <: Stmt : - info: FileInfo with: (as-method => true) - name: Symbol - module: Symbol - type: Type - -defmulti gender (e:Expression) -> Gender -defmethod gender (e:Expression) : - MALE - -defn get-gender (s:Stmt|Port) -> Gender : - match(s) : - (s:DefWire|DefRegister) : BI-GENDER - (s:WDefInstance|DefNode|DefInstance|DefPoison) : MALE - (s:Begin|Connect|BulkConnect|Stop|Print|Empty|IsInvalid) : UNKNOWN-GENDER - (s:DefMemory) : MALE - (p:Port) : - switch { _ == direction(p) } : - INPUT : MALE - OUTPUT : FEMALE - -public defmulti kind (e:Expression) -> Kind -defmethod kind (e:Expression) : - match(e) : - (e:WRef) : kind(e) - (e:WSubField) : kind(exp(e)) - (e:WSubIndex) : kind(exp(e)) - (e) : ExpKind() - -defmethod info (stmt:Begin) -> FileInfo : FileInfo() -defmethod info (stmt:Empty) -> FileInfo : FileInfo() - -defmethod type (exp:UIntValue) -> Type : UIntType(width(exp)) -defmethod type (exp:SIntValue) -> Type : SIntType(width(exp)) -defmethod type (exp:WVoid) -> Type : UnknownType() -defmethod type (exp:WInvalid) -> Type : UnknownType() - -defmethod get-type (s:WDefInstance) -> Type : type(s) - -defmethod equal? (e1:Expression,e2:Expression) -> True|False : - match(e1,e2) : - (e1:UIntValue,e2:UIntValue) : - if to-int(value(e1)) == to-int(value(e2)) : width(e1) == width(e2) - else : false - (e1:SIntValue,e2:SIntValue) : - if to-int(value(e1)) == to-int(value(e2)) : width(e1) == width(e2) - else : false - (e1:WRef,e2:WRef) : name(e1) == name(e2) - (e1:WSubField,e2:WSubField) : - (name(e1) == name(e2)) and (exp(e1) == exp(e2)) - (e1:WSubIndex,e2:WSubIndex) : - (value(e1) == value(e2)) and (exp(e1) == exp(e2)) - (e1:WSubAccess,e2:WSubAccess) : - (index(e1) == index(e2)) and (exp(e1) == exp(e2)) - (e1:WVoid,e2:WVoid) : true - (e1:WInvalid,e2:WInvalid) : true - (e1:DoPrim,e2:DoPrim) : - var are-equal? = op(e1) == op(e2) - for (x in args(e1),y in args(e2)) do : - if not x == y : - are-equal? = false - for (x in consts(e1),y in consts(e2)) do : - if not x == y : - are-equal? = false - are-equal? - (e1:Mux,e2:Mux) : - (cond(e1) == cond(e2)) and - (tval(e1) == tval(e2)) and - (fval(e1) == fval(e2)) - (e1:ValidIf,e2:ValidIf) : - (cond(e1) == cond(e2)) and - (value(e1) == value(e2)) - (e1,e2) : false - -; ================= PRINTERS =================== -defmethod print (o:OutputStream, g:Gender) : - print{o, _} $ - switch {g == _} : - MALE : "m" - FEMALE: "f" - BI-GENDER : "b" - UNKNOWN-GENDER: "u" - -;============== DEBUG STUFF ============================= -public var PRINT-TYPES : True|False = false -public var PRINT-KINDS : True|False = false -public var PRINT-WIDTHS : True|False = false -public var PRINT-TWIDTHS : True|False = false -public var PRINT-GENDERS : True|False = false -public var PRINT-CIRCUITS : True|False = false -public var PRINT-DEBUG : True|False = false -public var PRINT-INFO : True|False = false - -;========= TO TURN OFF =========== - -var old-PRINT-TYPES : True|False = false -var old-PRINT-KINDS : True|False = false -var old-PRINT-WIDTHS : True|False = false -var old-PRINT-TWIDTHS : True|False = false -var old-PRINT-GENDERS : True|False = false -var old-PRINT-CIRCUITS : True|False = false -var old-PRINT-DEBUG : True|False = false -var old-PRINT-INFO : True|False = false -defmethod turn-off-debug (x:False) : - old-PRINT-TYPES = PRINT-TYPES - old-PRINT-KINDS = PRINT-KINDS - old-PRINT-WIDTHS = PRINT-WIDTHS - old-PRINT-TWIDTHS = PRINT-TWIDTHS - old-PRINT-GENDERS = PRINT-GENDERS - old-PRINT-CIRCUITS = PRINT-CIRCUITS - old-PRINT-DEBUG = PRINT-DEBUG - old-PRINT-INFO = PRINT-INFO - PRINT-TYPES = false - PRINT-KINDS = false - PRINT-WIDTHS = false - PRINT-TWIDTHS = false - PRINT-GENDERS = false - PRINT-CIRCUITS = false - PRINT-DEBUG = false - PRINT-INFO = false - -defmethod turn-on-debug (x:False) : - PRINT-TYPES = old-PRINT-TYPES - PRINT-KINDS = old-PRINT-KINDS - PRINT-WIDTHS = old-PRINT-WIDTHS - PRINT-TWIDTHS = old-PRINT-TWIDTHS - PRINT-GENDERS = old-PRINT-GENDERS - PRINT-CIRCUITS = old-PRINT-CIRCUITS - PRINT-DEBUG = old-PRINT-DEBUG - PRINT-INFO = old-PRINT-INFO - -;=== ThePrinters === - -public defn println-all-debug (l:?) -> False : - if PRINT-DEBUG : println-all(l) - else : false - -public defn println-debug (s:?) -> False : - if PRINT-DEBUG : println(s) - else : false - -defmethod print (o:OutputStream, k:Kind) : - print{o, _} $ - match(k) : - (k:WireKind) : "wire" - (k:PoisonKind) : "poison" - (k:RegKind) : "reg" - (k:PortKind) : "port" - (k:MemKind) : "mem" - (k:NodeKind) : "node" - (k:InstanceKind) : "inst" - (k:ExpKind) : "exp" - -defn hasGender (e:?) : - e typeof Expression - -defn hasWidth (e:?) : - e typeof UIntType|SIntType|UIntValue|SIntValue - -defn hasType (e:?) : - e typeof Expression|DefWire|DefRegister|DefPoison - |VectorType|Port|UIntValue|SIntValue - -defn hasKind (e:?) : - e typeof Expression - -defn hasInfo (e:?) : - e typeof Stmt|Port|Circuit|Module - -defn any-debug? (e:?) : - (hasGender(e) and PRINT-GENDERS) or - (hasType(e) and PRINT-TYPES) or - (hasWidth(e) and PRINT-WIDTHS) or - (hasKind(e) and PRINT-KINDS) or - (hasInfo(e) and PRINT-INFO) - -defmethod print-debug (o:OutputStream, e:Expression|Stmt|Type|Port|Field|Module|Circuit) : - defn wipe-width (t:Type) -> Type : - match(t) : - (t:UIntType) : UIntType(UnknownWidth()) - (t:SIntType) : SIntType(UnknownWidth()) - (t) : map(wipe-width,t) - - if any-debug?(e) : print(o,"@") - if PRINT-KINDS and hasKind(e) : print-all(o,["<k:" kind(e as ?) ">"]) - if PRINT-TYPES and hasType(e) : print-all(o,["<t:" wipe-width(type(e as ?)) ">"]) - if PRINT-TWIDTHS and hasType(e): print-all(o,["<t:" type(e as ?) ">"]) - if PRINT-WIDTHS and hasWidth(e): print-all(o,["<w:" width(e as ?) ">"]) - if PRINT-GENDERS and hasGender(e): print-all(o,["<g:" gender(e as ?) ">"]) - if PRINT-INFO and hasInfo(e): print-all(o,["<i:" info(e as ?) ">"]) - -defmethod print (o:OutputStream, e:WRef) : - print(o,name(e)) - print-debug(o,e as ?) -defmethod print (o:OutputStream, e:WSubField) : - print-all(o,[exp(e) "." name(e)]) - print-debug(o,e as ?) -defmethod print (o:OutputStream, e:WSubIndex) : - print-all(o,[exp(e) "[" value(e) "]"]) - print-debug(o,e as ?) -defmethod print (o:OutputStream, e:WSubAccess) : - print-all(o,[exp(e) "[" index(e) "]"]) - print-debug(o,e as ?) -defmethod print (o:OutputStream, e:WVoid) : - print(o,"VOID") - print-debug(o,e as ?) -defmethod print (o:OutputStream, e:WInvalid) : - print(o,"INVALID") - print-debug(o,e as ?) -defmethod print (o:OutputStream, c:WDefInstance) : - print-all(o, ["inst " name(c) " of " module(c) " : " type(c)]) - print-debug(o,c as ?) - - -defmethod map (f: Expression -> Expression, e: WSubField) : - WSubField(f(exp(e)), name(e), type(e), gender(e)) -defmethod map (f: Expression -> Expression, e: WSubIndex) : - WSubIndex(f(exp(e)), value(e), type(e), gender(e)) -defmethod map (f: Expression -> Expression, e: WSubAccess) : - WSubAccess(f(exp(e)), f(index(e)), type(e), gender(e)) - -defmethod map (f: Type -> Type, e: WRef) : - WRef(name(e), f(type(e)), kind(e), gender(e)) -defmethod map (f: Type -> Type, e: WSubField) : - WSubField(exp(e), name(e), f(type(e)), gender(e)) -defmethod map (f: Type -> Type, e: WSubIndex) : - WSubIndex(exp(e), value(e), f(type(e)), gender(e)) -defmethod map (f: Type -> Type, e: WSubAccess) : - WSubAccess(exp(e), index(e), f(type(e)), gender(e)) - -defmethod map (f: Type -> Type, s: WDefInstance) : - WDefInstance(info(s),name(s),module(s),f(type(s))) -defmethod map (f: Symbol -> Symbol, s: WDefInstance) : - WDefInstance(info(s),f(name(s)),module(s),type(s)) - -;================ WIDTH LIBRARY ==================== - -public val ONE = IntWidth(1) -public defstruct VarWidth <: Width : - name: Symbol -public defstruct PlusWidth <: Width : - arg1 : Width - arg2 : Width -public defstruct MinusWidth <: Width : - arg1 : Width - arg2 : Width -public defstruct MaxWidth <: Width : - args : List<Width> -public defstruct MinWidth <: Width : - args : List<Width> -public defstruct ExpWidth <: Width : - arg1 : Width -val width-name-hash = HashTable<Symbol,Int>(symbol-hash) - -public defmulti map<?T> (f: Width -> Width, w:?T&Width) -> T -defmethod map (f: Width -> Width, w:Width) -> Width : - match(w) : - (w:MaxWidth) : MaxWidth(map(f,args(w))) - (w:MinWidth) : MinWidth(map(f,args(w))) - (w:PlusWidth) : PlusWidth(f(arg1(w)),f(arg2(w))) - (w:MinusWidth) : MinusWidth(f(arg1(w)),f(arg2(w))) - (w:ExpWidth) : ExpWidth(f(arg1(w))) - (w) : w - -public defmethod print (o:OutputStream, w:VarWidth) : - print(o,name(w)) -public defmethod print (o:OutputStream, w:MaxWidth) : - print-all(o,["max" args(w)]) -public defmethod print (o:OutputStream, w:MinWidth) : - print-all(o,["min" args(w)]) -public defmethod print (o:OutputStream, w:PlusWidth) : - print-all(o,[ "(" arg1(w) " + " arg2(w) ")"]) -public defmethod print (o:OutputStream, w:MinusWidth) : - print-all(o,[ "(" arg1(w) " - " arg2(w) ")"]) -public defmethod print (o:OutputStream, w:ExpWidth) : - print-all(o,[ "exp(" arg1(w) ")"]) - -defn remove-unknowns-w (w:Width) -> Width : - match(w) : - (w:UnknownWidth) : VarWidth(firrtl-gensym(`w,width-name-hash)) - (w) : w -defn remove-unknowns (t:Type) -> Type : mapr(remove-unknowns-w,t) - -defmethod equal? (w1:Width,w2:Width) -> True|False : - match(w1,w2) : - (w1:VarWidth,w2:VarWidth) : name(w1) == name(w2) - (w1:MaxWidth,w2:MaxWidth) : - label<True|False> ret : - if not length(args(w1)) == length(args(w2)) : ret(false) - else : - for w in args(w1) do : - if not contains?(args(w2),w) : ret(false) - ret(true) - (w1:MinWidth,w2:MinWidth) : - label<True|False> ret : - if not length(args(w1)) == length(args(w2)) : ret(false) - else : - for w in args(w1) do : - if not contains?(args(w2),w) : ret(false) - ret(true) - (w1:IntWidth,w2:IntWidth) : width(w1) == width(w2) - (w1:PlusWidth,w2:PlusWidth) : - (arg1(w1) == arg1(w2) and arg2(w1) == arg2(w2)) or (arg1(w1) == arg2(w2) and arg2(w1) == arg1(w2)) - (w1:MinusWidth,w2:MinusWidth) : - (arg1(w1) == arg1(w2) and arg2(w1) == arg2(w2)) or (arg1(w1) == arg2(w2) and arg2(w1) == arg1(w2)) - (w1:ExpWidth,w2:ExpWidth) : arg1(w1) == arg1(w2) - (w1:UnknownWidth,w2:UnknownWidth) : true - (w1,w2) : false -;================ WORKING IR UTILS ========================= -;defn plus (g1:Gender,g2:Gender) -> Gender : -; switch fn ([x,y]) : g1 == x and g2 == y : -; [FEMALE,MALE] : UNKNOWN-GENDER -; [MALE,FEMALE] : UNKNOWN-GENDER -; [MALE,MALE] : MALE -; [FEMALE,FEMALE] : FEMALE -; [BI-GENDER,MALE] : MALE -; [BI-GENDER,FEMALE] : FEMALE -; [MALE,BI-GENDER] : MALE -; [FEMALE,BI-GENDER] : FEMALE - -; These functions do not error, but return Unknown Type -defn module-type (m:Module) -> Type : - BundleType(for p in ports(m) map : to-field(p)) -defn field-type (v:Type,s:Symbol) -> Type : - match(v) : - (v:BundleType) : - val ft = for p in fields(v) find : name(p) == s - if ft != false : type(ft as Field) - else : UnknownType() - (v) : UnknownType() -defn sub-type (v:Type) -> Type : - match(v) : - (v:VectorType) : type(v) - (v) : UnknownType() -defn field-flip (v:Type,s:Symbol) -> Flip : - match(v) : - (v:BundleType) : - val ft = for p in fields(v) find : name(p) == s - if ft != false : flip(ft as Field) - else : DEFAULT ;This will get caught later - (v) : DEFAULT - -defn swap (g:Gender) -> Gender : - switch {_ == g} : - UNKNOWN-GENDER : UNKNOWN-GENDER - MALE : FEMALE - FEMALE : MALE - BI-GENDER : BI-GENDER -defn swap (d:Direction) -> Direction : - switch {_ == d} : - OUTPUT : INPUT - INPUT : OUTPUT - -public defn times (flip:Flip,d:Direction) -> Direction : - flip * d -public defn times (d:Direction,flip:Flip) -> Direction : - switch {_ == flip} : - DEFAULT : d - REVERSE : swap(d) -public defn times (g:Gender,flip:Flip) -> Gender : flip * g -public defn times (flip:Flip,g:Gender) -> Gender : - switch {_ == flip} : - DEFAULT : g - REVERSE : swap(g) -defn to-field (p:Port) -> Field : - if direction(p) == OUTPUT : Field(name(p),DEFAULT,type(p)) - else if direction(p) == INPUT : Field(name(p),REVERSE,type(p)) - else : error("Shouldn't be here") -defn to-dir (g:Gender) -> Direction : - switch {_ == g} : - MALE : INPUT - FEMALE : OUTPUT -defn to-gender (d:Direction) -> Gender : - switch {_ == d} : - INPUT: MALE - OUTPUT: FEMALE - -public defn mux-type-and-widths (e1:Expression,e2:Expression) -> Type : - mux-type-and-widths(type(e1),type(e2)) -public defn mux-type-and-widths (t1:Type,t2:Type) -> Type : - defn wmax (w1:Width,w2:Width) -> Width : - match(w1,w2) : - (w1:IntWidth,w2:IntWidth) : IntWidth(max(width(w1),width(w2))) - (w1,w2) : MaxWidth(list(w1,w2)) - if t1 == t2 : - match(t1,t2) : - (t1:UIntType,t2:UIntType) : UIntType(wmax(width(t1),width(t2))) - (t1:SIntType,t2:SIntType) : SIntType(wmax(width(t1),width(t2))) - (t1:VectorType,t2:VectorType) : VectorType(mux-type-and-widths(type(t1),type(t2)),size(t1)) - (t1:BundleType,t2:BundleType) : - BundleType $ for (f1 in fields(t1),f2 in fields(t2)) map : - Field(name(f1),flip(f1),mux-type-and-widths(type(f1),type(f2))) - else : UnknownType() - -;================= Remove Special Characters ======================== -; Returns a new Circuit where all names have all special characters -; removed, except _. -; -;public defstruct RemoveSpecialChars <: Pass -;public defmethod pass (b:RemoveSpecialChars) -> (Circuit -> Circuit) : remove-special-chars -;public defmethod name (b:RemoveSpecialChars) -> String : "Remove Special Characters" -;public defmethod short-name (b:RemoveSpecialChars) -> String : "rem-spec-chars" -; -;;------------ Helper Functions ------------- -; -;defn get-new-string (n:Char) -> String : -; switch {n == _} : -; '_' : "__" -; '~' : "$A" -; '!' : "$B" -; '@' : "$C" -; '#' : "$D" -; '$' : "$E" -; '%' : "$F" -; '^' : "$G" -; '*' : "$H" -; '-' : "$I" -; '+' : "$J" -; '=' : "$K" -; '?' : "$L" -; '/' : "$M" -; else : to-string(n) -; -;;------------ Pass ------------------ -; -;defn remove-special-chars (c:Circuit) : -; defn rename (n:Symbol) -> Symbol : -; val v = Vector<String>() -; for c in to-string(n) do : -; add(v,get-new-string(c)) -; val n* = symbol-join(v) -; if key?(v-keywords,n*) : -; symbol-join([n* `_]) -; else : -; n* -; defn rename-t (t:Type) -> Type : -; match(t) : -; (t:BundleType) : BundleType $ -; for f in fields(t) map : -; Field(rename(name(f)),flip(f),rename-t(type(f))) -; (t:VectorType) : VectorType(rename-t(type(t)),size(t)) -; (t) : t -; defn rename-e (e:Expression) -> Expression : -; match(e) : -; (e:Ref) : Ref(rename(name(e)),rename-t(type(e))) -; (e:Subfield) : Subfield(rename-e(exp(e)),rename(name(e)),rename-t(type(e))) -; (e:Index) : Index(rename-e(exp(e)),value(e),rename-t(type(e))) -; (e:DoPrim) : DoPrim{op(e),_,consts(e),rename-t(type(e))} $ for x in args(e) map : rename-e(x) -; (e:UIntValue) : e -; (e:SIntValue) : e -; defn rename-s (s:Stmt) -> Stmt : -; match(s) : -; (s:DefWire) : DefWire(info(s),rename(name(s)),rename-t(type(s))) -; (s:DefPoison) : DefPoison(info(s),rename(name(s)),rename-t(type(s))) -; (s:DefRegister) : DefRegister(info(s),rename(name(s)),rename-t(type(s)),rename-e(clock(s)),rename-e(reset(s))) -; (s:WDefInstance) : WDefInstance(info(s),rename(name(s)),rename-e(module(s))) -; (s:DefMemory) : DefMemory(info(s),rename(name(s)),rename-t(type(s)),seq?(s),rename-e(clock(s)),size(s)) -; (s:DefNode) : DefNode(info(s),rename(name(s)),rename-e(value(s))) -; (s:DefAccessor) : DefAccessor(info(s),rename(name(s)),rename-e(source(s)),rename-e(index(s)),acc-dir(s)) -; (s:Conditionally) : Conditionally(info(s),rename-e(pred(s)),rename-s(conseq(s)),rename-s(alt(s))) -; (s:Begin) : Begin $ for b in body(s) map : rename-s(b) -; (s:OnReset) : OnReset(info(s),rename-e(loc(s)),rename-e(exp(s))) -; (s:BulkConnect) : BulkConnect(info(s),rename-e(loc(s)),rename-e(exp(s))) -; (s:Connect) : Connect(info(s),rename-e(loc(s)),rename-e(exp(s))) -; (s:EmptyStmt) : s -; (s:StopStmt) : s -; (s:PrintfStmt) : PrintfStmt(info(s),string(s),map(rename-e,args(s))) -; -; Circuit(info(c),modules*, rename(main(c))) where : -; val modules* = -; for m in modules(c) map : -; match(m) : -; (m:InModule) : -; val ports* = for p in ports(m) map : -; Port(info(p),rename(name(p)),direction(p),rename-t(type(p))) -; InModule(info(m),rename(name(m)), ports*, rename-s(body(m))) -; (m:ExModule) : m - - -;================= Temporary Variable Elimination ======================== -; Returns a new Circuit where temporary variables are removed and returns -; the resulting nested expression -;public defstruct TempElimination <: Pass -;public defmethod pass (b:TempElimination) -> (Circuit -> Circuit) : temp-elimination -;public defmethod name (b:TempElimination) -> String : "Temp Elimination" -;public defmethod short-name (b:TempElimination) -> String : "temp-elim" -; -;defn temp-elimination (c:Circuit) : -; defn is-temp? (n:Symbol) -> True|False : -; to-string(n)[0] == 'T' -; defn temp-elim (m:InModule) : -; val h = HashTable<Symbol,Expression>(symbol-hash) -; defn temp-elim-e (e:Expression) : -; match(map(temp-elim-e,e)) : -; (e:Ref) : -; if key?(h,name(e)) : h[name(e)] -; else : e -; (e) : e -; defn temp-elim-s (s:Stmt) : -; match(map(temp-elim-e,s)) : -; (s:DefNode) : -; if is-temp?(name(s)) : -; h[name(s)] = value(s) -; EmptyStmt() -; else : s -; (s) : map(temp-elim-s,s) -; InModule(info(m),name(m), ports(m), temp-elim-s(body(m))) -; -; Circuit(info(c),modules*, main(c)) where : -; val modules* = -; for m in modules(c) map : -; match(m) : -; (m:InModule) : temp-elim(m) -; (m:ExModule) : m - -;================= Bring to Working IR ======================== -; Returns a new Circuit with Refs, Subfields, Indexes and DefAccessors -; replaced with IR-internal nodes that contain additional -; information (kind, gender) - -public defstruct ToWorkingIR <: Pass -public defmethod pass (b:ToWorkingIR) -> (Circuit -> Circuit) : to-working-ir -public defmethod name (b:ToWorkingIR) -> String : "Working IR" -public defmethod short-name (b:ToWorkingIR) -> String : "to-working-ir" - -defn to-working-ir (c:Circuit) : - defn to-exp (e:Expression) -> Expression : - match(map(to-exp,e)) : - (e:Ref) : WRef(name(e), type(e), NodeKind(), UNKNOWN-GENDER) - (e:SubField) : WSubField(exp(e), name(e), type(e), UNKNOWN-GENDER) - (e:SubIndex) : WSubIndex(exp(e), value(e), type(e), UNKNOWN-GENDER) - (e:SubAccess) : WSubAccess(exp(e), index(e), type(e), UNKNOWN-GENDER) - (e) : e - defn to-stmt (s:Stmt) -> Stmt : - match(map(to-exp,s)) : - (s:DefInstance) : WDefInstance(info(s),name(s),module(s),UnknownType()) - (s) : map(to-stmt,s) - - Circuit(info(c),modules*, main(c)) where : - val modules* = - for m in modules(c) map : - match(m) : - (m:InModule) : InModule(info(m),name(m), ports(m), to-stmt(body(m))) - (m:ExModule) : m - -;=============== Resolve Kinds ============================= -; It is useful for the compiler to know information about -; objects referenced. This information is stored in the kind -; field in WRef. This pass walks the graph and returns a new -; Circuit where all WRef kinds are resolved -public defstruct ResolveKinds <: Pass -public defmethod pass (b:ResolveKinds) -> (Circuit -> Circuit) : resolve-kinds -public defmethod name (b:ResolveKinds) -> String : "Resolve Kinds" -public defmethod short-name (b:ResolveKinds) -> String : "resolve-kinds" - -defn resolve-kinds (c:Circuit) : - defn resolve (body:Stmt, kinds:HashTable<Symbol,Kind>) : - defn resolve-stmt (s:Stmt) -> Stmt : - map{resolve-expr,_} $ - map(resolve-stmt,s) - - defn resolve-expr (e:Expression) -> Expression : - match(e) : - (e:WRef) : WRef(name(e),type(e),kinds[name(e)],gender(e)) - (e) : map(resolve-expr,e) - - resolve-stmt(body) - - defn find (m:Module, kinds:HashTable<Symbol,Kind>) : - defn find-stmt (s:Stmt) -> Stmt : - match(s) : - (s:DefWire) : kinds[name(s)] = WireKind() - (s:DefPoison) : kinds[name(s)] = PoisonKind() - (s:DefNode) : kinds[name(s)] = NodeKind() - (s:DefRegister) : kinds[name(s)] = RegKind() - (s:WDefInstance) : kinds[name(s)] = InstanceKind() - (s:DefMemory) : kinds[name(s)] = MemKind(append-all([readers(s) writers(s) readwriters(s)])) - (s) : false - map(find-stmt,s) - - for p in ports(m) do : - kinds[name(p)] = PortKind() - match(m) : - (m:InModule) : find-stmt(body(m)) - (m:ExModule) : false - - defn resolve-kinds (m:Module, c:Circuit) -> Module : - val kinds = HashTable<Symbol,Kind>(symbol-hash) - find(m,kinds) - match(m) : - (m:InModule) : - val body! = resolve(body(m),kinds) - InModule(info(m),name(m),ports(m),body!) - (m:ExModule) : ExModule(info(m),name(m),ports(m)) - - Circuit(info(c),modules*, main(c)) where : - val modules* = - for m in modules(c) map : - resolve-kinds(m,c) - -;============== INFER TYPES ================================ - -; ------------------ Utils ------------------------- - -defn set-type (s:Stmt,t:Type) -> Stmt : - match(s) : - (s:DefWire) : DefWire(info(s),name(s),t) - (s:DefRegister) : DefRegister(info(s),name(s),t,clock(s),reset(s),init(s)) - (s:DefMemory) : DefMemory(info(s),name(s),t,depth(s),write-latency(s),read-latency(s),readers(s),writers(s),readwriters(s)) - (s:DefNode) : s - (s:DefPoison) : DefPoison(info(s),name(s),t) - - -; ------------------ Pass ------------------------- -public defstruct InferTypes <: Pass -public defmethod pass (b:InferTypes) -> (Circuit -> Circuit) : infer-types -public defmethod name (b:InferTypes) -> String : "Infer Types" -public defmethod short-name (b:InferTypes) -> String : "infer-types" - -defn infer-types (c:Circuit) -> Circuit : - val module-types = HashTable<Symbol,Type>(symbol-hash) - defn infer-types (m:Module) -> Module : - val types = HashTable<Symbol,Type>(symbol-hash) - defn infer-types-e (e:Expression) -> Expression : - match(map(infer-types-e,e)) : - (e:ValidIf) : ValidIf(cond(e),value(e),type(value(e))) - (e:WRef) : WRef(name(e), types[name(e)],kind(e),gender(e)) - (e:WSubField) : WSubField(exp(e),name(e),field-type(type(exp(e)),name(e)),gender(e)) - (e:WSubIndex) : WSubIndex(exp(e),value(e),sub-type(type(exp(e))),gender(e)) - (e:WSubAccess) : WSubAccess(exp(e),index(e),sub-type(type(exp(e))),gender(e)) - (e:DoPrim) : set-primop-type(e) - (e:Mux) : Mux(cond(e),tval(e),fval(e),mux-type-and-widths(tval(e),fval(e))) - (e:UIntValue|SIntValue) : e - defn infer-types-s (s:Stmt) -> Stmt : - match(s) : - (s:DefRegister) : - val t = remove-unknowns(get-type(s)) - types[name(s)] = t - map(infer-types-e,set-type(s,t)) - (s:DefWire|DefPoison|DefNode) : - val s* = map(infer-types-e,s) - val t = remove-unknowns(get-type(s*)) - types[name(s*)] = t - set-type(s*,t) - (s:DefMemory) : - val t = remove-unknowns(get-type(s)) - types[name(s)] = t - val dt = remove-unknowns(data-type(s)) - set-type(s,dt) - (s:WDefInstance) : - types[name(s)] = module-types[module(s)] - WDefInstance(info(s),name(s),module(s),module-types[module(s)]) - (s) : map{infer-types-e,_} $ map(infer-types-s,s) - for p in ports(m) do : - types[name(p)] = type(p) - match(m) : - (m:InModule) : - InModule(info(m),name(m),ports(m),infer-types-s(body(m))) - (m:ExModule) : m - - ; MAIN - val modules* = - for m in modules(c) map : - val ports* = - for p in ports(m) map : - Port(info(p),name(p),direction(p),remove-unknowns(type(p))) - match(m) : - (m:InModule) : InModule(info(m),name(m),ports*,body(m)) - (m:ExModule) : ExModule(info(m),name(m),ports*) - - for m in modules* do : - module-types[name(m)] = module-type(m) - Circuit{info(c), _, main(c) } $ - for m in modules* map : - infer-types(m) - -;============= RESOLVE GENDER ============================ -; To ensure a proper circuit, we must ensure that assignments -; only work on expressions that can be assigned to. Similarly, -; we must ensure that only expressions that can be read from -; are used to assign from. This invariant requires each -; expression's gender to be inferred. -; Various elements can be bi-gender (e.g. wires) and can -; thus be treated as either female or male. Conversely, some -; elements are single-gender (e.g. accessors, ports). -public defstruct ResolveGenders <: Pass -public defmethod pass (b:ResolveGenders) -> (Circuit -> Circuit) : resolve-genders -public defmethod name (b:ResolveGenders) -> String : "Resolve Genders" -public defmethod short-name (b:ResolveGenders) -> String : "resolve-genders" - -defn resolve-genders (c:Circuit) : - defn resolve-e (e:Expression,g:Gender) -> Expression : - match(e) : - (e:WRef) : WRef(name(e),type(e),kind(e),g) - (e:WSubField) : - val exp* = - switch { _ == field-flip(type(exp(e)),name(e)) } : - DEFAULT : resolve-e(exp(e),g) - REVERSE : resolve-e(exp(e),swap(g)) - WSubField(exp*,name(e),type(e),g) - (e:WSubIndex) : - val exp* = resolve-e(exp(e),g) - WSubIndex(exp*,value(e),type(e),g) - (e:WSubAccess) : - val exp* = resolve-e(exp(e),g) - val index* = resolve-e(index(e),MALE) - WSubAccess(exp*,index*,type(e),g) - (e) : map(resolve-e{_,g},e) - - defn resolve-s (s:Stmt) -> Stmt : - match(s) : - (s:IsInvalid) : - val exp* = resolve-e(exp(s),FEMALE) - IsInvalid(info(s),exp*) - (s:Connect) : - val loc* = resolve-e(loc(s),FEMALE) - val exp* = resolve-e(exp(s),MALE) - Connect(info(s),loc*,exp*) - (s:BulkConnect) : - val loc* = resolve-e(loc(s),FEMALE) - val exp* = resolve-e(exp(s),MALE) - BulkConnect(info(s),loc*,exp*) - (s) : - map{resolve-s,_} $ map(resolve-e{_,MALE},s) - Circuit(info(c),modules*, main(c)) where : - val modules* = - for m in modules(c) map : - match(m) : - (m:InModule) : - val body* = resolve-s(body(m)) - InModule(info(m),name(m),ports(m),body*) - (m:ExModule) : m - -;============= Pull Muxes =============== - -public defstruct PullMuxes <: Pass -public defmethod pass (b:PullMuxes) -> (Circuit -> Circuit) : pull-muxes -public defmethod name (b:PullMuxes) -> String : "Pull Muxes" -public defmethod short-name (b:PullMuxes) -> String : "pull-muxes" - -defn pull-muxes (c:Circuit) -> Circuit : - defn pull-muxes-e (e:Expression) -> Expression : - map{pull-muxes-e,_} $ match(map(pull-muxes-e,e)) : - (e:WRef) : e - (e:WSubField) : - match(exp(e)) : - (e*:Mux) : Mux(cond(e*),WSubField(tval(e*),name(e),type(e),gender(e)),WSubField(fval(e*),name(e),type(e),gender(e)),type(e)) - (e*:ValidIf) : ValidIf(cond(e*),WSubField(value(e*),name(e),type(e),gender(e)),type(e)) - (e*) : e - (e:WSubIndex) : - match(exp(e)) : - (e*:Mux) : Mux(cond(e*),WSubIndex(tval(e*),value(e),type(e),gender(e)),WSubIndex(fval(e*),value(e),type(e),gender(e)),type(e)) - (e*:ValidIf) : ValidIf(cond(e*),WSubIndex(value(e*),value(e),type(e),gender(e)),type(e)) - (e*) : e - (e:WSubAccess) : - match(exp(e)) : - (e*:Mux) : Mux(cond(e*),WSubAccess(tval(e*),index(e),type(e),gender(e)),WSubAccess(fval(e*),index(e),type(e),gender(e)),type(e)) - (e*:ValidIf) : ValidIf(cond(e*),WSubAccess(value(e*),index(e),type(e),gender(e)),type(e)) - (e*) : e - (e:Mux) : e - (e:ValidIf) : e - (e) : e - - defn pull-muxes (s:Stmt) -> Stmt : - map(pull-muxes-e,map(pull-muxes,s)) - - Circuit{info(c),_,main(c)} $ - for m in modules(c) map : - match(m) : - (m:InModule) : InModule(info(m),name(m),ports(m),pull-muxes(body(m))) - (m:ExModule) : m - -;================ EXPAND CONNECTS ================== -public defstruct ExpandConnects <: Pass -public defmethod pass (b:ExpandConnects) -> (Circuit -> Circuit) : expand-connects -public defmethod name (b:ExpandConnects) -> String : "Expand Connects" -public defmethod short-name (b:ExpandConnects) -> String : "expand-connects" - -;---------------- UTILS ------------------ - -defn get-size (e:Expression) -> Int : get-size(type(e)) -defn get-flip (t:Type, i:Int, f:Flip) -> Flip : - if i >= get-size(t) : error("Shouldn't be here") - val x = match(t) : - (t:UIntType|SIntType|ClockType) : f - (t:BundleType) : label<Flip> ret : - var n = i - for x in fields(t) do : - if n < get-size(type(x)) : - ret(get-flip(type(x),n,flip(x) * f)) - else : - n = n - get-size(type(x)) - error("Shouldn't be here") - (t:VectorType) : label<Flip> ret : - var n = i - for j in 0 to size(t) do : - if n < get-size(type(t)) : - ret(get-flip(type(t),n,f)) - else : - n = n - get-size(type(t)) - error("Shouldn't be here") - x - -defn get-point (e:Expression) -> Int : - match(e) : - (e:WRef) : 0 - (e:WSubField) : - var i = 0 - for f in fields(type(exp(e)) as BundleType) find : - val b = name(f) == name(e) - if not b : i = i + get-size(type(f)) - b - i - (e:WSubIndex) : - value(e) * get-size(e) - (e:WSubAccess) : - get-point(exp(e)) - -defn create-exps (n:Symbol, t:Type) -> List<Expression> : - create-exps(WRef(n,t,ExpKind(),UNKNOWN-GENDER)) -defn create-exps (e:Expression) -> List<Expression> : - match(e) : - (e:Mux) : - for (e1 in create-exps(tval(e)), e2 in create-exps(fval(e))) map : - Mux(cond(e),e1,e2,mux-type-and-widths(e1,e2)) - (e:ValidIf) : - for e1 in create-exps(value(e)) map : - ValidIf(cond(e),e1,type(e1)) - (e) : - match(type(e)) : - (t:UIntType|SIntType|ClockType) : list(e) - (t:BundleType) : - for f in fields(t) map-append : - create-exps(WSubField(e,name(f),type(f),gender(e) * flip(f))) - (t:VectorType) : - for i in 0 to size(t) map-append : - create-exps(WSubIndex(e,i,type(t),gender(e))) - -defn gexp-hash (e:Expression) -> Int : - turn-off-debug(false) - val ls = to-list([mname `.... e `.... gender(e) `.... type(e)]) - ;val ls = to-list([e `.... gender(e) `.... type(e)]) - val i = symbol-hash(symbol-join(ls)) - ;val i = symbol-hash(to-symbol(to-string(e))) - turn-on-debug(false) - i -val hashed-create-exps = HashTable<Expression,List<Expression>>(gexp-hash) -defn fast-create-exps (n:Symbol, t:Type) -> List<Expression> : - fast-create-exps(WRef(n,t,ExpKind(),UNKNOWN-GENDER)) -defn fast-create-exps (e:Expression) -> List<Expression> : - if key?(hashed-create-exps,e) : - hashed-create-exps[e] - else : - match(e) : - (e:Mux) : - val x = for (e1 in create-exps(tval(e)), e2 in create-exps(fval(e))) map : - Mux(cond(e),e1,e2,mux-type-and-widths(e1,e2)) - hashed-create-exps[e] = x - x - (e:ValidIf) : - val x = for e1 in create-exps(value(e)) map : - ValidIf(cond(e),e1,type(e1)) - hashed-create-exps[e] = x - x - (e) : - val es = Vector<List<Expression>>() - match(type(e)) : - (t:UIntType|SIntType|ClockType) : add(es,list(e)) - (t:BundleType) : - for f in fields(t) do : - add(es,fast-create-exps(WSubField(e,name(f),type(f),gender(e) * flip(f)))) - (t:VectorType) : - for i in 0 to size(t) do : - add(es,fast-create-exps(WSubIndex(e,i,type(t),gender(e)))) - val x = append-all(es) - hashed-create-exps[e] = x - x - -;---------------- Pass --------------------- - -defn expand-connects (c:Circuit) -> Circuit : - defn expand-connects (m:InModule) -> InModule : - mname = name(m) - val genders = HashTable<Symbol,Gender>(symbol-hash) - defn expand-s (s:Stmt) -> Stmt : - defn set-gender (e:Expression) -> Expression : - match(map(set-gender,e)) : - (e:WRef) : WRef(name(e),type(e),kind(e),genders[name(e)]) - (e:WSubField) : - val f = {_ as Field} $ - for f in fields(type(exp(e)) as BundleType) find : - name(f) == name(e) - val gender* = gender(exp(e)) * flip(f) - WSubField(exp(e),name(e),type(e),gender*) - (e:WSubIndex) : WSubIndex(exp(e),value(e),type(e),gender(exp(e))) - (e:WSubAccess) : WSubAccess(exp(e),index(e),type(e),gender(exp(e))) - (e) : e - match(s) : - (s:DefWire|DefRegister) : - genders[name(s)] = BI-GENDER - s - (s:WDefInstance|DefMemory|DefPoison|DefNode) : - genders[name(s)] = MALE - s - (s:IsInvalid) : - val n = get-size(exp(s)) - val invalids = Vector<Stmt>() - val exps = create-exps(exp(s)) - for i in 0 to n do : - val exp* = exps[i] - val gexp* = set-gender(exp*) - switch { _ == gender(gexp*) } : - BI-GENDER : add(invalids,IsInvalid(info(s),exp*)) - FEMALE : add(invalids,IsInvalid(info(s),exp*)) - else : false - if length(invalids) == 0 : Empty() - else if length(invalids) == 1 : invalids[0] - else : Begin(to-list(invalids)) - (s:Connect) : - val n = get-size(loc(s)) - val connects = Vector<Stmt>() - val locs = create-exps(loc(s)) - val exps = create-exps(exp(s)) - for i in 0 to n do : - val loc* = locs[i] - val exp* = exps[i] - add{connects,_} $ - switch { _ == get-flip(type(loc(s)),i,DEFAULT) } : - DEFAULT : Connect(info(s),loc*,exp*) - REVERSE : Connect(info(s),exp*,loc*) - Begin(to-list(connects)) - (s:BulkConnect) : - val ls = get-valid-points(type(loc(s)),type(exp(s)),DEFAULT,DEFAULT) - val connects = Vector<Stmt>() - val locs = create-exps(loc(s)) - val exps = create-exps(exp(s)) - for x in ls do : - val loc* = locs[x[0]] - val exp* = exps[x[1]] - add{connects,_} $ - switch { _ == get-flip(type(loc(s)),x[0],DEFAULT) } : - DEFAULT : Connect(info(s),loc*,exp*) - REVERSE : Connect(info(s),exp*,loc*) - Begin(to-list(connects)) - (s) : map(expand-s,s) - - for p in ports(m) do : - genders[name(p)] = to-gender(direction(p)) - InModule(info(m),name(m),ports(m),expand-s(body(m))) - - Circuit(info(c),modules*, main(c)) where : - val modules* = - for m in modules(c) map : - match(m) : - (m:ExModule) : m - (m:InModule) : expand-connects(m) - - -;;;================ REPLACE INDEXERS ========================= -; This pass inlines all accessors to non-memory vector typed -; components. - -public defstruct RemoveAccesses <: Pass -public defmethod pass (b:RemoveAccesses) -> (Circuit -> Circuit) : remove-access -public defmethod name (b:RemoveAccesses) -> String : "Remove Accesses" -public defmethod short-name (b:RemoveAccesses) -> String : "remove-access" - -defstruct Location : - base : Expression - guard : Expression -defmethod print (o:OutputStream,x:Location) : - print-all(o,["[" base(x) " , " guard(x) "]"]) - -defn get-locations (e:Expression) -> List<Location> : - match(e) : - (e:WRef) : map(Location{_,one},create-exps(e)) - (e:WSubIndex|WSubField) : - val ls = get-locations(exp(e)) - val start = get-point(e) - val end = start + get-size(e) - val stride = get-size(exp(e)) - val ls* = Vector<Location>() - var c = 0 - for i in 0 to length(ls) do : - if (i % stride >= start and i % stride < end) : - add(ls*,ls[i]) - to-list(ls*) - (e:WSubAccess) : - val ls = get-locations(exp(e)) - val stride = get-size(e) - val wrap = size(type(exp(e)) as VectorType) - val ls* = Vector<Location>() - var c = 0 - for i in 0 to length(ls) do : - if c % wrap == 0 : c = 0 - val base* = base(ls[i]) - val guard* = AND(guard(ls[i]),EQV(uint(c),index(e))) - add(ls*,Location(base*,guard*)) - if (i + 1) % stride == 0 : c = c + 1 - to-list(ls*) - -defn has-access? (e:Expression) -> True|False : - var ret = false - defn rec-has-access (e:Expression) -> Expression : - match(e) : - (e:WSubAccess) : - ret = true - e - (e) : map(rec-has-access,e) - rec-has-access(e) - ret - -defn remove-access (c:Circuit) : - defn remove-m (m:InModule) -> InModule : - val sh = get-sym-hash(m,keys(v-keywords)) - mname = name(m) - defn remove-s (s:Stmt) -> Stmt : - val stmts = Vector<Stmt>() - defn create-temp (e:Expression) -> Expression : - val n = firrtl-gensym(`GEN,sh) - add(stmts,DefWire(info(s),n,type(e))) - WRef(n,type(e),kind(e),gender(e)) - defn remove-e (e:Expression) -> Expression : ;NOT RECURSIVE (except primops) INTENTIONALLY! - match(e) : - (e:DoPrim) : map(remove-e,e) - (e:Mux) : map(remove-e,e) - (e:ValidIf) : map(remove-e,e) - (e:UIntValue|SIntValue) : e - (e) : - if has-access?(e) : - val rs = get-locations(e) - val foo = for x in rs find : - (guard(x)) != one - if foo == false : error("Shouldn't be here") - else : - val temp = create-temp(e) - val temps = create-exps(temp) - defn get-temp (i:Int) : - temps[i % length(temps)] - for (x in rs, i in 0 to false) do : - if i < length(temps) : - add(stmts,Connect(info(s),get-temp(i),base(x))) - else : - add(stmts,Conditionally(info(s),guard(x),Connect(info(s),get-temp(i),base(x)),Empty())) - temp - else : e - val s* = match(s) : - (s:Connect) : - if has-access?(loc(s)) : - val ls = get-locations(loc(s)) - val loc* = - if length(ls) == 1 and guard(head(ls)) == one : loc(s) - else : - val temp = create-temp(loc(s)) - for x in ls do : - add(stmts,Conditionally(info(s),guard(x),Connect(info(s),base(x),temp),Empty())) - temp - Connect(info(s),loc*,remove-e(exp(s))) - else : - Connect(info(s),loc(s),remove-e(exp(s))) - (s) : map{remove-s,_} $ map(remove-e,s) - add(stmts,s*) - if length(stmts) != 1 : Begin(to-list(stmts)) - else : stmts[0] - - InModule(info(m),name(m),ports(m),remove-s(body(m))) - - Circuit(info(c),modules*, main(c)) where : - val modules* = - for m in modules(c) map : - match(m) : - (m:ExModule) : m - (m:InModule) : remove-m(m) - -;;================ EXPAND WHENS ============================= -; This pass does three things: remove last connect semantics, -; remove conditional blocks, and eliminate concept of scoping. - -public defstruct ExpandWhens <: Pass -public defmethod pass (b:ExpandWhens) -> (Circuit -> Circuit) : expand-whens -public defmethod name (b:ExpandWhens) -> String : "Expand Whens" -public defmethod short-name (b:ExpandWhens) -> String : "expand-whens" - -; ========== Expand When Utilz ========== - -defn get-entries (hash:HashTable<Expression,Expression>,exps:Streamable<Expression>) -> HashTable<Expression,Expression> : - val hash* = HashTable<Expression,Expression>(exp-hash) - for e in exps do : - val value = get?(hash,e,false) - match(value) : - (value:Expression) : hash*[e] = value - (value:False) : false - hash* -defn get-female-refs (n:Symbol,t:Type,g:Gender) -> List<Expression> : - val exps = create-exps(WRef(n,t,ExpKind(),g)) - val exps* = Vector<Expression>() - for i in 0 to length(exps) do : - switch { _ == get-gender(t,i,g)} : - BI-GENDER : add(exps*,exps[i]) - FEMALE : add(exps*,exps[i]) - else : false - to-list(exps*) -defn get-gender (t:Type, i:Int, g:Gender) -> Gender : - val f = get-flip(t,i,DEFAULT) - g * f -defn print-hash (h:HashTable<Expression,Expression>) : - for x in h do : - println(x) - -; ------------ Pass ------------------- -defn expand-whens (c:Circuit) -> Circuit : - defn void-all (m:InModule) -> InModule : - mname = name(m) - defn void-all-s (s:Stmt) -> Stmt : - match(s) : - (s:DefWire|DefRegister|WDefInstance|DefMemory) : - val voids = Vector<Stmt>() - for e in get-female-refs(name(s),get-type(s),get-gender(s)) do : - add(voids,Connect(info(s),e,WVoid())) - Begin(List(s,to-list(voids))) - (s) : map(void-all-s,s) - val voids = Vector<Stmt>() - for p in ports(m) do : - for e in get-female-refs(name(p),type(p),get-gender(p)) do : - add(voids,Connect(info(p),e,WVoid())) - val body* = void-all-s(body(m)) - InModule(info(m),name(m),ports(m),Begin(list(Begin(to-list(voids)),body*))) - - defn expand-whens (m:InModule) -> [HashTable<Expression,Expression> Vector<Stmt>] : - val simlist = Vector<Stmt>() - mname = name(m) - defn expand-whens (s:Stmt,netlist:HashTable<Expression,Expression>,p:Expression) -> Stmt : - match(s) : - (s:Connect) : netlist[loc(s)] = exp(s) - (s:IsInvalid) : netlist[exp(s)] = WInvalid() - (s:Conditionally) : - val exps = Vector<Expression>() - defn prefetch (s:Stmt) -> Stmt: - match(s) : - (s:Connect) : - add(exps,loc(s)) - s - (s) : map(prefetch,s) - prefetch(conseq(s)) - val c-netlist = get-entries(netlist,exps) - expand-whens(conseq(s),c-netlist,AND(p,pred(s))) - expand-whens(alt(s),netlist,AND(p,NOT(pred(s)))) - for lvalue in keys(c-netlist) do : - val value = get?(netlist,lvalue,false) - match(value) : - (value:Expression) : - val tv = c-netlist[lvalue] - val fv = value - val res = match(tv,fv) : - (tv:WInvalid,fv:WInvalid) : WInvalid() - (tv:WInvalid,fv) : ValidIf(NOT(pred(s)),fv,type(fv)) - (tv,fv:WInvalid) : ValidIf(pred(s),tv,type(tv)) - (tv,fv) : Mux(pred(s),tv,fv,mux-type-and-widths(tv,fv)) - netlist[lvalue] = res - (value:False) : - netlist[lvalue] = c-netlist[lvalue] - (s:Print) : - if p == one : add(simlist,s) - else : add(simlist,Print(info(s),string(s),args(s),clk(s),AND(p,en(s)))) - (s:Stop) : - if p == one : add(simlist,s) - else : add(simlist,Stop(info(s),ret(s),clk(s),AND(p,en(s)))) - (s) : map(expand-whens{_,netlist,p},s) - s - val netlist = HashTable<Expression,Expression>(exp-hash) - expand-whens(body(m),netlist,one) - - ;println("Netlist:") - ;println(netlist) - ;println("Simlist:") - ;println(simlist) - [ netlist simlist ] - - defn create-module (netlist:HashTable<Expression,Expression>,simlist:Vector<Stmt>,m:InModule) -> InModule : - mname = name(m) - val stmts = Vector<Stmt>() - val connections = Vector<Stmt>() - defn replace-void (e:Expression,rvalue:Expression) -> Expression : - match(rvalue) : - (rv:WVoid) : e - (rv) : map(replace-void{e,_},rv) - defn create (s:Stmt) -> Stmt : - match(s) : - (s:DefWire|DefRegister|WDefInstance|DefMemory) : - add(stmts,s) - for e in get-female-refs(name(s),get-type(s),get-gender(s)) do : - val rvalue = - if s typeof DefRegister : replace-void(e,netlist[e]) - else : netlist[e] - val con = match(rvalue) : - (rvalue:WInvalid) : IsInvalid(info(s),e) - (rvalue) : Connect(info(s),e,rvalue) - add(connections,con) - (s:DefPoison|DefNode) : - add(stmts,s) - (s) : map(create,s) - s - create(body(m)) - for p in ports(m) do : - for e in get-female-refs(name(p),type(p),get-gender(p)) do : - val rvalue = netlist[e] - val con = match(rvalue) : - (rvalue:WInvalid) : IsInvalid(info(p),e) - (rvalue) : Connect(info(p),e,rvalue) - add(connections,con) - for x in simlist do : - add(stmts,x) - InModule(info(m),name(m),ports(m),Begin(list(Begin(to-list(stmts)),Begin(to-list(connections))))) - - val voided-modules = - for m in modules(c) map : - match(m) : - (m:ExModule) : m - (m:InModule) : - val m* = void-all(m as InModule) - m* - val modules* = - for m in voided-modules map : - match(m) : - (m:ExModule) : m - (m:InModule) : - val [netlist simlist] = expand-whens(m) - create-module(netlist,simlist,m) - Circuit(info(c),modules*,main(c)) - -;;================ Module Duplication ================== -; Duplicates modules so that no module is instantiated -; more than once. - -;public defstruct ModuleDuplication <: Pass -;public defmethod pass (b:ModuleDuplication) -> (Circuit -> Circuit) : module-duplication -;public defmethod name (b:ModuleDuplication) -> String : "Module Duplication" -;public defmethod short-name (b:ModuleDuplication) -> String : "mod-dup" -; -;;------------ Helper Functions ------------- -; -;;------------ Pass ------------------ -; -;public defn module-duplication (c:Circuit) : -; val modules* = Vector<Module>() -; val m-names = HashTable<Symbol,Int>(symbol-hash) -; defn rename (n:Symbol) -> Symbol : -; val int = get?(m-names,n,0) -; m-names[n] = int + 1 -; val n* = symbol-join([n module-expand-delin int]) -; val m = for x in modules(c) find : name(x) == n -; match(m) : -; (m:InModule) : add(modules*,InModule(info(m),n*, ports(m), rename-s(body(m)))) -; (m:ExModule) : add(modules*,ExModule(info(m),n*, ports(m))) -; (m:False) : error("Shouldn't be here") -; n* -; -; defn rename-e (e:Expression) -> Expression : -; match(e) : -; (e:Ref) : Ref(rename(name(e)),type(e)) -; (e) : error("Shouldn't be here") -; defn rename-s (s:Stmt) -> Stmt : -; match(s) : -; (s:WDefInstance) : WDefInstance(info(s),name(s),rename-e(module(s))) -; (s) : map(rename-s,s) -; -; val top = for m in modules(c) find : name(m) == main(c) -; match(top) : -; (m:InModule) : add(modules*,InModule(info(m),name(m), ports(m), rename-s(body(m)))) -; (m:ExModule) : m -; (m:False) : error("Shouldn't be here") -; -; Circuit(info(c),to-list(modules*), main(c)) -; -; -;;;================ Deadcode Elimination =================== -;; Walks the circuit, starting from the outputs from the top -;; level module. All components that are not reached are -;; deleted -; -;public defstruct DeadcodeElimination <: Pass -;public defmethod pass (b:DeadcodeElimination) -> (Circuit -> Circuit) : deadcode-elimination -;public defmethod name (b:DeadcodeElimination) -> String : "Deadcode Elimination" -;public defmethod short-name (b:DeadcodeElimination) -> String : "deadcode-elim" -; -;;------------ Helper Functions ------------- -; -;;------------ Pass ------------------ -; -;public defn deadcode-elimination (c:Circuit) : c -; -;;;================ INFER WIDTHS ============================= -;; First, you replace all unknown widths with a unique width -;; variable. -;; Then, you collect all width constraints. -;; Then, you solve width constraints. -;; Finally, you replace all width variables with the solved -;; widths. -;; Low FIRRTL Pass. -public defstruct InferWidths <: Pass -public defmethod pass (b:InferWidths) -> (Circuit -> Circuit) : infer-widths -public defmethod name (b:InferWidths) -> String : "Infer Widths" -public defmethod short-name (b:InferWidths) -> String : "infer-widths" - -public definterface Constraint -public defstruct WGeq <: Constraint : - loc : Width - exp : Width -public defmethod print (o:OutputStream, c:WGeq) : - print-all(o,[ loc(c) " >= " exp(c)]) -defn apply (a:Int|False,b:Int|False, f: (Int,Int) -> Int) -> Int|False : - if a typeof Int and b typeof Int : f(a as Int, b as Int) - else : false - -defn solve-constraints (l:List<WGeq>) -> HashTable<Symbol,Width> : - defn contains? (n:Symbol,h:HashTable<Symbol,?>) -> True|False : key?(h,n) - defn make-unique (ls:List<WGeq>) -> HashTable<Symbol,Width> : - val h = HashTable<Symbol,Width>(symbol-hash) - for g in ls do : - match(loc(g)) : - (w:VarWidth) : - val n = name(w) - if contains?(n,h) : h[n] = MaxWidth(list(exp(g),h[n])) - else : h[n] = exp(g) - (w) : w - h - defn simplify (w:Width) -> Width : - match(map(simplify,w)) : - (w:MinWidth) : - val v = Vector<Width>() - for w* in args(w) do : - match(w*) : - (w*:MinWidth) : - for x in args(w*) do : add(v,x) - (w*) : add(v,w*) - MinWidth(unique(v)) - (w:MaxWidth) : - val v = Vector<Width>() - for w* in args(w) do : - match(w*) : - (w*:MaxWidth) : - for x in args(w*) do : add(v,x) - (w*) : add(v,w*) - MaxWidth(unique(v)) - (w:PlusWidth) : - match(arg1(w),arg2(w)) : - (w1:IntWidth,w2:IntWidth) : IntWidth(plus(width(w1),width(w2))) - (w1,w2) : w - (w:MinusWidth) : - match(arg1(w),arg2(w)) : - (w1:IntWidth,w2:IntWidth) : IntWidth(minus(width(w1),width(w2))) - (w1,w2) : w - (w:ExpWidth) : - match(arg1(w)) : - (w1:IntWidth) : IntWidth(pow(to-long(2),width(w1)) - to-long(1)) - (w1) : w - (w) : w - defn substitute (w:Width,h:HashTable<Symbol,Width>) -> Width : - ;println-all-debug(["Substituting for [" w "]"]) - val w* = simplify(w) - ;println-all-debug(["After Simplify: [" w* "]"]) - match(map(substitute{_,h},simplify(w))) : - (w:VarWidth) : - ;println-debug("matched varwidth!") - if contains?(name(w),h) : - ;println-debug("Contained!") - ;println-all-debug(["Width: " w]) - ;println-all-debug(["Accessed: " h[name(w)]]) - val t = simplify(substitute(h[name(w)],h)) - ;val t = h[name(w)] - ;println-all-debug(["Width after sub: " t]) - h[name(w)] = t - t - else : w - (w): - ;println-all-debug(["not varwidth!" w]) - w - defn b-sub (w:Width,h:HashTable<Symbol,Width>) -> Width: - match(map(b-sub{_,h},w)) : - (w:VarWidth) : - if key?(h,name(w)) : h[name(w)] - else : w - (w) : w - defn remove-cycle (n:Symbol,w:Width) -> Width : - ;println-all-debug(["Removing cycle for " n " inside " w]) - val w* = match(map(remove-cycle{n,_},w)) : - (w:MaxWidth) : MaxWidth(to-list(filter({_ != VarWidth(n)},args(w)))) - (w:MinusWidth) : - if arg1(w) == VarWidth(n) : arg1(w) - else : w - (w) : w - ;println-all-debug(["After removing cycle for " n ", returning " w*]) - w* - defn self-rec? (n:Symbol,w:Width) -> True|False : - var has? = false - defn look (w:Width) -> Width : - match(map(look,w)) : - (w:VarWidth) : if name(w) == n : has? = true - (w) : w - w - look(w) - has? - - ; Forward solve - ; Returns a solved list where each constraint undergoes: - ; 1) Continuous Solving (using triangular solving) - ; 2) Remove Cycles - ; 3) Move to solved if not self-recursive - val u = make-unique(l) - println-debug("======== UNIQUE CONSTRAINTS ========") - for x in u do : println-debug(x) - println-debug("====================================") - - val f = HashTable<Symbol,Width>(symbol-hash) - val o = Vector<Symbol>() - for x in u do : - println-debug("==== SOLUTIONS TABLE ====") - for x in f do : println-debug(x) - println-debug("=========================") - - val [n e] = [key(x) value(x)] - - val e-sub = substitute(e,f) - println-debug(["Solving " n " => " e]) - println-debug(["After Substitute: " n " => " e-sub]) - println-debug("==== SOLUTIONS TABLE (Post Substitute) ====") - for x in f do : println-debug(x) - println-debug("=========================") - val e* = remove-cycle{n,_} $ e-sub - ;println-debug(["After Remove Cycle: " n " => " e*]) - if not self-rec?(n,e*) : - ;println-all-debug(["Not rec!: " n " => " e*]) - ;println-all-debug(["Adding [" n "=>" e* "] to Solutions Table"]) - add(o,n) - f[n] = e* - - println-debug("Forward Solved Constraints") - for x in f do : println-debug(x) - - ; Backwards Solve - val b = HashTable<Symbol,Width>(symbol-hash) - for i in (length(o) - 1) through 0 by -1 do : - val n = o[i] - println-all-debug(["SOLVE BACK: [" n " => " f[n] "]"]) - println-debug("==== SOLUTIONS TABLE ====") - for x in b do : println-debug(x) - println-debug("=========================") - val e* = simplify(b-sub(f[n],b)) - println-all-debug(["BACK RETURN: [" n " => " e* "]"]) - b[n] = e* - println-debug("==== SOLUTIONS TABLE (Post backsolve) ====") - for x in b do : println-debug(x) - println-debug("=========================") - b - -public defn width! (t:Type) -> Width : - match(t) : - (t:UIntType) : width(t) - (t:SIntType) : width(t) - (t:ClockType) : IntWidth(1) - (t) : error("No width!") -public defn width! (e:Expression) -> Width : width!(type(e)) - -defn reduce-var-widths (c:Circuit,h:HashTable<Symbol,Width>) -> Circuit : - defn evaluate (w:Width) -> Width : - defn apply (a:Long|False,f:(Long) -> Long) -> Long|False : - if a typeof Long : f(a as Long) - else : false - defn apply (a:Long|False,b:Long|False, f: (Long,Long) -> Long) -> Long|False : - if a typeof Long and b typeof Long : f(a as Long, b as Long) - else : false - defn apply-l (l:List<Long|False>,f:(Long,Long) -> Long) -> Long|False : - if length(l) == 0 : to-long(0) - else : apply(head(l),apply-l(tail(l),f),f) - defn max (a:Long,b:Long) -> Long : - if a >= b : a - else : b - defn min (a:Long,b:Long) -> Long : - if a >= b : b - else : a - defn solve (w:Width) -> False|Long : - match(w) : - (w:VarWidth) : - val w* = get?(h,name(w),false) - match(w*) : - (w:VarWidth) : false - (w:False) : false - (w) : solve(w as Width) - (w:MaxWidth) : apply-l(map(solve,args(w)),max) - (w:MinWidth) : apply-l(map(solve,args(w)),min) - (w:PlusWidth) : apply(solve(arg1(w)),solve(arg2(w)),{plus(_,_)}) - (w:MinusWidth) : apply(solve(arg1(w)),solve(arg2(w)),{minus(_,_)}) - (w:ExpWidth) : apply(to-long(2),solve(arg1(w)),{minus(pow(_,_),to-long(1))}) - (w:IntWidth) : width(w) - (w) : - println(w) - error("Shouldn't be here") - - val s = solve(w) - match(s) : - (s:Long) : IntWidth(s) - (s) : w - - defn reduce-var-widths-w (w:Width) -> Width : - println-all-debug(["REPLACE: " w]) - val w* = evaluate(w) - println-all-debug(["WITH: " w*]) - w* - - val modules* = for m in modules(c) map : - val ports* = for p in ports(m) map : - Port(info(p),name(p),direction(p),mapr(reduce-var-widths-w,type(p))) - - match(m) : - (m:ExModule) : ExModule(info(m),name(m),ports*) - (m:InModule) : - mname = name(m) - InModule(info(m),name(m),ports*,mapr(reduce-var-widths-w,body(m))) - - Circuit(info(c),modules*,main(c)) - -defn infer-widths (c:Circuit) -> Circuit : - val v = Vector<WGeq>() - defn constrain (w1:Width,w2:Width) -> False : constrain(w1,w2,DEFAULT) - defn constrain (w1:Width,w2:Width,f:Flip) -> False : - switch { _ == f } : - DEFAULT : add(v,WGeq(w1,w2)) - REVERSE : add(v,WGeq(w2,w1)) - defn get-constraints (t1:Type,t2:Type,f:Flip) -> False : - match(t1,t2) : - (t1:UIntType,t2:UIntType) : constrain(width(t1),width(t2)) - (t1:SIntType,t2:SIntType) : constrain(width(t1),width(t2)) - (t1:BundleType,t2:BundleType) : - for (f1 in fields(t1),f2 in fields(t2)) do : - get-constraints(type(f1),type(f2),flip(f1) * f) - (t1:VectorType,t2:VectorType) : - get-constraints(type(t1),type(t2),f) - defn get-constraints-e (e:Expression) -> Expression : - match(map(get-constraints-e,e)) : - (e:Mux) : - constrain(width!(cond(e)),ONE) - constrain(ONE,width!(cond(e))) - e - (e) : e - defn get-constraints (s:Stmt) -> Stmt : - match(map(get-constraints-e,s)) : - (s:Connect) : - ;constrain(width!(loc(s)),width!(exp(s))) - ;s - val n = get-size(loc(s)) - val ce-loc = create-exps(loc(s)) - val ce-exp = create-exps(exp(s)) - for i in 0 to n do : - val loc* = ce-loc[i] - val exp* = ce-exp[i] - switch { _ == get-flip(type(loc(s)),i,DEFAULT) } : - DEFAULT : constrain(width!(loc*),width!(exp*)) - REVERSE : constrain(width!(exp*),width!(loc*)) - s - (s:BulkConnect) : - val ls = get-valid-points(type(loc(s)),type(exp(s)),DEFAULT,DEFAULT) - for x in ls do : - ;println(x) - ;println(create-exps(loc(s))) - ;println(create-exps(exp(s))) - val loc* = create-exps(loc(s))[x[0]] - val exp* = create-exps(exp(s))[x[1]] - switch { _ == get-flip(type(loc(s)),x[0],DEFAULT) } : - DEFAULT : constrain(width!(loc*),width!(exp*)) - REVERSE : constrain(width!(exp*),width!(loc*)) - s - (s:DefRegister) : - constrain(width!(reset(s)),ONE) - constrain(ONE,width!(reset(s))) - get-constraints(type(s),type(init(s)),DEFAULT) - s - (s:Conditionally) : - add(v,WGeq(width!(pred(s)),ONE)) - add(v,WGeq(ONE,width!(pred(s)))) - map(get-constraints,s) - (s) : map(get-constraints,s) - - for m in modules(c) do : - match(m) : - (m:InModule) : - mname = name(m) - get-constraints(body(m)) - (m) : false - println-debug("======== ALL CONSTRAINTS ========") - for x in v do : println-debug(x) - println-debug("=================================") - val h = solve-constraints(to-list(v)) - println-debug("======== SOLVED CONSTRAINTS ========") - for x in h do : println-debug(x) - println-debug("====================================") - reduce-var-widths(Circuit(info(c),modules(c),main(c)),h) - -; ================ All Resolving Passes ================ -public defstruct Resolve <: Pass -public defmethod pass (b:Resolve) -> (Circuit -> Circuit) : resolve -public defmethod name (b:Resolve) -> String : "Resolve" -public defmethod short-name (b:Resolve) -> String : "resolve" - -defn resolve (c:Circuit) -> Circuit : - check-width $ - infer-widths $ - check-genders $ - resolve-genders $ - check-types $ - infer-types $ - resolve-kinds $ - to-working-ir(c) - -;;================= Inline Instances ======================== -;; Inlines instances. Assumes module with same name as the -;; Circuit is the top level module -;public defstruct Inline <: Pass -;public defmethod pass (b:Inline) -> (Circuit -> Circuit) : inline-instances -;public defmethod name (b:Inline) -> String : "Inline Instances" -;public defmethod short-name (b:Inline) -> String : "inline-instances" -; -;defn inline-instances (c:Circuit) : -; val h = HashTable<Symbol,InModule>(symbol-hash) -; val h-s = HashTable<Symbol,Stmt>(symbol-hash) -; defn inline-inst (s:Stmt) -> Stmt : -; match(map(inline-inst,s)) : -; (s:WDefInstance) : -; val n = name(module(s) as WRef) -; val m = h[n] -; val body* = -; if key?(h-s,n) : h-s[n] -; else : -; val v = Vector<Stmt>() -; for p in ports(m) do : -; add(v,DefWire(info(s),name(p),type(p))) -; add(v,inline-inst(body(m))) -; Begin(to-list(v)) -; h-s[n] = body* -; rename-s(body*,name(s)) -; (s) : map(inline-inst-e,s) -; defn inline-inst-e (e:Expression) -> Expression : -; match(map(inline-inst-e,e)) : -; (e:WSubField) : -; match(kind(exp(e) as WRef)) : -; (k:InstanceKind) : -; WRef(symbol-join([name(exp(e) as WRef) inline-delin name(e)]),type(e),k,gender(e)) -; (k:MemKind) : e -; (e) : e -; defn rename (ref:Symbol,n:Symbol) -> Symbol : symbol-join([n inline-delin ref]) -; defn rename-e (e:Expression,n:Symbol) -> Expression : -; match(map(rename-e{_,n},e)) : -; (e:WRef) : WRef(rename(name(e),n),type(e),kind(e),gender(e)) -; (e:WSubField) : -; match(kind(exp(e) as WRef)) : -; (k:InstanceKind) : -; WRef(symbol-join([name(exp(e) as WRef) inline-delin name(e)]),type(e),k,gender(e)) -; (k:MemKind) : e -; (e) : e -; defn rename-s (s:Stmt,n:Symbol) -> Stmt : -; map{rename-e{_,n},_} $ match(map(rename-s{_,n},s)) : -; (s:DefWire) : DefWire(info(s),rename(name(s),n),type(s)) -; (s:DefPoison) : DefPoison(info(s),rename(name(s),n),type(s)) -; (s:DefRegister) : DefRegister(info(s),rename(name(s),n),type(s),clock(s),reset(s)) -; (s:WDefInstance) : error("Shouldn't be here") -; (s:DefMemory) : DefMemory(info(s),rename(name(s),n),type(s),seq?(s),clock(s),size(s)) -; (s:DefNode) : DefNode(info(s),rename(name(s),n),value(s)) -; (s) : s -; for m in modules(c) do : -; match(m) : -; (m:ExModule) : error("Cannot inline with external modules") -; (m:InModule) : h[name(m)] = m -; val top = (for m in modules(c) find : name(m) == main(c)) as InModule -; Circuit(info(c),list(InModule(info(top),name(top),ports(top),inline-inst(body(top)))),main(c)) - -;;================= Verilog Wrap ======================== - -; --------- Utils -------------- - -;---------- Pass --------------- -;; Intended to only work on low firrtl -public defstruct VerilogWrap <: Pass -public defmethod pass (b:VerilogWrap) -> (Circuit -> Circuit) : v-wrap -public defmethod name (b:VerilogWrap) -> String : "Verilog Wrap" -public defmethod short-name (b:VerilogWrap) -> String : "verilog-wrap" - -public definterface WPrimOp <: PrimOp -val ADDW-OP = new WPrimOp -val SUBW-OP = new WPrimOp - -defmethod print (o:OutputStream,op:WPrimOp) : - print{o, _} $ switch {op == _} : - ADDW-OP : "addw" - SUBW-OP : "subw" - -defn v-wrap-e (e:Expression) -> Expression : - match(map(v-wrap-e,e)) : - (e:DoPrim) : - defn a0 () : args(e)[0] - if op(e) == TAIL-OP : - match(a0()) : - (e0:DoPrim) : - if op(e0) == ADD-OP : - DoPrim(ADDW-OP,args(e0),list(),type(e)) - else if op(e0) == SUB-OP : - DoPrim(SUBW-OP,args(e0),list(),type(e)) - else : e - (e0) : e - else : e - (e) : e -defn v-wrap-s (s:Stmt) -> Stmt : - map{v-wrap-e,_} $ map(v-wrap-s,s) -defn v-wrap (c:Circuit) -> Circuit : - val modules* = for m in modules(c) map : - match(m) : - (m:InModule) : - mname = name(m) - InModule(info(m),name(m),ports(m),v-wrap-s(body(m))) - (m:ExModule) : m - Circuit(info(c),modules*,main(c)) - -;;================= Split Expressions ======================== - -;; Intended to only work on low firrtl -public defstruct SplitExp <: Pass -public defmethod pass (b:SplitExp) -> (Circuit -> Circuit) : split-exp -public defmethod name (b:SplitExp) -> String : "Split Expressions" -public defmethod short-name (b:SplitExp) -> String : "split-expressions" - -defn split-exp (m:InModule) -> InModule : - mname = name(m) - val v = Vector<Stmt>() - val sh = get-sym-hash(m,keys(v-keywords)) - defn split-exp-s (s:Stmt) -> Stmt : - val base = match(s) : - (s:Connect) : lowered-name(loc(s)) - (s:DefNode) : name(s) - (s:DefRegister) : name(s) - (s) : `F - defn split (e:Expression) -> Expression : - val n = firrtl-gensym(`GEN,sh) - add(v,DefNode(info(s),n,e)) - WRef(n,type(e),kind(e),gender(e)) - defn split-exp-e (e:Expression,i:Int) -> Expression : - match(map(split-exp-e{_,i + 1},e)) : - (e:DoPrim) : - if i > 0 : split(e) - else : e - (e) : e - match(s) : - (s:Begin) : map(split-exp-s,s) - (s:Print) : - val s* = map(split-exp-e{_,1},s) - add(v,s*) - s* - (s) : - val s* = map(split-exp-e{_,0},s) - add(v,s*) - s* - split-exp-s(body(m)) - InModule(info(m),name(m),ports(m),Begin(to-list(v))) - -defn split-exp (c:Circuit) -> Circuit : - val modules* = for m in modules(c) map : - match(m) : - (m:InModule) : split-exp(m) - (m:ExModule) : m - Circuit(info(c),modules*,main(c)) - - -;;================= Special Rename ======================== -;; Returns a new Circuit with only real IR nodes. -;public defstruct SpecialRename <: Pass : -; original-sym : Symbol -; new-sym : Symbol -;public defmethod pass (b:SpecialRename) -> (Circuit -> Circuit) : special-rename{original-sym(b),new-sym(b),_:Circuit} -;public defmethod name (b:SpecialRename) -> String : "Special Rename" -;public defmethod short-name (b:SpecialRename) -> String : "special-rename" -; -;public defn special-rename (original-sym:Symbol,new-sym:Symbol,c:Circuit) : -; defn rename (s:Symbol) -> Symbol : -; val y = Vector<String>() -; val os = to-string $ original-sym -; val ns = to-string $ new-sym -; defn rename (st:String) -> False : -; if st == os : -; add(y,ns) -; else if length(st) <= length(os) : -; add(y,st) -; else : -; if substring(st,0,length(os)) == os : -; add(y,ns) -; ;println(st) -; ;println(substring(st,length(os),length(st))) -; rename(substring(st,length(os),length(st))) -; else : -; add(y,substring(st,0,1)) -; rename(substring(st,1,length(st))) -; rename(to-string(s)) -; to-symbol $ string-join $ to-list(y) -; defn to-type (t:Type) -> Type : -; match(map(to-type,t)) : -; (t:BundleType) : BundleType $ -; for f in fields(t) map : Field(rename(name(f)),flip(f),type(f)) -; (t) : t -; defn to-exp (e:Expression) -> Expression : -; map{to-type,_} $ match(map(to-exp,e)) : -; (e:Ref) : Ref(rename(name(e)), type(e)) -; (e:Subfield) : Subfield(exp(e),rename(name(e)),type(e)) -; (e) : e -; defn to-stmt (s:Stmt) -> Stmt : -; map{to-type,_} $ match(map(to-exp,s)) : -; (s:DefWire) : DefWire(info(s),rename(name(s)),type(s)) -; (s:DefPoison) : DefPoison(info(s),rename(name(s)),type(s)) -; (s:DefRegister) : DefRegister(info(s),rename(name(s)),type(s),clock(s),reset(s)) -; (s:WDefInstance) : WDefInstance(info(s),rename(name(s)),module(s)) -; (s:DefMemory) : DefMemory(info(s),rename(name(s)),type(s),seq?(s),clock(s),size(s)) -; (s:DefNode) : DefNode(info(s),rename(name(s)),value(s)) -; (s:DefAccessor) : DefAccessor(info(s),rename(name(s)),source(s),index(s),acc-dir(s)) -; (s) : map(to-stmt,s) -; -; defn to-port (p:Port) -> Port : Port(info(p),rename(name(p)),direction(p),type(p)) -; -; Circuit(info(c),modules*, main(c)) where : -; val modules* = -; for m in modules(c) map : -; match(m) : -; (m:InModule) : InModule(info(m),name(m), map(to-port,ports(m)), to-stmt(body(m))) -; (m:ExModule) : m -; -; -;;========== Pad Widths ================== -; -;public defstruct Pad <: Pass -;public defmethod pass (b:Pad) -> (Circuit -> Circuit) : pad-widths -;public defmethod name (b:Pad) -> String : "Pad Widths" -; -;;------------ Helper Functions -------------- -;defn int-width! (t:Type) -> Long : -; match(width!(t)) : -; (w:IntWidth) : width(w) -; (w) : error("Non-int width") -; -;defn set-width (desired:Long,t:Type) -> Type : -; match(t) : -; (t:UIntType) : UIntType(IntWidth(desired)) -; (t:SIntType) : SIntType(IntWidth(desired)) -; (t) : error("Non-ground type") -; -;defn lmax (l1:Long, l2:Long) -> Long : -; if l1 > l2 : l1 -; else : l2 -; -;;------------- Pad Widths ------------------- -; -;defn pad-widths-e (desired:Long,e:Expression) -> Expression : -; defn trim (desired:Long, e:Expression) : -; ;; println-all(["TRIM " desired " e " e]) -; DoPrim(BITS-SELECT-OP,list(e),list(to-int(to-string(desired)) - 1, 0),set-width(desired,type(e))) -; defn pad (desired:Long, e:Expression) : -; ;; println-all(["PAD " desired " e " e]) -; DoPrim(PAD-OP,list(e),list(to-int $ to-string(desired)),set-width(desired,type(e))) -; defn trim-pad (desired:Long, e:Expression) : -; val i = int-width!(type(e)) -; if i > desired : trim(desired, e) -; else if i == desired : e -; else : pad(desired, e) -; defn self-pad-widths-e (e:Expression) -> Expression : -; pad-widths-e(int-width!(type(e)), e) -; ;; println-all(["PAD-E " desired " " e]) -; match(e) : -; (e:DoPrim) : -; val new-desired = reduce(lmax, to-long(0), map(int-width!{type(_)}, args(e))) -; ;; println-all([" NEW DESIRED " new-desired]) -; val e* = -; if contains?([CONCAT-OP, DYN-SHIFT-RIGHT-OP, DYN-SHIFT-LEFT-OP], op(e)) : -; DoPrim(op(e), map(self-pad-widths-e, args(e)), consts(e), type(e)) -; else if contains?([MUX-OP], op(e)) : -; DoPrim(op(e), list(pad-widths-e(to-long(1), args(e)[0]), pad-widths-e(new-desired, args(e)[1]), pad-widths-e(new-desired, args(e)[2])), consts(e), type(e)) -; else : -; map(pad-widths-e{new-desired,_},e) -; trim-pad(desired, e*) -; (e:Ref|Subfield|Index) : -; trim-pad(desired, e) -; (e:UIntValue) : -; val i = int-width!(type(e)) -; if i > desired : trim(desired, e) -; else : UIntValue(value(e),IntWidth(desired)) -; (e:SIntValue) : -; val i = int-width!(type(e)) -; if i > desired : trim(desired, e) -; else : SIntValue(value(e),IntWidth(desired)) -; (e) : error(to-string $ e) -; -;defn pad-widths-s (s:Stmt) -> Stmt : -; ;; println-all(["PAD-S " s]) -; match(map(pad-widths-s,s)) : -; (s:Connect) : -; val i = int-width!(type(loc(s))) -; val loc* = pad-widths-e(i,loc(s)) -; val exp* = pad-widths-e(i,exp(s)) -; Connect(info(s),loc*,exp*) -; (s:PrintfStmt) : -; val args* = for x in args(s) map : -; val i = int-width!(type(x)) -; pad-widths-e(i,x) -; PrintfStmt(info(s),string(s),args*) -; (s:DefNode) : -; val i = int-width!(type(value(s))) -; val exp* = pad-widths-e(i,value(s)) -; DefNode(info(s),name(s),exp*) -; (s:Conditionally) : -; val i = int-width!(type(pred(s))) -; val pred* = pad-widths-e(i,pred(s)) -; Conditionally(info(s),pred*,conseq(s),alt(s)) -; (s) : s -; -;public defn pad-widths (c:Circuit) -> Circuit : -; Circuit{info(c),_,main(c)} $ -; for m in modules(c) map : -; match(m) : -; (m:ExModule) : m -; (m:InModule) : InModule(info(m),name(m),ports(m),pad-widths-s(body(m))) -; -; - -;============== Common Subexpression Elimination =========== -;NOT DONE - -;public defstruct CSE <: Pass -;public defmethod pass (b:CSE) -> (Circuit -> Circuit) : const-prop -;public defmethod name (b:CSE) -> String : "Common Subexpression Elimination" -;public defmethod short-name (b:ConstProp) -> String : "cse" -; -;defn cse-m (m:InModule) -> InModule : -; val cse-hash = HashTable<Expression,Int>(exp-hash) -; val placed? = HashTable<Expression,True|False>(exp-hash) -; -; defn cse-s (s:Stmt) -> Stmt : -; val stmts = Vector<Stmt>() -; defn cse-e (e:Expression) -> Expression -; match(s) : -; -; defn build-e (e:Expression) -> Expression : -; match(e) : -; (e:DoPrim) : -; if key?(cse-hash,e) : -; cse-hash[e] = cse-hash[e] + 1 -; else : -; cse-hash[e] = 1 -; placed?[e] = false -; (e) : e -; defn build-s (s:Stmt) -> Stmt : map{build-s,_} $ map(build-e,s) -; -; build-s(body(m)) -; InModule(info(m),name(m),ports(m),cse-s(body(m))) -; -;public defn cse (c:Circuit) -> Circuit : -; Circuit{info(c),_,main(c)} $ -; for m in modules(c) map : -; match(m) : -; (m:ExModule) : m -; (m:InModule) : cse-m(m) - - - -;;============= Constant Propagation ================ -; -public defstruct ConstProp <: Pass -public defmethod pass (b:ConstProp) -> (Circuit -> Circuit) : const-prop -public defmethod name (b:ConstProp) -> String : "Constant Propagation" -public defmethod short-name (b:ConstProp) -> String : "const-prop" - -defn const-prop-e (e:Expression) -> Expression : - match(map(const-prop-e,e)) : - (e:DoPrim) : - switch {op(e) == _} : - ;DYN-SHIFT-RIGHT-OP : - ; match(args(e)[1]) : - ; (x:UIntValue|SIntValue) : - ; DoPrim(SHIFT-RIGHT-OP,list(args(e)[0]),list(to-int(value(x))),UnknownType()) - ; (x) : e - ;DYN-SHIFT-LEFT-OP : - ; match(args(e)[1]) : - ; (x:UIntValue|SIntValue) : - ; DoPrim(SHIFT-LEFT-OP,list(args(e)[0]),list(to-int(value(x))),UnknownType()) - ; (x) : e - SHIFT-RIGHT-OP : - match(args(e)[0]) : - (x:UIntValue) : - val b = rsh(value(x),consts(e)[0]) - UIntValue(b,width(type(e) as UIntType)) - (x:SIntValue) : - val b = rsh(value(x),consts(e)[0]) - SIntValue(b,width(type(e) as SIntType)) - (x) : e - BITS-SELECT-OP : - match(args(e)[0]) : - (x:UIntValue) : - val b = bits(value(x),consts(e)[0] + 1,consts(e)[1]) - UIntValue(b,width(type(e) as UIntType)) - (x) : - if long!(type(e)) == long!(type(x)) : - if type(x) typeof UIntType : x - else : DoPrim(AS-UINT-OP,list(x),list(),type(e)) - else : e - else : e - (e) : e - -defn const-prop-s (s:Stmt) -> Stmt : - map{const-prop-e,_} $ map(const-prop-s,s) - -public defn const-prop (c:Circuit) -> Circuit : - Circuit{info(c),_,main(c)} $ - for m in modules(c) map : - match(m) : - (m:ExModule) : m - (m:InModule) : - mname = name(m) - InModule(info(m),name(m),ports(m),const-prop-s(body(m))) - -;============= Condense Mems ================ -; -;public defstruct CondenseMems <: Pass -;public defmethod pass (b:CondenseMems) -> (Circuit -> Circuit) : condense-mems -;public defmethod name (b:CondenseMems) -> String : "Condense Mems" -;public defmethod short-name (b:CondenseMems) -> String : "condense-mems" -; -;;------------- Utils --------------- -; -;defn concat (es:List<Expression>) -> Expression : -; if length(es) == 1 : head(es) -; else : CAT(head(es),cat(tail(es))) -;defn cast (t:Type,e:Expression) -> Expression : -; match(t) : -; (t:UIntType) : e -; (t:SIntType) : DoPrim(AS-SINT-OP,list(e),list(),SIntType(get-width(t))) -;defn get-width-index (e:Expression) -> Long : -; match(e) : -; (e:WRef) : 0 -; (e:WSubField) : -; var w = get-width-index(exp(e)) -; var found? = false -; for f in fields(type(exp(e)) as BundleType) do : -; if name(f) == name(e) : -; found? = true -; if found? == false : -; w = w + get-width(type(f)) -; w -; (e:WSubIndex) : -; get-width-index(exp(e)) + get-width(type(e)) * value(e) -;defn root-ref (e:Expression) -> Expression : -; match(e) : -; (e:WRef) : e -; (e:WSubField|WSubIndex) : root-ref(e) -;defn flatten (e:Expression) -> Expression : -; match(e) : -; (e:WRef) : e -; (e:WSubField|WSubIndex) : -; val base = get-width-index(e) -; val off = get-width(type(e)) -; DoPrim(BITS-SELECT-OP,list(root-ref(e)),list(base,off),UIntType(IntWidth(off))) -; -;;------------- Pass ------------------ - -;defn condense-mems (m:InModule) -> InModule : -; val mem-assigns = HashTable<Expression,Expression>(exp-hash) -; defn collect-mems (s:Stmt) -> Stmt : -; match(s) : -; (s:Connect) : -; defn condense-mems-e (e:Expression) -> Expression : -; val e* = match(e) : -; (e:WRef|WSubField|WSubIndex) : -; if (kind(e) typeof MemKind) : cast(type(e),flatten(e)) -; else : e -; (e:UIntValue|SIntValue) : e -; (e:DoPrim) : map(condense-mems-e,e) -; defn condense-mems (s:Stmt) -> Stmt : -; match(s) : -; (s:DefMemory) : -; val stmts = Vector<Stmt>() -; val s* = map(flatten,s) -; add(stmts,s*) -; val mem = WRef(name(s),type(s),MemKind(),UNKNOWN-GENDER) -; for f in fields(type(s) as BundleType) do : -; val data-name = -; if contains?(writers(s),name(f)) : `data -; else if contains(readwriters(s),name(f)) : `wdata -; else : false -; match(data-name) : -; (f:False) : false -; (n:Symbol) : -; val port = WSubField(mem,name(f),type(f),UNKNOWN-GENDER) -; val es = create-exps(WSubField(port,n,field-type(type(port),n),UNKNOWN-GENDER)) -; val e* = concat $ for e in es map : -; map(condense-mems-e,mem-assigns[e]) -; add(stmts,Connect(info(s),WSubField(port,n,data-type(s*),UNKNOWN-GENDER),e*)) -; Begin(to-list(stmts)) -; (s:Connect) : -; if kind(loc(s)) typeof MemKind : EmptyStmt() -; else : map(condense-mems-e, s) -; (s) : map{condense-mems,_} $ map(condense-mems-e, s) -; InModule(info(m),name(m),ports(m),condense-mems(body(m))) -; -;defn condense-mems (c:Circuit) -> Circuit : -; Circuit{info(c),_,main(c)} $ -; for m in modules(c) map : -; match(m) : -; (m:ExModule) : m -; (m:InModule) : condense-mems(m) - - -;============= Lower Types ================ -; -public defstruct LowerTypes <: Pass -public defmethod pass (b:LowerTypes) -> (Circuit -> Circuit) : lower-types -public defmethod name (b:LowerTypes) -> String : "Lower Types" -public defmethod short-name (b:LowerTypes) -> String : "lower-types" - -;------------- Utils --------------- -defn is-ground? (t:Type) -> True|False : - match(t) : - (t:UIntType|SIntType) : true - (t) : false -defn data? (ex:Expression) -> True|False : - match(kind(ex)) : - (k:MemKind) : match(ex) : - (ex:WRef|WSubIndex) : false - (ex:WSubField) : - var yes? = switch { _ == name(ex) } : - `rdata : true - `data : true - `mask : true - else : false - yes? and match(exp(ex)) : - (e:WSubField) : - contains?(ports(kind(e) as MemKind),name(e)) and (exp(e) typeof WRef) - (e) : false - (ex) : false - (k) : false - -defn expand-name (e:Expression) -> List<Symbol> : - val names = Vector<Symbol>() - defn expand-name-e (e:Expression) -> Expression : - match(map(expand-name-e,e)) : - (e:WRef) : add(names,name(e)) - (e:WSubField) : add(names,name(e)) - (e:WSubIndex) : add(names,to-symbol(value(e))) - e - expand-name-e(e) - to-list(names) - - -defn lower-other-mem (e:Expression, dt:Type) -> List<Expression> : - val names = expand-name(e) - if length(names) < 3 : error("Shouldn't be here") - for x in create-exps(names[0],dt) map : - var base = lowered-name(x) - for (x in names,i in 0 to false) do : - if i >= 3 : base = symbol-join([base `_ x]) - val m = WRef(base, UnknownType(), kind(e), UNKNOWN-GENDER) - val p = WSubField(m,to-symbol(names[1]),UnknownType(),UNKNOWN-GENDER) - WSubField(p,to-symbol(names[2]),UnknownType(),UNKNOWN-GENDER) - -defn lower-data-mem (e:Expression) -> Expression : - val names = expand-name(e) - if length(names) < 3 : error("Shouldn't be here") - else : - var base = names[0] - for (x in names,i in 0 to false) do : - if i >= 3 : base = symbol-join([base `_ x]) - val m = WRef(base, UnknownType(), kind(e), UNKNOWN-GENDER) - val p = WSubField(m,to-symbol(names[1]),UnknownType(),UNKNOWN-GENDER) - WSubField(p,to-symbol(names[2]),UnknownType(),UNKNOWN-GENDER) - -defn merge (a:Symbol,b:Symbol,x:Symbol) -> Symbol : symbol-join([a x b]) -val hashed-lowered-name = HashTable<Expression,Symbol>(gexp-hash) -defn fast-lowered-name (e:Expression) -> Symbol : - val x = get?(hashed-lowered-name,e,false) - match(x) : - (x:Symbol) : x - (x:False) : - match(e) : - (e:WRef) : name(e) - (e:WSubField) : merge(fast-lowered-name(exp(e)),name(e),`_) - (e:WSubIndex) : merge(fast-lowered-name(exp(e)),to-symbol(value(e)),`_) -defn lowered-name (e:Expression) -> Symbol : - match(e) : - (e:WRef) : name(e) - (e:WSubField) : merge(lowered-name(exp(e)),name(e),`_) - (e:WSubIndex) : merge(lowered-name(exp(e)),to-symbol(value(e)),`_) -defn root-ref (e:Expression) -> WRef : - match(e) : - (e:WRef) : e - (e:WSubField|WSubIndex|WSubAccess) : root-ref(exp(e)) - -;------------- Pass ------------------ - -defn lower-types (m:Module) -> Module : - val mdt = HashTable<Symbol,Type>(symbol-hash) - mname = name(m) - defn lower-types (s:Stmt) -> Stmt : - defn lower-mem (e:Expression) -> List<Expression> : - val names = expand-name(e) - if contains?([`data `mask `rdata],names[2]) : - list(lower-data-mem(e)) - else : - lower-other-mem(e,mdt[name(root-ref(e))]) - defn lower-types-e (e:Expression) -> Expression : - match(e) : - (e:WRef|UIntValue|SIntValue) : e - (e:WSubField|WSubIndex) : - match(kind(e)) : - (k:InstanceKind) : - val names = expand-name(e) - var n = names[1] - for (x in names,i in 0 to false) do : - if i > 1 : n = symbol-join([n `_ x]) - WSubField(root-ref(e),n,type(e),gender(e)) - (k:MemKind) : - if not gender(e) == FEMALE : - lower-mem(e)[0] - else : e - (k) : WRef(lowered-name(e),type(e),kind(e),gender(e)) - (e:DoPrim) : map(lower-types-e,e) - (e:Mux) : map(lower-types-e,e) - (e:ValidIf) : map(lower-types-e,e) - match(s) : - (s:DefWire|DefPoison) : - if is-ground?(type(s)) : s - else : - val es = create-exps(name(s),type(s)) - Begin $ for (e in es, i in 0 to false) map : - defn replace-type (t:Type) -> Type : type(e) - defn replace-name (n:Symbol) -> Symbol : lowered-name(e) - map{replace-name,_} $ map(replace-type,s) - (s:DefRegister) : - if is-ground?(type(s)) : s - else : - val es = create-exps(name(s),type(s)) - Begin $ for (e in es, i in 0 to false) map : - val init = lower-types-e(create-exps(init(s))[i]) - DefRegister(info(s),lowered-name(e),type(e),clock(s),reset(s),init) - (s:WDefInstance) : - val fields* = for f in fields(type(s) as BundleType) map-append : - val es = create-exps(WRef(name(f),type(f),ExpKind(),flip(f) * MALE)) - for e in es map : - switch { _ == gender(e) } : - MALE : Field(lowered-name(e),DEFAULT,type(f)) - FEMALE : Field(lowered-name(e),REVERSE,type(f)) - WDefInstance(info(s),name(s),module(s),BundleType(fields*)) - (s:DefMemory) : - mdt[name(s)] = data-type(s) - if is-ground?(data-type(s)) : s - else : - val es = create-exps(name(s),data-type(s)) - Begin $ for e in es map : - DefMemory(info(s),lowered-name(e),type(e),depth(s),write-latency(s),read-latency(s),readers(s),writers(s),readwriters(s)) - (s:IsInvalid) : - val s* = map(lower-types-e,s) - if kind(exp(s*)) typeof MemKind : - val es = lower-mem(exp(s*)) - Begin $ for e in es map : - IsInvalid(info(s*),e) - else : s* - (s:Connect) : - val s* = map(lower-types-e,s) - if kind(loc(s*)) typeof MemKind : - val es = lower-mem(loc(s*)) - Begin $ for e in es map : - Connect(info(s*),e,exp(s*)) - else : s* - (s:DefNode) : - val locs = create-exps(name(s),type(value(s))) - val n = length(locs) - val nodes = Vector<Stmt>() - val exps = create-exps(value(s)) - for i in 0 to n do : - val loc* = locs[i] - val exp* = exps[i] - add(nodes,DefNode(info(s),lowered-name(loc*),lower-types-e(exp*))) - if n == 1 : nodes[0] - else : Begin(to-list(nodes)) - (s) : map(lower-types-e,map(lower-types,s)) - - val ports* = for p in ports(m) map-append : - val es = create-exps(WRef(name(p),type(p),PortKind(),to-gender(direction(p)))) - for e in es map : - Port(info(p),lowered-name(e),to-dir(gender(e)),type(e)) - match(m) : - (m:ExModule) : ExModule(info(m),name(m),ports*) - (m:InModule) : InModule(info(m),name(m),ports*,lower-types(body(m))) - -defn lower-types (c:Circuit) -> Circuit : - Circuit{info(c),_,main(c)} $ - for m in modules(c) map : lower-types(m) - - - -;============ RENAME VERILOG KEYWORDS ============= - -public defstruct VerilogRename <: Pass -public defmethod pass (b:VerilogRename) -> (Circuit -> Circuit) : verilog-rename -public defmethod name (b:VerilogRename) -> String : "Verilog Rename" -public defmethod short-name (b:VerilogRename) -> String : "verilog-rename" - -defn verilog-rename (c:Circuit) -> Circuit : - defn verilog-rename-n (n:Symbol) -> Symbol : - if key?(v-keywords,n) : symbol-join([n `$]) - else : n - defn verilog-rename-e (e:Expression) -> Expression : - match(e) : - (e:WRef) : WRef(verilog-rename-n(name(e)),type(e),kind(e),gender(e)) - (e) : map(verilog-rename-e,e) - defn verilog-rename-s (s:Stmt) -> Stmt : - map{verilog-rename-n,_} $ - map{verilog-rename-e,_} $ - map(verilog-rename-s,s) - - Circuit{info(c),_,main(c)} $ - for m in modules(c) map : - val ports* = for p in ports(m) map : - Port(info(p),verilog-rename-n(name(p)),direction(p),type(p)) - match(m) : - (m:InModule) : InModule(info(m),name(m),ports*,verilog-rename-s(body(m))) - (m:ExModule) : m - -;============ VERILOG ============== - -public defstruct Verilog <: Pass : - with-output: (() -> False) -> False -public defmethod pass (b:Verilog) -> (Circuit -> Circuit) : emit-verilog{with-output(b),_} -public defmethod name (b:Verilog) -> String : "To Verilog" -public defmethod short-name (b:Verilog) -> String : "to-verilog" - -;============ Utilz ============= -defstruct VIndent -defstruct VRandom -val tab = " " -val ran = VRandom() -defn wref (n:Symbol,t:Type) : WRef(n,t,ExpKind(),UNKNOWN-GENDER) -defn escape (s:String) -> String : - val s* = Vector<String>() - add(s*,"\"");" - var percent = false - for c in s do : - if c == '\n' : - add(s*,"\\n") - else if c == '"' : - add(s*, "\\\"") - else : - if c == 'x' and percent : - add(s*,"h") - else : add(s*,to-string(c)) - percent = c == '%' - add(s*,"\"");" - string-join(s*) -defn remove-root (ex:Expression) -> Expression : - match(exp(ex as WSubField)) : - (e:WSubField) : remove-root(e) - (e:WRef) : WRef(name(ex as WSubField),type(ex),InstanceKind(),UNKNOWN-GENDER) -defn !empty? (s:Vector) -> True|False : - if length(s) == 0 : false - else : true -defn long! (t:Type) -> Long : - match(t) : - (t:UIntType|SIntType) : width(width(t) as IntWidth) - (t:BundleType) : - var w = to-long(0) - for f in fields(t) do : - w = w + long!(type(f)) - w - (t:VectorType) : to-long(size(t)) * long!(type(t)) - (t:ClockType) : to-long(1) - -defn rand-string (t:Type) -> Streamable : - val w* = ((long!(t) + to-long(31)) / to-long(32)) - ["{" w* "{" ran "}}"] -defn emit (x:?) : emit(x,0) -defn emit (x:?, top:Int) : - defn cast (e:Expression) -> ? : - match(type(e)) : - (t:UIntType) : e - (t:SIntType) : ["$signed(" e ")"] - match(x) : - (e:Expression) : - turn-off-debug(false) - match(e) : - (e:DoPrim) : emit(op-stream(e), top + 1) - (e:Mux) : emit([cond(e) " ? " cast(tval(e)) " : " cast(fval(e))],top + 1) - (e:ValidIf) : emit([cast(value(e))],top + 1) - (e:WRef) : print(e) - (e:WSubField) : print(lowered-name(e)) - (e:WSubAccess) : print-all([lowered-name(exp(e)) "[" lowered-name(index(e)) "]"]) - (e:WSubIndex) : print(e) - (e:UIntValue|SIntValue) : v-print(e) - turn-on-debug(false) - (t:Type) : - match(t) : - (t:UIntType|SIntType) : - val w = long!(t) - to-long(1) - if w > to-long(0) : print-all(["[" w ":0]"]) - else : print("");" - (t:ClockType) : print("");" - (t:VectorType) : - emit(type(t), top + 1) - print-all(["[" size(t) - 1 ":0]"]) - (t) : println(t) - - (p:Direction) : - switch {_ == p} : - INPUT : print("input") - OUTPUT : print("output") - (s:Symbol) : print(s) - (i:Int) : print(i) - (i:Long) : print(i) - (s:String) : print(s) - (t:VIndent) : print(" ") - (r:VRandom) : print("$random") - (s:Streamable) : - for x in s do : - emit(x, top + 1) - if top == 0 : print("\n") - -;------------- PASS ----------------- -defn v-print (e:UIntValue|SIntValue) : - val str = to-string(value(e)) - val out = substring(str,1,length(str) - 1) - print $ string-join $ match(e) : - (e:UIntValue) : [long!(type(e)) "'" out] - (e:SIntValue) : [long!(type(e)) "'s" out] -defn op-stream (doprim:DoPrim) -> Streamable : - defn cast-if (e:Expression) -> ? : - val signed? = for x in args(doprim) any? : type(x) typeof SIntType - if not signed? : e - else : match(type(e)) : - (t:SIntType) : ["$signed(" e ")"] - (t:UIntType) : ["$signed({1'b0," e "})"] - defn cast (e:Expression) -> ? : - match(type(doprim)) : - (t:UIntType) : e - (t:SIntType) : ["$signed(" e ")"] - defn cast-as (e:Expression) -> ? : - match(type(e)) : - (t:UIntType) : e - (t:SIntType) : ["$signed(" e ")"] - defn a0 () -> Expression : args(doprim)[0] - defn a1 () -> Expression : args(doprim)[1] - defn a2 () -> Expression : args(doprim)[2] - defn c0 () -> Int : consts(doprim)[0] - defn c1 () -> Int : consts(doprim)[1] - - switch {_ == op(doprim)} : - ADD-OP : [cast-if(a0()) " + " cast-if(a1())] - ADDW-OP : [cast-if(a0()) " + " cast-if(a1())] - SUB-OP : [cast-if(a0()) " - " cast-if(a1())] - SUBW-OP : [cast-if(a0()) " - " cast-if(a1())] - MUL-OP : [cast-if(a0()) " * " cast-if(a1()) ] - DIV-OP : [cast-if(a0()) " / " cast-if(a1()) ] - REM-OP : [cast-if(a0()) " % " cast-if(a1()) ] - LESS-OP : [cast-if(a0()) " < " cast-if(a1())] - LESS-EQ-OP : [cast-if(a0()) " <= " cast-if(a1())] - GREATER-OP : [cast-if(a0()) " > " cast-if(a1())] - GREATER-EQ-OP : [cast-if(a0()) " >= " cast-if(a1())] - EQUAL-OP : [cast-if(a0()) " == " cast-if(a1())] - NEQUAL-OP : [cast-if(a0()) " != " cast-if(a1())] - PAD-OP : - val w = long!(type(a0())) - val diff = (to-long(c0()) - w) - if w == to-long(0) : [ a0() ] - else : match(type(doprim)) : - (t:SIntType) : ["{{" diff "{" a0() "[" w - to-long(1) "]}}, " a0() " }"] - (t) : ["{{" diff "'d0 }, " a0() " }"] - AS-UINT-OP : ["$unsigned(" a0() ")"] - AS-SINT-OP : ["$signed(" a0() ")"] - AS-CLOCK-OP : ["$unsigned(" a0() ")"] - DYN-SHIFT-LEFT-OP : [cast(a0()) " << " a1()] - DYN-SHIFT-RIGHT-OP : - match(type(doprim)) : - (t:SIntType) : [cast(a0()) " >>> " a1()] - (t) : [cast(a0()) " >> " a1()] - SHIFT-LEFT-OP : [cast(a0()) " << " c0()] - SHIFT-RIGHT-OP : [a0() "[" long!(type(a0())) - to-long(1) ":" c0() "]"] - NEG-OP : ["-{" cast(a0()) "}"] - CONVERT-OP : - match(type(a0())) : - (t:UIntType) : ["{1'b0," cast(a0()) "}"] - (t:SIntType) : [cast(a0())] - NOT-OP : ["~ " a0()] - AND-OP : [cast-as(a0()) " & " cast-as(a1())] - OR-OP : [cast-as(a0()) " | " cast-as(a1())] - XOR-OP : [cast-as(a0()) " ^ " cast-as(a1())] - AND-REDUCE-OP : - val v = Vector<Streamable>() - for b in 0 to to-int(long!(type(doprim))) do : - add(v,[cast(a0()) "[" b "]"]) - join(v," & ") - OR-REDUCE-OP : - val v = Vector<Streamable>() - for b in 0 to to-int(long!(type(doprim))) do : - add(v,[cast(a0() ) "[" b "]"]) - join(v," | ") - XOR-REDUCE-OP : - val v = Vector<Streamable>() - for b in 0 to to-int(long!(type(doprim))) do : - add(v,[cast(a0() ) "[" b "]"]) - join(v," ^ ") - CONCAT-OP : ["{" cast(a0()) "," cast(a1()) "}"] - BITS-SELECT-OP : - if c0() == c1() : [a0() "[" c0() "]"] - else : [a0() "[" c0() ":" c1() "]"] - HEAD-OP : - val w = long!(type(a0())) - val high = w - to-long(1) - val low = w - to-long(c0()) - [a0() "[" high ":" low "]"] - TAIL-OP : - val w = long!(type(a0())) - val low = w - to-long(c0()) - to-long(1) - [a0() "[" low ":" 0 "]"] - -defn emit-verilog (m:InModule) -> Module : - mname = name(m) - val netlist = HashTable<Expression,Expression>(exp-hash) - val simlist = Vector<Stmt>() - val namehash = get-sym-hash(m,keys(v-keywords)) - defn build-netlist (s:Stmt) -> Stmt : - match(s) : - (s:Connect) : netlist[loc(s)] = exp(s) - (s:IsInvalid) : - val n = firrtl-gensym(`GEN,namehash) - val e = wref(n,type(exp(s))) - netlist[exp(s)] = e - (s:Conditionally) : add(simlist,s) - (s:DefNode) : - val e = WRef(name(s),get-type(s),NodeKind(),MALE) - netlist[e] = value(s) - (s) : map(build-netlist,s) - s - - val portdefs = Vector<Streamable>() - val declares = Vector<Streamable>() - val instdeclares = Vector<Streamable>() - val assigns = Vector<Streamable>() - val at-clock = HashTable<Expression,Vector<Streamable>>(exp-hash) - val initials = Vector<Streamable>() - val simulates = Vector<Streamable>() - defn declare (b:Symbol,n:Symbol,t:Type) : - match(t) : - (t:VectorType) : add(declares,[b " " type(t) " " n " [0:" size(t) - 1 "];"]) - (t) : add(declares,[b " " t " " n ";"]) - defn assign (e:Expression,value:Expression) : - add(assigns,["assign " e " = " value ";"]) - defn update-and-reset (r:Expression,clk:Expression,reset?:Expression,init:Expression) : - if not key?(at-clock,clk) : at-clock[clk] = Vector<Streamable>() - defn add-update (e:Expression,tabs:String) : - match(e) : - (e:Mux) : - add(at-clock[clk],[tabs "if(" cond(e) ") begin"]) - add-update(tval(e),string-join([tabs tab])) - add(at-clock[clk],[tabs "end else begin"]) - add-update(fval(e),string-join([tabs tab])) - add(at-clock[clk],[tabs "end"]) - (e) : - if e == r : add(at-clock[clk],[tabs ";"]) - else : add(at-clock[clk],[tabs r " <= " e ";"]) - val tv = init - val fv = netlist[r] - add-update(Mux(reset?,tv,fv,mux-type-and-widths(tv,fv)),"");" - defn update (e:Expression,value:Expression,clk:Expression,en:Expression) : - if not key?(at-clock,clk) : - at-clock[clk] = Vector<Streamable>() - if en == one : - add(at-clock[clk],[e " <= " value ";"]) - else : - add(at-clock[clk],["if(" en ") begin"]) - add(at-clock[clk],[tab e " <= " value ";"]) - add(at-clock[clk],["end"]) - defn initialize (e:Expression) : - add(initials,[e " = " rand-string(type(e)) ";"]) - defn initialize-mem (n:Symbol,i:Int,t:Type) : - add(initials,["for (initvar = 0; initvar < " i "; initvar = initvar+1)"]) - val index = WRef(`initvar,UnknownType(),ExpKind(),UNKNOWN-GENDER) - add(initials,[tab WSubAccess(wref(n,t),index,UnknownType(),FEMALE), " = " rand-string(t) ";"]) - defn instantiate (n:Symbol,m:Symbol,es:List<Expression>) : - add(instdeclares,[m " " n " ("]) - for (e in es,i in 0 to false) do : - val s = [tab "." remove-root(e) "(" lowered-name(e) ")"] - if i != length(es) - 1 : add(instdeclares,[s ","]) - else : add(instdeclares,s) - add(instdeclares,[");"]) - for e in es do : - declare(`wire,lowered-name(e),type(e)) - val e* = WRef(lowered-name(e),type(e),kind(e),gender(e)) - if (gender(e) == FEMALE) : assign(e*,netlist[e]) - defn simulate (clk:Expression,en:Expression,s:Streamable) : - if not key?(at-clock,clk) : - at-clock[clk] = Vector<Streamable>() - add(at-clock[clk],["`ifndef SYNTHESIS"]) - add(at-clock[clk],[tab "if(" en ") begin"]) - add(at-clock[clk],[tab tab s]) - add(at-clock[clk],[tab "end"]) - add(at-clock[clk],["`endif"]) - defn stop (ret:Int) -> Streamable : - ["$fdisplay(32'h80000002,\"" ret "\");$finish;"] - defn printf (str:String,args:List<Expression>) -> Streamable : - val str* = join(List(escape(str),args),",") - ["$fwrite(32'h80000002," str* ");"] - defn delay (e:Expression, n:Int, clk:Expression) -> Expression : - var e* = e - for i in 0 to n do : - val name = firrtl-gensym(`GEN,namehash) - declare(`reg,name,type(e)) - val e** = WRef(name,type(e),ExpKind(),UNKNOWN-GENDER) - update(e**,e*,clk,one) - e* = e** - e* - defn build-ports () : - for (p in ports(m),i in 0 to false) do : - var end = ",\n" - if length(ports(m)) - 1 == i : - end = "\n);\n" - switch {_ == direction(p)} : - INPUT : - add(portdefs,[direction(p) " " type(p) " " name(p) ]) - OUTPUT : - add(portdefs,[direction(p) " " type(p) " " name(p) ]) - val e* = WRef(name(p),type(p),PortKind(),FEMALE) - assign(e*,netlist[e*]) - if length(ports(m)) == 0 : print(");\n") - defn build-streams (s:Stmt) -> Stmt : - match(s) : - (s:Connect) : s - (s:DefWire) : - declare(`wire,name(s),type(s)) - val e = wref(name(s),type(s)) - assign(e,netlist[e]) - (s:DefRegister) : - declare(`reg,name(s),type(s)) - val e = wref(name(s),type(s)) - update-and-reset(e,clock(s),reset(s),init(s)) - initialize(e) - (s:IsInvalid) : - val wref = netlist[exp(s)] as WRef - declare(`reg,name(wref),type(exp(s))) - initialize(wref) - (s:DefPoison) : - val n = name(s) - val e = wref(n,type(s)) - declare(`reg,n,type(e)) - initialize(e) - (s:DefNode) : - declare(`wire,name(s),type(value(s))) - assign(WRef(name(s),type(value(s)),NodeKind(),MALE),value(s)) - (s:Stop) : simulate(clk(s),en(s),stop(ret(s))) - (s:Print) : simulate(clk(s),en(s),printf(string(s),args(s))) - (s:WDefInstance) : - val es = create-exps(WRef(name(s),type(s),InstanceKind(),MALE)) - instantiate(name(s),module(s),es) - (s:DefMemory) : - val mem = WRef(name(s),get-type(s),MemKind(append-all([readers(s) writers(s) readwriters(s)])),UNKNOWN-GENDER) - defn mem-exp (p:Symbol,f:Symbol) : - val t1 = field-type(type(mem),p) - val t2 = field-type(t1,f) - WSubField{_,f,t2,UNKNOWN-GENDER} $ - WSubField{_,p,t1,UNKNOWN-GENDER} $ - mem - - declare(`reg,name(s),VectorType(data-type(s),depth(s))) - initialize-mem(name(s),depth(s),data-type(s)) - for r in readers(s) do : - val data = mem-exp(r,`data) - val addr = mem-exp(r,`addr) - val en = mem-exp(r,`en) - val clk = mem-exp(r,`clk) - - declare(`wire,lowered-name(data),type(data)) - declare(`wire,lowered-name(addr),type(addr)) - declare(`wire,lowered-name(en),type(en)) - declare(`wire,lowered-name(clk),type(clk)) - - ; Read port - assign(addr,netlist[addr]) ;Connects value to m.r.addr - assign(en,netlist[en]) ;Connects value to m.r.en - assign(clk,netlist[clk]) ;Connects value to m.r.clk - val addr* = delay(addr,read-latency(s),clk) - val en* = delay(en,read-latency(s),clk) - val mem-port = WSubAccess(mem,addr*,UnknownType(),UNKNOWN-GENDER) - assign(data,mem-port) - - for w in writers(s) do : - val data = mem-exp(w,`data) - val addr = mem-exp(w,`addr) - val mask = mem-exp(w,`mask) - val en = mem-exp(w,`en) - val clk = mem-exp(w,`clk) - - declare(`wire,lowered-name(data),type(data)) - declare(`wire,lowered-name(addr),type(addr)) - declare(`wire,lowered-name(mask),type(mask)) - declare(`wire,lowered-name(en),type(en)) - declare(`wire,lowered-name(clk),type(clk)) - - ; Write port - assign(data,netlist[data]) - assign(addr,netlist[addr]) - assign(mask,netlist[mask]) - assign(en,netlist[en]) - assign(clk,netlist[clk]) - - val data* = delay(data,write-latency(s) - 1,clk) - val addr* = delay(addr,write-latency(s) - 1,clk) - val mask* = delay(mask,write-latency(s) - 1,clk) - val en* = delay(en,write-latency(s) - 1,clk) - val mem-port = WSubAccess(mem,addr*,UnknownType(),UNKNOWN-GENDER) - update(mem-port,data*,clk,AND(en*,mask*)) - - for rw in readwriters(s) do : - val wmode = mem-exp(rw,`wmode) - val rdata = mem-exp(rw,`rdata) - val data = mem-exp(rw,`data) - val mask = mem-exp(rw,`mask) - val addr = mem-exp(rw,`addr) - val en = mem-exp(rw,`en) - val clk = mem-exp(rw,`clk) - - declare(`wire,lowered-name(wmode),type(wmode)) - declare(`wire,lowered-name(rdata),type(rdata)) - declare(`wire,lowered-name(data),type(data)) - declare(`wire,lowered-name(mask),type(mask)) - declare(`wire,lowered-name(addr),type(addr)) - declare(`wire,lowered-name(en),type(en)) - declare(`wire,lowered-name(clk),type(clk)) - - ; Assigned to lowered wires of each - assign(clk,netlist[clk]) - assign(addr,netlist[addr]) - assign(data,netlist[data]) - assign(addr,netlist[addr]) - assign(mask,netlist[mask]) - assign(en,netlist[en]) - assign(wmode,netlist[wmode]) - - ; Delay new signals by latency - val raddr* = delay(addr,read-latency(s),clk) - val waddr* = delay(addr,write-latency(s) - 1,clk) - val en* = delay(en,write-latency(s) - 1,clk) - val rmod* = delay(wmode,write-latency(s) - 1,clk) - val data* = delay(data,write-latency(s) - 1,clk) - val mask* = delay(mask,write-latency(s) - 1,clk) - - ; Write - - val rmem-port = WSubAccess(mem,raddr*,UnknownType(),UNKNOWN-GENDER) - assign(rdata,rmem-port) - val wmem-port = WSubAccess(mem,waddr*,UnknownType(),UNKNOWN-GENDER) - update(wmem-port,data*,clk,AND(AND(en*,mask*),wmode)) - (s:Begin) : map(build-streams,s) - s - - defn emit-streams () : - emit(["module " name(m) "("]) - if !empty?(portdefs) : - for (x in portdefs, i in 0 to false) do : - if i != length(portdefs) - 1 : emit([tab x ","]) - else : emit([tab x]) - emit([");"]) - - if !empty?(declares) : - for x in declares do : emit([tab x]) - - if !empty?(instdeclares) : - for x in instdeclares do : emit([tab x]) - - if !empty?(assigns) : - for x in assigns do : emit([tab x]) - - if !empty?(initials) : - emit(["`ifndef SYNTHESIS"]) - emit([" integer initvar;"]) - emit([" initial begin"]) - emit([" #0.002;"]) - for x in initials do : - emit([tab x]) - emit([" end"]) - emit(["`endif"]) - - for clk-stream in at-clock do : - if !empty?(value(clk-stream)) : - emit([tab "always @(posedge " key(clk-stream) ") begin"]) - for x in value(clk-stream) do : - emit([tab tab x]) - emit([tab "end"]) - - emit(["endmodule"]) - - build-netlist(body(m)) - build-ports() - build-streams(body(m)) - emit-streams() - m - -defn emit-verilog (with-output:(() -> False) -> False, c:Circuit) : - with-output $ fn () : - for m in modules(c) do : - match(m) : - (m:InModule) : emit-verilog(m) - (m:ExModule) : false - c - - -;============ LoFIRRTLToVERILOG ============== - -public defstruct LoToVerilog <: Pass : - with-output: (() -> False) -> False -public defmethod pass (b:LoToVerilog) -> (Circuit -> Circuit) : lo-to-verilog{with-output(b),_} -public defmethod name (b:LoToVerilog) -> String : "Lo To Verilog" -public defmethod short-name (b:LoToVerilog) -> String : "lo-to-verilog" - -defn lo-to-verilog (with-output:(() -> False) -> False, c:Circuit) : - val c1 = to-working-ir(c) - ;println(c1) - val c2 = resolve(c1) - ;println(c2) - val c3 = v-wrap(c2) - ;println(c3) - val c4 = split-exp(c3) - ;println(c4) - val c5 = verilog-rename(c4) - ;println(c5) - emit-verilog(with-output,c5) - - diff --git a/src/main/stanza/primop.stanza b/src/main/stanza/primop.stanza deleted file mode 100644 index f6aa0de5..00000000 --- a/src/main/stanza/primop.stanza +++ /dev/null @@ -1,280 +0,0 @@ -;Copyright (c) 2014 - 2016 The Regents of the University of -;California (Regents). All Rights Reserved. Redistribution and use in -;source and binary forms, with or without modification, are permitted -;provided that the following conditions are met: -; * Redistributions of source code must retain the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer. -; * Redistributions in binary form must reproduce the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer in the documentation and/or other materials -; provided with the distribution. -; * Neither the name of the Regents nor the names of its contributors -; may be used to endorse or promote products derived from this -; software without specific prior written permission. -;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, -;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF -;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT -;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF -;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION -;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR -;MODIFICATIONS. -defpackage firrtl/primops : - import core - import verse - import firrtl/ir2 - import firrtl/ir-utils - import firrtl/passes - - -public defn set-primop-type (e:DoPrim) -> DoPrim : - ;println-all(["Inferencing primop type: " e]) - defn PLUS (w1:Width,w2:Width) -> Width : PlusWidth(w1,w2) - defn MAX (w1:Width,w2:Width) -> Width : MaxWidth(list(w1,w2)) - defn MINUS (w1:Width,w2:Width) -> Width : MinusWidth(w1,w2) - defn POW (w1:Width) -> Width : ExpWidth(w1) - defn MIN (w1:Width,w2:Width) -> Width : MinWidth(list(w1,w2)) - val o = op(e) - val a = args(e) - val c = consts(e) - defn t1 () : type(a[0]) - defn t2 () : type(a[1]) - defn t3 () : type(a[2]) - defn w1 () : width!(type(a[0])) - defn w2 () : width!(type(a[1])) - defn w3 () : width!(type(a[2])) - defn c1 () : IntWidth(c[0]) - defn c2 () : IntWidth(c[1]) - switch {op(e) == _} : - ADD-OP : DoPrim{o,a,c,_} $ - match(t1(),t2()) : - (t1:UIntType, t2:UIntType) : UIntType(PLUS(MAX(w1(),w2()),ONE)) - (t1:UIntType, t2:SIntType) : SIntType(PLUS(MAX(w1(),w2()),ONE)) - (t1:SIntType, t2:UIntType) : SIntType(PLUS(MAX(w1(),w2()),ONE)) - (t1:SIntType, t2:SIntType) : SIntType(PLUS(MAX(w1(),w2()),ONE)) - (t1, t2) : UnknownType() - SUB-OP : DoPrim{o,a,c,_} $ - match(t1(),t2()) : - (t1:UIntType, t2:UIntType) : SIntType(PLUS(MAX(w1(),w2()),ONE)) - (t1:UIntType, t2:SIntType) : SIntType(PLUS(MAX(w1(),w2()),ONE)) - (t1:SIntType, t2:UIntType) : SIntType(PLUS(MAX(w1(),w2()),ONE)) - (t1:SIntType, t2:SIntType) : SIntType(PLUS(MAX(w1(),w2()),ONE)) - (t1, t2) : UnknownType() - MUL-OP : DoPrim{o,a,c,_} $ - match(t1(),t2()) : - (t1:UIntType, t2:UIntType) : UIntType(PLUS(w1(),w2())) - (t1:UIntType, t2:SIntType) : SIntType(PLUS(w1(),w2())) - (t1:SIntType, t2:UIntType) : SIntType(PLUS(w1(),w2())) - (t1:SIntType, t2:SIntType) : SIntType(PLUS(w1(),w2())) - (t1, t2) : UnknownType() - DIV-OP : DoPrim{o,a,c,_} $ - match(t1(),t2()) : - (t1:UIntType, t2:UIntType) : UIntType(w1()) - (t1:UIntType, t2:SIntType) : SIntType(PLUS(w1(),ONE)) - (t1:SIntType, t2:UIntType) : SIntType(w1()) - (t1:SIntType, t2:SIntType) : SIntType(PLUS(w1(),ONE)) - (t1, t2) : UnknownType() - REM-OP : DoPrim{o,a,c,_} $ - match(t1(),t2()) : - (t1:UIntType, t2:UIntType) : UIntType(MIN(w1(),w2())) - (t1:UIntType, t2:SIntType) : UIntType(MIN(w1(),w2())) - (t1:SIntType, t2:UIntType) : SIntType(MIN(w1(),PLUS(w2(),ONE))) - (t1:SIntType, t2:SIntType) : SIntType(MIN(w1(),w2())) - (t1, t2) : UnknownType() - LESS-OP : DoPrim{o,a,c,_} $ - match(t1(),t2()) : - (t1:UIntType|SIntType, t2:UIntType|SIntType) : BoolType() - (t1, t2) : UnknownType() - LESS-EQ-OP : DoPrim{o,a,c,_} $ - match(t1(),t2()) : - (t1:UIntType|SIntType, t2:UIntType|SIntType) : BoolType() - (t1, t2) : UnknownType() - GREATER-OP : DoPrim{o,a,c,_} $ - match(t1(),t2()) : - (t1:UIntType|SIntType, t2:UIntType|SIntType) : BoolType() - (t1, t2) : UnknownType() - GREATER-EQ-OP : DoPrim{o,a,c,_} $ - match(t1(),t2()) : - (t1:UIntType|SIntType, t2:UIntType|SIntType) : BoolType() - (t1, t2) : UnknownType() - EQUAL-OP : DoPrim{o,a,c,_} $ - match(t1(),t2()) : - (t1:UIntType|SIntType, t2:UIntType|SIntType) : BoolType() - (t1, t2) : UnknownType() - NEQUAL-OP : DoPrim{o,a,c,_} $ - match(t1(),t2()) : - (t1:UIntType|SIntType, t2:UIntType|SIntType) : BoolType() - (t1, t2) : UnknownType() - PAD-OP : DoPrim{o,a,c,_} $ - match(t1()) : - (t1:UIntType) : UIntType(MAX(w1(),c1())) - (t1:SIntType) : SIntType(MAX(w1(),c1())) - (t1) : UnknownType() - AS-UINT-OP : DoPrim{o,a,c,_} $ - match(t1()) : - (t1:UIntType) : UIntType(w1()) - (t1:SIntType) : UIntType(w1()) - (t1:ClockType) : UIntType(ONE) - (t1) : UnknownType() - AS-SINT-OP : DoPrim{o,a,c,_} $ - match(t1()) : - (t1:UIntType) : SIntType(w1()) - (t1:SIntType) : SIntType(w1()) - (t1:ClockType) : SIntType(ONE) - (t1) : UnknownType() - AS-CLOCK-OP : DoPrim{o,a,c,_} $ - match(t1()) : - (t1:UIntType) : ClockType() - (t1:SIntType) : ClockType() - (t1:ClockType) : ClockType() - (t1) : UnknownType() - SHIFT-LEFT-OP : DoPrim{o,a,c,_} $ - match(t1()) : - (t1:UIntType) : UIntType(PLUS(w1(),c1())) - (t1:SIntType) : SIntType(PLUS(w1(),c1())) - (t1) : UnknownType() - SHIFT-RIGHT-OP : DoPrim{o,a,c,_} $ - match(t1()) : - (t1:UIntType) : UIntType(MINUS(w1(),c1())) - (t1:SIntType) : SIntType(MINUS(w1(),c1())) - (t1) : UnknownType() - DYN-SHIFT-LEFT-OP : DoPrim{o,a,c,_} $ - match(t1()) : - (t1:UIntType) : UIntType(PLUS(w1(),POW(w2()))) - (t1:SIntType) : SIntType(PLUS(w1(),POW(w2()))) - (t1) : UnknownType() - DYN-SHIFT-RIGHT-OP : DoPrim{o,a,c,_} $ - match(t1()) : - (t1:UIntType) : UIntType(w1()) - (t1:SIntType) : SIntType(w1()) - (t1) : UnknownType() - CONVERT-OP : DoPrim{o,a,c,_} $ - match(t1()) : - (t1:UIntType) : SIntType(PLUS(w1(),ONE)) - (t1:SIntType) : SIntType(w1()) - (t1) : UnknownType() - NEG-OP : DoPrim{o,a,c,_} $ - match(t1()) : - (t1:UIntType) : SIntType(PLUS(w1(),ONE)) - (t1:SIntType) : SIntType(PLUS(w1(),ONE)) - (t1) : UnknownType() - NOT-OP : DoPrim{o,a,c,_} $ - match(t1()) : - (t1:UIntType|SIntType) : UIntType(w1()) - (t1) : UnknownType() - AND-OP : DoPrim{o,a,c,_} $ - match(t1(),t2()) : - (t1:UIntType|SIntType, t2:UIntType|SIntType) : UIntType(MAX(w1(),w2())) - (t1,t2) : UnknownType() - OR-OP : DoPrim{o,a,c,_} $ - match(t1(),t2()) : - (t1:UIntType|SIntType, t2:UIntType|SIntType) : UIntType(MAX(w1(),w2())) - (t1,t2) : UnknownType() - XOR-OP : DoPrim{o,a,c,_} $ - match(t1(),t2()) : - (t1:UIntType|SIntType, t2:UIntType|SIntType) : UIntType(MAX(w1(),w2())) - (t1,t2) : UnknownType() - AND-REDUCE-OP : DoPrim{o,a,c,_} $ - match(t1()) : - (t1:UIntType|SIntType) : BoolType() - (t1) : UnknownType() - OR-REDUCE-OP : DoPrim{o,a,c,_} $ - match(t1()) : - (t1:UIntType|SIntType) : BoolType() - (t1) : UnknownType() - XOR-REDUCE-OP : DoPrim{o,a,c,_} $ - match(t1()) : - (t1:UIntType|SIntType) : BoolType() - (t1) : UnknownType() - CONCAT-OP : DoPrim{o,a,c,_} $ - match(t1(),t2()) : - (t1:UIntType|SIntType, t2:UIntType|SIntType) : UIntType(PLUS(w1(),w2())) - (t1, t2) : UnknownType() - BITS-SELECT-OP : DoPrim{o,a,c,_} $ - match(t1()) : - (t1:UIntType|SIntType) : UIntType(PLUS(MINUS(c1(),c2()),ONE)) - (t1) : UnknownType() - HEAD-OP : DoPrim{o,a,c,_} $ - match(t1()) : - (t1:UIntType|SIntType) : UIntType(c1()) - (t1) : UnknownType() - TAIL-OP : DoPrim{o,a,c,_} $ - match(t1()) : - (t1:UIntType|SIntType) : UIntType(MINUS(w1(),c1())) - (t1) : UnknownType() - -;public defn primop-gen-constraints (e:DoPrim,v:Vector<WGeq>) -> Type : -; defn get-max (i0:Int,i1:Int) -> Width : get-max(list(i0,i1)) -; defn get-max (ls:List<Int>) -> Width : -; MaxWidth $ for i in ls map : width!(args(e)[i]) -; defn all-max () -> Width : -; MaxWidth $ for x in args(e) map : width!(x) -; -; println-all-debug(["Looking at " op(e) " with inputs " args(e)]) -; val w* = switch {op(e) == _} : -; ADD-OP : PlusWidth(get-max(0,1),IntWidth(1)) -; SUB-OP : PlusWidth(get-max(0,1),IntWidth(1)) -; MUL-OP : PlusWidth(get-max(0,1),get-max(0,1)) -; DIV-OP : -; match(type(args(e)[0]),type(args(e)[1])) : -; (t0:UIntType,t1:SIntType) : PlusWidth(width!(args(e)[0]),IntWidth(1)) -; (t0:SIntType,t1:SIntType) : PlusWidth(width!(args(e)[0]),IntWidth(1)) -; (t0,t1) : width!(args(e)[0]) -; REM-OP : -; match(type(args(e)[0]),type(args(e)[1])) : -; (t0:SIntType,t1:UIntType) : PlusWidth(width!(args(e)[1]),IntWidth(1)) -; (t0,t1) : width!(args(e)[1]) -; QUO-OP : -; match(type(args(e)[0]),type(args(e)[1])) : -; (t0:UIntType,t1:SIntType) : PlusWidth(width!(args(e)[0]),IntWidth(1)) -; (t0:SIntType,t1:SIntType) : PlusWidth(width!(args(e)[0]),IntWidth(1)) -; (t0,t1) : width!(args(e)[0]) -; REM-OP : -; match(type(args(e)[0]),type(args(e)[1])) : -; (t0:SIntType,t1:UIntType) : PlusWidth(width!(args(e)[1]),IntWidth(1)) -; (t0,t1) : width!(args(e)[1]) -; ADD-WRAP-OP : get-max(0,1) -; SUB-WRAP-OP : get-max(0,1) -; LESS-OP : IntWidth(1) -; LESS-EQ-OP : IntWidth(1) -; GREATER-OP : IntWidth(1) -; GREATER-EQ-OP : IntWidth(1) -; EQUAL-OP : IntWidth(1) -; NEQUAL-OP : IntWidth(1) -; EQUIV-OP : IntWidth(1) -; NEQUIV-OP : IntWidth(1) -; MUX-OP : -; add(v,WGeq(IntWidth(1),width!(args(e)[0]))) -; add(v,WGeq(width!(args(e)[0]),IntWidth(1))) -; get-max(1,2) -; PAD-OP : IntWidth(consts(e)[0]) -; AS-UINT-OP : width!(args(e)[0]) -; AS-SINT-OP : width!(args(e)[0]) -; SHIFT-LEFT-OP : PlusWidth(width!(args(e)[0]),IntWidth(consts(e)[0])) -; SHIFT-RIGHT-OP : MinusWidth(width!(args(e)[0]),IntWidth(consts(e)[0])) -; DYN-SHIFT-LEFT-OP : PlusWidth(width!(args(e)[0]),ExpWidth(width!(args(e)[1]))) -; DYN-SHIFT-RIGHT-OP : width!(args(e)[0]) -; CONVERT-OP : -; match(type(args(e)[0])) : -; (t0:UIntType) : PlusWidth(width!(args(e)[0]),IntWidth(1)) -; (t0:SIntType) : width!(args(e)[0]) -; NEG-OP : PlusWidth(width!(args(e)[0]),IntWidth(1)) -; BIT-NOT-OP : width!(args(e)[0]) -; BIT-AND-OP : get-max(0,1) -; BIT-OR-OP : get-max(0,1) -; BIT-XOR-OP : get-max(0,1) -; BIT-AND-REDUCE-OP : all-max() -; BIT-OR-REDUCE-OP : all-max() -; BIT-XOR-REDUCE-OP : all-max() -; CONCAT-OP : PlusWidth(width!(args(e)[0]),width!(args(e)[1])) -; BIT-SELECT-OP : IntWidth(1) -; BITS-SELECT-OP : IntWidth(consts(e)[0] - consts(e)[1] + 1) -; -; match(type(e)) : -; (t:UIntType) : UIntType(w*) -; (t:SIntType) : SIntType(w*) -; (t) : error("Shouldn't be here") -; diff --git a/src/main/stanza/symbolic-value.stanza b/src/main/stanza/symbolic-value.stanza deleted file mode 100644 index 3d073f1b..00000000 --- a/src/main/stanza/symbolic-value.stanza +++ /dev/null @@ -1,95 +0,0 @@ -;Copyright (c) 2014 - 2016 The Regents of the University of -;California (Regents). All Rights Reserved. Redistribution and use in -;source and binary forms, with or without modification, are permitted -;provided that the following conditions are met: -; * Redistributions of source code must retain the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer. -; * Redistributions in binary form must reproduce the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer in the documentation and/or other materials -; provided with the distribution. -; * Neither the name of the Regents nor the names of its contributors -; may be used to endorse or promote products derived from this -; software without specific prior written permission. -;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, -;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF -;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT -;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF -;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION -;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR -;MODIFICATIONS. -defpackage firrtl/symbolic-value : - import core - import verse - import firrtl/ir2 - import firrtl/ir-utils - -; ======= Symbolic Value Library ========== -public definterface SymbolicValue -public defstruct SVExp <: SymbolicValue : - exp : Expression -public defstruct SVMux <: SymbolicValue : - pred : Expression - conseq : SymbolicValue - alt : SymbolicValue -public defstruct SVNul <: SymbolicValue - -defmethod print (o:OutputStream, sv:SymbolicValue) : - match(sv) : - (sv: SVExp) : print(o, exp(sv)) - (sv: SVMux) : print-all(o, ["(" pred(sv) " ? " conseq(sv) " : " alt(sv) ")"]) - (sv: SVNul) : print(o, "SVNUL") - -defn map (f: Expression -> Expression, sv:SymbolicValue) -> SymbolicValue : - match(sv) : - (sv:SVMux) : SVMux(f(pred(sv)),conseq(sv),alt(sv)) - (sv:SVExp) : SVExp(f(exp(sv))) - (sv:SVNul) : sv - -defmulti map<?T> (f: SymbolicValue -> SymbolicValue, sv:?T&SymbolicValue) -> T -defmethod map (f: SymbolicValue -> SymbolicValue, sv:SymbolicValue) -> SymbolicValue : - match(sv) : - (sv: SVMux) : SVMux(pred(sv),f(conseq(sv)),f(alt(sv))) - (sv) : sv - -defn do (f:SymbolicValue -> ?, s:SymbolicValue) -> False : - defn f* (sv:SymbolicValue) -> SymbolicValue : - f(sv) - sv - map(f*,s) - false - -defn dor (f:SymbolicValue -> ?, e:SymbolicValue) -> False : - do(f,e) - defn f* (x:SymbolicValue) -> SymbolicValue : - dor(f,x) - x - map(f*,e) - false - -defmethod equal? (a:SymbolicValue,b:SymbolicValue) -> True|False : - match(a,b) : - (a:SVNul,b:SVNul) : true - (a:SVExp,b:SVExp) : exp(a) == exp(b) - (a:SVMux,b:SVMux) : pred(a) == pred(b) and conseq(a) == conseq(b) and alt(a) == alt(b) - (a,b) : false - -;TODO add invert to primop -defn optimize (sv:SymbolicValue) -> SymbolicValue : - match(map(optimize,sv)) : - (sv:SVMux) : - if conseq(sv) == alt(sv) : conseq(sv) - else : - match(conseq(sv),alt(sv)) : - (c:SVExp,a:SVExp) : - if exp(c) == one and exp(a) == zero : SVExp(pred(sv)) - else if exp(c) == zero and exp(a) == one : SVExp(NOT(pred(sv))) - else if exp(c) == exp(a) : c - else : sv - (c,a) : sv - (sv) : sv - diff --git a/src/main/stanza/widthsolver.stanza b/src/main/stanza/widthsolver.stanza deleted file mode 100644 index b3f72f03..00000000 --- a/src/main/stanza/widthsolver.stanza +++ /dev/null @@ -1,322 +0,0 @@ -;Copyright (c) 2014 - 2016 The Regents of the University of -;California (Regents). All Rights Reserved. Redistribution and use in -;source and binary forms, with or without modification, are permitted -;provided that the following conditions are met: -; * Redistributions of source code must retain the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer. -; * Redistributions in binary form must reproduce the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer in the documentation and/or other materials -; provided with the distribution. -; * Neither the name of the Regents nor the names of its contributors -; may be used to endorse or promote products derived from this -; software without specific prior written permission. -;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, -;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF -;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT -;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF -;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION -;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR -;MODIFICATIONS. -;Define the STANDALONE flag to run STANDALONE -#if-defined(STANDALONE) : - #include<"core/stringeater.stanza"> - #include<"compiler/lexer.stanza"> - -defpackage widthsolver : - import core - import verse - import stz/lexer - -;============= Language of Constraints ====================== -public definterface WConstraint -public defstruct WidthEqual <: WConstraint : - name: Symbol - value: Exp -public defstruct WidthGreater <: WConstraint : - name: Symbol - value: Exp - -defmethod print (o:OutputStream, c:WConstraint) : - print-all{o, _} $ - match(c) : - (c:WidthEqual) : [name(c) " = " value(c)] - (c:WidthGreater) : [name(c) " >= " value(c)] - -defn construct-eqns (cs: Streamable<WConstraint>) : - val eqns = HashTable<Symbol, False|Exp>(symbol-hash) - val lower-bounds = HashTable<Symbol, List<Exp>>(symbol-hash) - for c in cs do : - match(c) : - (c:WidthEqual) : - eqns[name(c)] = value(c) - (c:WidthGreater) : - lower-bounds[name(c)] = - List(value(c), - get?(lower-bounds, name(c), List())) - - ;Create minimum expressions for lower-bounds - for entry in lower-bounds do : - val v = key(entry) - val exps = value(entry) - if not key?(eqns, v) : - eqns[v] = reduce(EMax, ELit(0), exps) - - ;Return equations - eqns -;============================================================ - -;============= Language of Expressions ====================== -public definterface Exp -public defstruct EVar <: Exp : - name: Symbol -public defstruct EMax <: Exp : - a: Exp - b: Exp -public defstruct EPlus <: Exp : - a: Exp - b: Exp -public defstruct EMinus <: Exp : - a: Exp - b: Exp -public defstruct ELit <: Exp : - width: Int - -defmethod print (o:OutputStream, e:Exp) : - match(e) : - (e:EVar) : print(o, name(e)) - (e:EMax) : print-all(o, ["max(" a(e) ", " b(e) ")"]) - (e:EPlus) : print-all(o, [a(e) " + " b(e)]) - (e:EMinus) : print-all(o, [a(e) " - " b(e)]) - (e:ELit) : print(o, width(e)) - -defn map (f: (Exp) -> Exp, e: Exp) -> Exp : - match(e) : - (e:EMax) : EMax(f(a(e)), f(b(e))) - (e:EPlus) : EPlus(f(a(e)), f(b(e))) - (e:EMinus) : EMinus(f(a(e)), f(b(e))) - (e:Exp) : e - -defn children (e: Exp) -> List<Exp> : - match(e) : - (e:EMax) : list(a(e), b(e)) - (e:EPlus) : list(a(e), b(e)) - (e:EMinus) : list(a(e), b(e)) - (e:Exp) : list() -;============================================================ - -;================== Reading from File ======================= -defn read-exp (x) : - match(unwrap-token(x)) : - (x:Symbol) : - EVar(x) - (x:Int) : - ELit(x) - (x:List) : - val tag = unwrap-token(x[1]) - switch {tag == _} : - `plus : EPlus(read-exp(x[2]), read-exp(x[3])) - `minus : EMinus(read-exp(x[2]), read-exp(x[3])) - `max : EMax(read-exp(x[2]), read-exp(x[3])) - else : error $ string-join $ - ["Improper expression: " x] - -defn read (filename: String) : - var form:List = lex-file(filename) - val cs = Vector<WConstraint>() - while not empty?(form) : - val x = unwrap-token(form[0]) - val op = form[1] - val e = read-exp(form[2]) - form = tailn(form, 3) - add{cs, _} $ - switch {unwrap-token(op) == _} : - `= : WidthEqual(x, e) - `>= : WidthGreater(x, e) - else : error $ string-join $ ["Unsupported Operator: " op] - cs -;============================================================ - -;============ Operations on Expressions ===================== -defn occurs? (v: Symbol, exp: Exp) : - match(exp) : - (exp: EVar) : name(exp) == v - (exp: Exp) : any?(occurs?{v, _}, children(exp)) - -defn freevars (exp: Exp) : - to-list $ generate<Symbol> : - defn loop (exp: Exp) : - match(exp) : - (exp: EVar) : yield(name(exp)) - (exp: Exp) : do(loop, children(exp)) - loop(exp) - -defn contains-only-max? (exp: Exp) : - match(exp) : - (exp:EVar|EMax|ELit) : all?(contains-only-max?, children(exp)) - (exp) : false - -defn simplify (exp: Exp) : - match(map(simplify,exp)) : - (exp: EPlus) : - match(a(exp), b(exp)) : - (a: ELit, b: ELit) : - ELit(width(a) + width(b)) - (a: ELit, b) : - if width(a) == 0 : b - else : exp - (a, b: ELit) : - if width(b) == 0 : a - else : exp - (a, b) : - exp - (exp: EMinus) : - match(a(exp), b(exp)) : - (a: ELit, b: ELit) : - ELit(width(a) - width(b)) - (a, b: ELit) : - if width(b) == 0 : a - else : exp - (a, b) : - exp - (exp: EMax) : - match(a(exp), b(exp)) : - (a: ELit, b: ELit) : - ELit(max(width(a), width(b))) - (a: ELit, b) : - if width(a) == 0 : b - else : exp - (a, b: ELit) : - if width(b) == 0 : a - else : exp - (a, b) : - exp - (exp: Exp) : - exp - -defn eval (exp: Exp, state: HashTable<Symbol,Int>) -> Int : - defn loop (e: Exp) -> Int : - match(e) : - (e: EVar) : state[name(e)] - (e: EMax) : max(loop(a(e)), loop(b(e))) - (e: EPlus) : loop(a(e)) + loop(b(e)) - (e: EMinus) : loop(a(e)) - loop(b(e)) - (e: ELit) : width(e) - loop(exp) -;============================================================ - - -;================ Constraint Solver ========================= -defn substitute (solns: HashTable<Symbol, Exp>, exp: Exp) : - match(exp) : - (exp: EVar) : - match(get?(solns, name(exp), false)) : - (s:Exp) : substitute(solns, s) - (f:False) : exp - (exp) : - map(substitute{solns, _}, exp) - -defn dataflow (eqns: HashTable<Symbol, False|Exp>, solns: HashTable<Symbol,Exp>) : - var progress?:True|False = false - for entry in eqns do : - if value(entry) != false : - val v = key(entry) - val exp = simplify(substitute(solns, value(entry) as Exp)) - if occurs?(v, exp) : - eqns[v] = exp - else : - eqns[v] = false - solns[v] = exp - progress? = true - progress? - -defn fixpoint (eqns: HashTable<Symbol, False|Exp>, solns: HashTable<Symbol,Exp>) : - label<False|True> break : - for v in keys(eqns) do : - if eqns[v] != false : - val fix-eqns = fixpoint-eqns(v, eqns) - val has-fixpoint? = all?(contains-only-max?{value(_)}, fix-eqns) - if has-fixpoint? : - val soln = solve-fixpoint(fix-eqns) - for s in soln do : - solns[key(s)] = ELit(value(s)) - eqns[key(s)] = false - break(true) - false - -defn fixpoint-eqns (v: Symbol, eqns: HashTable<Symbol,False|Exp>) : - val vs = HashTable<Symbol,Exp>(symbol-hash) - defn loop (v: Symbol) : - if not key?(vs, v) : - val eqn = eqns[v] as Exp - vs[v] = eqn - do(loop, freevars(eqn)) - loop(v) - to-list(vs) - -defn solve-fixpoint (eqns: List<KeyValue<Symbol,Exp>>) : - ;Solve for fixpoint - val sol = HashTable<Symbol,Int>(symbol-hash) - do({sol[key(_)] = 0}, eqns) - defn loop () : - var progress?:True|False = false - for eqn in eqns do : - val v = key(eqn) - val x = eval(value(eqn), sol) - if x != sol[v] : - sol[v] = x - progress? = true - progress? - while loop() : false - - ;Return solutions - to-list(sol) - -defn backsubstitute (vs:Streamable<Symbol>, solns: HashTable<Symbol,Exp>) : - val widths = HashTable<Symbol,False|Int>(symbol-hash) - defn get-width (v:Symbol) : - if key?(solns, v) : - val vs = freevars(solns[v]) - ;Calculate dependencies - for v in vs do : - if not key?(widths, v) : - widths[v] = get-width(v) - ;Compute value - if none?({widths[_] == false}, vs) : - eval(solns[v], widths as HashTable<Symbol,Int>) - - ;Compute all widths - for v in vs do : - widths[v] = get-width(v) - - ;Return widths - to-list $ generate<WidthEqual> : - for entry in widths do : - if value(entry) != false : - yield $ WidthEqual(key(entry), ELit(value(entry) as Int)) - -public defn solve-widths (cs: Streamable<WConstraint>) : - ;Copy to new hashtable - val eqns = construct-eqns(cs) - val solns = HashTable<Symbol,Exp>(symbol-hash) - defn loop () : - dataflow(eqns, solns) or - fixpoint(eqns, solns) - while loop() : false - backsubstitute(keys(eqns), solns) - -;================= Main ===================================== -#if-defined(STANDALONE) : - defn main () : - val input = lex(commandline-arguments()) - error("No input file!") when length(input) < 2 - val cs = read(to-string(input[1])) - do(println, solve-widths(cs)) - - main() -;============================================================ - |