Remove stanza (#231)

* Removed stanza implementation/tests.

In the future we can move the stanza tests over, but for now they should
be deleted.

* Added back integration .fir files

* Added Makefile to give Travis hooks

* Added firrtl script (was ignored before)

5 files changed, 0 insertions, 117 deletions

diff --git a/test/passes/split-exp/gcd.fir b/test/passes/split-exp/gcd.fir
deleted file mode 100644
index 4b42d007..00000000
--- a/test/passes/split-exp/gcd.fir
+++ /dev/null
@@ -1,49 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-
-;CHECK: Split Expressions
-circuit top :
-   module subtracter :
-      input x : UInt
-      input y : UInt
-      output q : UInt
-      q <= tail(sub(x, y),1)
-   module gcd :
-      input clk : Clock
-      input reset : UInt<1>
-      input a : UInt<16>
-      input b : UInt<16>
-      input e : UInt<1>
-      output z : UInt<16>
-      reg x : UInt,clk with :
-         reset => (reset,UInt(0))
-      reg y : UInt,clk with :
-         reset => (reset,UInt(42))
-      when gt(x, y) :
-         inst s of subtracter
-         s.x <= x
-         s.y <= y
-         x <= s.q
-      else :
-         inst s2 of subtracter
-         s2.x <= x
-         s2.y <= y
-         y <= s2.q
-      when e :
-         x <= a
-         y <= b
-      z <= x
-   module top :
-      input clk : Clock
-      input reset : UInt<1>
-      input a : UInt<16>
-      input b : UInt<16>
-      output z : UInt
-      inst i of gcd
-      i.clk <= clk
-      i.reset <= reset
-      i.a <= a
-      i.b <= b
-      i.e <= UInt(1)
-      z <= i.z
-
-; CHECK: Finished Split Expressions
diff --git a/test/passes/split-exp/primop.fir b/test/passes/split-exp/primop.fir
deleted file mode 100644
index cdbd4e77..00000000
--- a/test/passes/split-exp/primop.fir
+++ /dev/null
@@ -1,21 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-
-;CHECK: Split Expressions
-circuit Top :
-   module Top :
-      output out : UInt<1>
-
-      wire m : UInt<1>[3]
-      m[0] <= UInt(0)
-      m[1] <= UInt(0)
-      m[2] <= UInt(0)
-
-      wire x : UInt<1>
-      x <= not(UInt(1))
-      wire a : UInt<1>
-      a <= m[x]
-      
-      out <= a
-
-
-
diff --git a/test/passes/split-exp/print-args.fir b/test/passes/split-exp/print-args.fir
deleted file mode 100644
index df21949d..00000000
--- a/test/passes/split-exp/print-args.fir
+++ /dev/null
@@ -1,14 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-
-; CHECK: Split Expressions
-; CHECK: node GEN_0 = and(a, b)
-; CHECK: printf(clk, UInt<1>("h1"), "%d\n", GEN_0)
-
-circuit Bug :
-  module Bug :
-    input clk : Clock
-    input a : UInt<1>
-    input b : UInt<1>
-
-    printf(clk, UInt<1>(1), "%d\n", and(a, b))
-
diff --git a/test/passes/split-exp/split-and.fir b/test/passes/split-exp/split-and.fir
deleted file mode 100644
index 8eb4bdab..00000000
--- a/test/passes/split-exp/split-and.fir
+++ /dev/null
@@ -1,8 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s
-
-; CHECK: Done!
-circuit Top :
-   module Top :
-      input a : SInt<2>
-      output c : UInt<2>
-      c <= and(a,asSInt(UInt(2)))
diff --git a/test/passes/split-exp/split-in-when.fir b/test/passes/split-exp/split-in-when.fir
deleted file mode 100644
index 47caa16b..00000000
--- a/test/passes/split-exp/split-in-when.fir
+++ /dev/null
@@ -1,25 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-
-;CHECK: Split Expressions
-circuit Top :
-   module Top :
-      input p : UInt<1>
-      input clk : Clock
-      input a : UInt<10>
-      input b : UInt<10>
-      input c : UInt<10>
-      
-      reg out : UInt<10>,clk with :
-         reset => (p,a)
-
-      when bits(tail(sub(a,c),1),3,3) : out <= mux(eq(bits(UInt(32),4,0),UInt(13)),tail(add(a,tail(add(b,c),1)),1),tail(sub(c,b),1))
-
-;CHECK: node GEN_0 = subw(a, c)
-;CHECK: node GEN_1 = bits(GEN_0, 3, 3)
-;CHECK: node GEN_2 = eq(UInt<5>("h0"), UInt<4>("hd"))
-;CHECK: node GEN_3 = addw(b, c)
-;CHECK: node GEN_4 = addw(a, GEN_3)
-;CHECK: node GEN_5 = subw(c, b)
-;CHECK: out <= mux(GEN_1, mux(GEN_2, GEN_4, GEN_5), out)   
-
-;CHECK: Finished Split Expressions