WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadblock in assigning clocked ports

5 files changed, 15 insertions, 83 deletions

diff --git a/test/passes/resolve-genders/accessor.fir b/test/passes/resolve-genders/accessor.fir
deleted file mode 100644
index 64797ece..00000000
--- a/test/passes/resolve-genders/accessor.fir
+++ /dev/null
@@ -1,34 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p cg 2>&1 | tee %s.out | FileCheck %s
-
-;CHECK: Resolve Genders
-circuit top :
-   module top :
-      wire m : UInt<32>[2][2][2]
-      m[0][0][0] <= UInt(1)
-      m[1][0][0] <= UInt(1)
-      m[0][1][0] <= UInt(1)
-      m[1][1][0] <= UInt(1)
-      m[0][0][1] <= UInt(1)
-      m[1][0][1] <= UInt(1)
-      m[0][1][1] <= UInt(1)
-      m[1][1][1] <= UInt(1)
-      wire i : UInt
-      i <= UInt(1)
-      infer accessor a = m[i] ;CHECK: accessor a = m@<g:m>[i@<g:m>]@<g:m>
-      infer accessor b = a[i] ;CHECK: accessor b = a@<g:m>[i@<g:m>]@<g:m>
-      infer accessor c = b[i] ;CHECK: accessor c = b@<g:m>[i@<g:m>]@<g:m>
-      wire j : UInt
-      j <= c
-
-      infer accessor x = m[i] ;CHECK: accessor x = m@<g:f>[i@<g:m>]@<g:f>
-      x[0][0] <= UInt(1)
-      x[1][0] <= UInt(1)
-      x[0][1] <= UInt(1)
-      x[1][1] <= UInt(1)
-      infer accessor y = x[i] ;CHECK: accessor y = x@<g:f>[i@<g:m>]@<g:f>
-      y[0] <= UInt(1)
-      y[1] <= UInt(1)
-      infer accessor z = y[i] ;CHECK: accessor z = y@<g:f>[i@<g:m>]@<g:f>
-      z <= j
-
-; CHECK: Finished Resolve Genders
diff --git a/test/passes/resolve-genders/gcd.fir b/test/passes/resolve-genders/gcd.fir
index 85b6474b..4d7772d9 100644
--- a/test/passes/resolve-genders/gcd.fir
+++ b/test/passes/resolve-genders/gcd.fir
@@ -16,15 +16,12 @@ circuit top :
       input reset : UInt<1>
       output z : UInt<16>
       output v : UInt<1>
-      reg x : UInt,clk,reset
-      reg y : UInt,clk,reset
+      reg x : UInt,clk,reset,UInt(0)
+      reg y : UInt,clk,reset,UInt(42)
 ; CHECK: reg x : UInt
-      onreset x <= UInt(0)
-      onreset y <= UInt(42)
       when gt(x, y) :
-      ;CHECK: when gt(x@<g:m>, y@<g:m>) :
+      ;CHECK: when gt(x@<g:m>, y@<g:m>)@<g:m> :
          inst s of subtracter
-         ;CHECK: inst s of subtracter@<g:m>
          s.x <= x
          s.y <= y
          x <= s.z
diff --git a/test/passes/resolve-genders/ports.fir b/test/passes/resolve-genders/ports.fir
index 57c8721d..246fb9ac 100644
--- a/test/passes/resolve-genders/ports.fir
+++ b/test/passes/resolve-genders/ports.fir
@@ -11,11 +11,11 @@ circuit top :
       output ready : UInt<1>
    module top: 
       wire connect : { data : UInt<16>, flip ready: UInt<1> }
-      inst src of source         ;CHECK: inst src of source@<g:m>
-      inst snk of sink           ;CHECK: inst snk of sink@<g:m>
-      connect.data <= src.data   ;CHECK: connect@<g:f>.data@<g:f> := src@<g:m>.data@<g:m>
-      src.ready <= connect.ready ;CHECK: src@<g:m>.ready@<g:f> := connect@<g:f>.ready@<g:m>
-      snk.data <= connect.data   ;CHECK: snk@<g:m>.data@<g:f> := connect@<g:m>.data@<g:m>
-      connect.ready <= snk.ready ;CHECK: connect@<g:m>.ready@<g:f> := snk@<g:m>.ready@<g:m>
+      inst src of source         
+      inst snk of sink          
+      connect.data <= src.data   ;CHECK: connect@<g:f>.data@<g:f> <= src@<g:m>.data@<g:m>
+      src.ready <= connect.ready ;CHECK: src@<g:m>.ready@<g:f> <= connect@<g:f>.ready@<g:m>
+      snk.data <= connect.data   ;CHECK: snk@<g:m>.data@<g:f> <= connect@<g:m>.data@<g:m>
+      connect.ready <= snk.ready ;CHECK: connect@<g:m>.ready@<g:f> <= snk@<g:m>.ready@<g:m>
 
 ; CHECK: Finished Resolve Genders
diff --git a/test/passes/resolve-genders/rdwraccessor.fir b/test/passes/resolve-genders/rdwraccessor.fir
deleted file mode 100644
index 35f88071..00000000
--- a/test/passes/resolve-genders/rdwraccessor.fir
+++ /dev/null
@@ -1,31 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p cg 2>&1 | tee %s.out | FileCheck %s
-
-;CHECK: Resolve Genders
-circuit top :
-   module top :
-      wire m : UInt<32>[2][2][2]
-      m[0][0][0] <= UInt(1)
-      m[1][0][0] <= UInt(1)
-      m[0][1][0] <= UInt(1)
-      m[1][1][0] <= UInt(1)
-      m[0][0][1] <= UInt(1)
-      m[1][0][1] <= UInt(1)
-      m[0][1][1] <= UInt(1)
-      m[1][1][1] <= UInt(1)
-      wire i : UInt
-      i <= UInt(1)
-      rdwr accessor a = m[i] ;CHECK: accessor a = m@<g:b>[i@<g:m>]@<g:b>
-      rdwr accessor b = a[i] ;CHECK: accessor b = a@<g:b>[i@<g:m>]@<g:b>
-      rdwr accessor c = b[i] ;CHECK: accessor c = b@<g:b>[i@<g:m>]@<g:b>
-      wire j : UInt
-      j <= c
-      c <= j
-
-      rdwr accessor x = m[i] ;CHECK: accessor x = m@<g:b>[i@<g:m>]@<g:b>
-      rdwr accessor y = x[i] ;CHECK: accessor y = x@<g:b>[i@<g:m>]@<g:b>
-      rdwr accessor z = y[i] ;CHECK: accessor z = y@<g:b>[i@<g:m>]@<g:b>
-      z <= j
-      j <= z
-
-; CHECK: Finished Resolve Genders
-; CHECK: Done!
diff --git a/test/passes/resolve-genders/subbundle.fir b/test/passes/resolve-genders/subbundle.fir
index f734d08b..0d0dd574 100644
--- a/test/passes/resolve-genders/subbundle.fir
+++ b/test/passes/resolve-genders/subbundle.fir
@@ -1,13 +1,13 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s
 
-;CHECK: Lower To Ground
+;CHECK: Lower Types
 circuit top :
    module top :
       input clk : Clock
       input reset : UInt<1>
       wire w : { flip x : UInt<10>}
-      reg r : { flip x : UInt<10>},clk,reset
-      w <= r     ; CHECK r$x := w$x
-      w.x <= r.x ; CHECK w$x := r$x
-; CHECK: Finished Lower To Ground
+      reg r : { flip x : UInt<10>},clk,reset,w
+      w <= r     ; CHECK r_x := w_x
+      w.x <= r.x ; CHECK w_x := r_x
+; CHECK: Finished Lower Types