New memory works with verilog. Slowly changing tests and fixing bugs.

Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables

15 files changed, 137 insertions, 137 deletions

diff --git a/test/passes/jacktest/ALUTop.fir b/test/passes/jacktest/ALUTop.fir
index ef1ac7a9..74abe0bd 100644
--- a/test/passes/jacktest/ALUTop.fir
+++ b/test/passes/jacktest/ALUTop.fir
@@ -49,12 +49,12 @@ circuit ALUTop :
     node T_194 = eq(UInt<4>(0), alu_op)
     node oot = mux(T_194, T_157, T_193)
     node T_195 = bits(oot, 31, 0)
-    out := T_195
+    out <= T_195
     node T_196 = bit(alu_op, 0)
     node T_197 = subw(UInt<1>(0), B)
     node T_198 = mux(T_196, T_197, B)
     node T_199 = addw(A, T_198)
-    sum := T_199
+    sum <= T_199
   module ALUdec : 
     input opcode : UInt<7>
     input funct : UInt<3>
@@ -97,7 +97,7 @@ circuit ALUTop :
     node T_232 = mux(T_231, UInt<4>(0), T_230)
     node T_233 = eq(UInt<7>(55), opcode)
     node alu_op2 = mux(T_233, UInt<4>(11), T_232)
-    alu_op := alu_op2
+    alu_op <= alu_op2
   module ALUTop : 
     input B : UInt<32>
     output out : UInt<32>
@@ -108,10 +108,10 @@ circuit ALUTop :
     
     inst alu of ALU
     inst alu_dec of ALUdec
-    alu_dec.opcode := opcode
-    alu_dec.funct := funct
-    alu_dec.add_rshift_type := add_rshift_type
-    alu.A := A
-    alu.B := B
-    out := alu.out
-    alu.alu_op := alu_dec.alu_op
+    alu_dec.opcode <= opcode
+    alu_dec.funct <= funct
+    alu_dec.add_rshift_type <= add_rshift_type
+    alu.A <= A
+    alu.B <= B
+    out <= alu.out
+    alu.alu_op <= alu_dec.alu_op
diff --git a/test/passes/jacktest/ComplexAssign.fir b/test/passes/jacktest/ComplexAssign.fir
index e3858765..9ce51652 100644
--- a/test/passes/jacktest/ComplexAssign.fir
+++ b/test/passes/jacktest/ComplexAssign.fir
@@ -7,9 +7,9 @@ circuit ComplexAssign :
     input e : UInt<1>
     when e : 
       wire T_18 : {re : UInt<10>, im : UInt<10>}
-      T_18 := in
-      out.re := T_18.re
-      out.im := T_18.im
+      T_18 <= in
+      out.re <= T_18.re
+      out.im <= T_18.im
     else : 
-      out.re := UInt<1>(0)
-      out.im := UInt<1>(0)
+      out.re <= UInt<1>(0)
+      out.im <= UInt<1>(0)
diff --git a/test/passes/jacktest/Counter.fir b/test/passes/jacktest/Counter.fir
index a04ddf2f..db2b5d62 100644
--- a/test/passes/jacktest/Counter.fir
+++ b/test/passes/jacktest/Counter.fir
@@ -9,10 +9,10 @@ circuit Counter :
     input amt : UInt<4>
     
     reg T_13 : UInt<8>,clk,reset
-    onreset T_13 := UInt<8>(0)
+    onreset T_13 <= UInt<8>(0)
     when inc : 
       node T_14 = addw(T_13, amt)
       node T_15 = gt(T_14, UInt<8>(255))
       node T_16 = mux(T_15, UInt<1>(0), T_14)
-      T_13 := T_16
-    tot := T_13
+      T_13 <= T_16
+    tot <= T_13
diff --git a/test/passes/jacktest/EnableShiftRegister.fir b/test/passes/jacktest/EnableShiftRegister.fir
index 902098b7..7937d37f 100644
--- a/test/passes/jacktest/EnableShiftRegister.fir
+++ b/test/passes/jacktest/EnableShiftRegister.fir
@@ -9,16 +9,16 @@ circuit EnableShiftRegister :
     input shift : UInt<1>
     
     reg r0 : UInt<4>,clk,reset
-    onreset r0 := UInt<4>(0)
+    onreset r0 <= UInt<4>(0)
     reg r1 : UInt<4>,clk,reset
-    onreset r1 := UInt<4>(0)
+    onreset r1 <= UInt<4>(0)
     reg r2 : UInt<4>,clk,reset
-    onreset r2 := UInt<4>(0)
+    onreset r2 <= UInt<4>(0)
     reg r3 : UInt<4>,clk,reset
-    onreset r3 := UInt<4>(0)
+    onreset r3 <= UInt<4>(0)
     when shift : 
-      r0 := in
-      r1 := r0
-      r2 := r1
-      r3 := r2
-    out := r3
+      r0 <= in
+      r1 <= r0
+      r2 <= r1
+      r3 <= r2
+    out <= r3
diff --git a/test/passes/jacktest/LFSR16.fir b/test/passes/jacktest/LFSR16.fir
index b8e31e99..770ac3e6 100644
--- a/test/passes/jacktest/LFSR16.fir
+++ b/test/passes/jacktest/LFSR16.fir
@@ -8,7 +8,7 @@ circuit LFSR16 :
     input reset : UInt<1>
     
     reg res : UInt<16>,clk,reset
-    onreset res := UInt<16>(1)
+    onreset res <= UInt<16>(1)
     when inc : 
       node T_16 = bit(res, 0)
       node T_17 = bit(res, 2)
@@ -19,5 +19,5 @@ circuit LFSR16 :
       node T_22 = xor(T_20, T_21)
       node T_23 = bits(res, 15, 1)
       node T_24 = cat(T_22, T_23)
-      res := T_24
-    out := res
+      res <= T_24
+    out <= res
diff --git a/test/passes/jacktest/MemorySearch.fir b/test/passes/jacktest/MemorySearch.fir
index be6b3274..1e07596c 100644
--- a/test/passes/jacktest/MemorySearch.fir
+++ b/test/passes/jacktest/MemorySearch.fir
@@ -10,26 +10,26 @@ circuit MemorySearch :
     output done : UInt<1>
     
     reg index : UInt<3>,clk,reset
-    onreset index := UInt<3>(0)
+    onreset index <= UInt<3>(0)
     wire elts : UInt<4>[7]
-    elts[0] := UInt<4>(0)
-    elts[1] := UInt<4>(4)
-    elts[2] := UInt<4>(15)
-    elts[3] := UInt<4>(14)
-    elts[4] := UInt<4>(2)
-    elts[5] := UInt<4>(5)
-    elts[6] := UInt<4>(13)
+    elts[0] <= UInt<4>(0)
+    elts[1] <= UInt<4>(4)
+    elts[2] <= UInt<4>(15)
+    elts[3] <= UInt<4>(14)
+    elts[4] <= UInt<4>(2)
+    elts[5] <= UInt<4>(5)
+    elts[6] <= UInt<4>(13)
     infer accessor elt = elts[index]
     node T_35 = not(en)
     node T_36 = eq(elt, target)
     node T_37 = eq(index, UInt<3>(7))
     node T_38 = or(T_36, T_37)
     node end = and(T_35, T_38)
-    when en : index := UInt<1>(0)
+    when en : index <= UInt<1>(0)
     else : 
       node T_39 = not(end)
       when T_39 : 
         node T_40 = addw(index, UInt<1>(1))
-        index := T_40
-    done := end
-    address := index
+        index <= T_40
+    done <= end
+    address <= index
diff --git a/test/passes/jacktest/ModuleVec.fir b/test/passes/jacktest/ModuleVec.fir
index 8ac27aaf..9a8e7f2c 100644
--- a/test/passes/jacktest/ModuleVec.fir
+++ b/test/passes/jacktest/ModuleVec.fir
@@ -6,13 +6,13 @@ circuit ModuleVec :
     output out : UInt<32>
     
     node T_33 = addw(in, UInt<1>(1))
-    out := T_33
+    out <= T_33
   module PlusOne_25 : 
     input in : UInt<32>
     output out : UInt<32>
     
     node T_34 = addw(in, UInt<1>(1))
-    out := T_34
+    out <= T_34
   module ModuleVec : 
     input ins : UInt<32>[2]
     output outs : UInt<32>[2]
@@ -20,9 +20,9 @@ circuit ModuleVec :
     inst T_35 of PlusOne
     inst T_36 of PlusOne_25
     wire pluses : {flip in : UInt<32>, out : UInt<32>}[2]
-    pluses[0] := T_35
-    pluses[1] := T_36
-    pluses[0].in := ins[0]
-    outs[0] := pluses[0].out
-    pluses[1].in := ins[1]
-    outs[1] := pluses[1].out
+    pluses[0] <= T_35
+    pluses[1] <= T_36
+    pluses[0].in <= ins[0]
+    outs[0] <= pluses[0].out
+    pluses[1].in <= ins[1]
+    outs[1] <= pluses[1].out
diff --git a/test/passes/jacktest/Mul.fir b/test/passes/jacktest/Mul.fir
index 51753ece..8a3223e7 100644
--- a/test/passes/jacktest/Mul.fir
+++ b/test/passes/jacktest/Mul.fir
@@ -7,23 +7,23 @@ circuit Mul :
     output z : UInt<4>
     
     wire tbl : UInt<4>[16]
-    tbl[0] := UInt<4>(0)
-    tbl[1] := UInt<4>(0)
-    tbl[2] := UInt<4>(0)
-    tbl[3] := UInt<4>(0)
-    tbl[4] := UInt<4>(0)
-    tbl[5] := UInt<4>(1)
-    tbl[6] := UInt<4>(2)
-    tbl[7] := UInt<4>(3)
-    tbl[8] := UInt<4>(0)
-    tbl[9] := UInt<4>(2)
-    tbl[10] := UInt<4>(4)
-    tbl[11] := UInt<4>(6)
-    tbl[12] := UInt<4>(0)
-    tbl[13] := UInt<4>(3)
-    tbl[14] := UInt<4>(6)
-    tbl[15] := UInt<4>(9)
+    tbl[0] <= UInt<4>(0)
+    tbl[1] <= UInt<4>(0)
+    tbl[2] <= UInt<4>(0)
+    tbl[3] <= UInt<4>(0)
+    tbl[4] <= UInt<4>(0)
+    tbl[5] <= UInt<4>(1)
+    tbl[6] <= UInt<4>(2)
+    tbl[7] <= UInt<4>(3)
+    tbl[8] <= UInt<4>(0)
+    tbl[9] <= UInt<4>(2)
+    tbl[10] <= UInt<4>(4)
+    tbl[11] <= UInt<4>(6)
+    tbl[12] <= UInt<4>(0)
+    tbl[13] <= UInt<4>(3)
+    tbl[14] <= UInt<4>(6)
+    tbl[15] <= UInt<4>(9)
     node T_42 = shl(x, 2)
     node T_43 = or(T_42, y)
     infer accessor T_44 = tbl[T_43]
-    z := T_44
+    z <= T_44
diff --git a/test/passes/jacktest/RegisterVecShift.fir b/test/passes/jacktest/RegisterVecShift.fir
index 02ae03b5..eb2a0f34 100644
--- a/test/passes/jacktest/RegisterVecShift.fir
+++ b/test/passes/jacktest/RegisterVecShift.fir
@@ -12,19 +12,19 @@ circuit RegisterVecShift :
     reg delays : UInt<4>[4],clk,reset
     when reset : 
       wire T_33 : UInt<4>[4]
-      T_33[0] := UInt<4>(0)
-      T_33[1] := UInt<4>(0)
-      T_33[2] := UInt<4>(0)
-      T_33[3] := UInt<4>(0)
-      delays := T_33
+      T_33[0] <= UInt<4>(0)
+      T_33[1] <= UInt<4>(0)
+      T_33[2] <= UInt<4>(0)
+      T_33[3] <= UInt<4>(0)
+      delays <= T_33
     when load : 
-      delays[0] := ins[0]
-      delays[1] := ins[1]
-      delays[2] := ins[2]
-      delays[3] := ins[3]
+      delays[0] <= ins[0]
+      delays[1] <= ins[1]
+      delays[2] <= ins[2]
+      delays[3] <= ins[3]
     else : when shift : 
-        delays[0] := ins[0]
-        delays[1] := delays[0]
-        delays[2] := delays[1]
-        delays[3] := delays[2]
-    out := delays[3]
+        delays[0] <= ins[0]
+        delays[1] <= delays[0]
+        delays[2] <= delays[1]
+        delays[3] <= delays[2]
+    out <= delays[3]
diff --git a/test/passes/jacktest/Rom.fir b/test/passes/jacktest/Rom.fir
index 382ca5c9..6e4b3cc7 100644
--- a/test/passes/jacktest/Rom.fir
+++ b/test/passes/jacktest/Rom.fir
@@ -6,21 +6,21 @@ circuit Rom :
     input addr : UInt<4>
     
     wire r : UInt<5>[16]
-    r[0] := UInt<5>(0)
-    r[1] := UInt<5>(2)
-    r[2] := UInt<5>(4)
-    r[3] := UInt<5>(6)
-    r[4] := UInt<5>(8)
-    r[5] := UInt<5>(10)
-    r[6] := UInt<5>(12)
-    r[7] := UInt<5>(14)
-    r[8] := UInt<5>(16)
-    r[9] := UInt<5>(18)
-    r[10] := UInt<5>(20)
-    r[11] := UInt<5>(22)
-    r[12] := UInt<5>(24)
-    r[13] := UInt<5>(26)
-    r[14] := UInt<5>(28)
-    r[15] := UInt<5>(30)
+    r[0] <= UInt<5>(0)
+    r[1] <= UInt<5>(2)
+    r[2] <= UInt<5>(4)
+    r[3] <= UInt<5>(6)
+    r[4] <= UInt<5>(8)
+    r[5] <= UInt<5>(10)
+    r[6] <= UInt<5>(12)
+    r[7] <= UInt<5>(14)
+    r[8] <= UInt<5>(16)
+    r[9] <= UInt<5>(18)
+    r[10] <= UInt<5>(20)
+    r[11] <= UInt<5>(22)
+    r[12] <= UInt<5>(24)
+    r[13] <= UInt<5>(26)
+    r[14] <= UInt<5>(28)
+    r[15] <= UInt<5>(30)
     infer accessor T_39 = r[addr]
-    out := T_39
+    out <= T_39
diff --git a/test/passes/jacktest/Stack.fir b/test/passes/jacktest/Stack.fir
index f4fd896c..ed718331 100644
--- a/test/passes/jacktest/Stack.fir
+++ b/test/passes/jacktest/Stack.fir
@@ -12,26 +12,26 @@ circuit Stack :
     
     cmem stack_mem : UInt<32>[16],clk
     reg sp : UInt<5>,clk,reset
-    onreset sp := UInt<5>(0)
+    onreset sp <= UInt<5>(0)
     reg out : UInt<32>,clk,reset
-    onreset out := UInt<32>(0)
+    onreset out <= UInt<32>(0)
     when en : 
       node T_30 = lt(sp, UInt<5>(16))
       node T_31 = and(push, T_30)
       when T_31 : 
         infer accessor T_32 = stack_mem[sp]
-        T_32 := dataIn
+        T_32 <= dataIn
         node T_33 = addw(sp, UInt<1>(1))
-        sp := T_33
+        sp <= T_33
       else : 
         node T_34 = gt(sp, UInt<1>(0))
         node T_35 = and(pop, T_34)
         when T_35 : 
           node T_36 = subw(sp, UInt<1>(1))
-          sp := T_36
+          sp <= T_36
       node T_37 = gt(sp, UInt<1>(0))
       when T_37 : 
         node T_38 = subw(sp, UInt<1>(1))
         infer accessor T_39 = stack_mem[T_38]
-        out := T_39
-    dataOut := out
+        out <= T_39
+    dataOut <= out
diff --git a/test/passes/jacktest/Tbl.fir b/test/passes/jacktest/Tbl.fir
index 22c5fd5c..4ae87360 100644
--- a/test/passes/jacktest/Tbl.fir
+++ b/test/passes/jacktest/Tbl.fir
@@ -9,11 +9,11 @@ circuit Tbl :
     input we : UInt<1>
     
     cmem m : UInt<10>[256],clk
-    o := UInt<1>(0)
+    o <= UInt<1>(0)
     when we : 
       infer accessor T_13 = m[i]
       node T_14 = bits(d, 9, 0)
-      T_13 := T_14
+      T_13 <= T_14
     else : 
       infer accessor T_15 = m[i]
-      o := T_15
+      o <= T_15
diff --git a/test/passes/jacktest/VendingMachine.fir b/test/passes/jacktest/VendingMachine.fir
index 338df3f4..5ecfe522 100644
--- a/test/passes/jacktest/VendingMachine.fir
+++ b/test/passes/jacktest/VendingMachine.fir
@@ -9,24 +9,24 @@ circuit VendingMachine :
     input reset : UInt<1>
     
     reg state : UInt<3>,clk,reset
-    onreset state := UInt<3>(0)
+    onreset state <= UInt<3>(0)
     node T_22 = eq(state, UInt<3>(0))
     when T_22 : 
-      when nickel : state := UInt<3>(1)
-      when dime : state := UInt<3>(2)
+      when nickel : state <= UInt<3>(1)
+      when dime : state <= UInt<3>(2)
     node T_23 = eq(state, UInt<3>(1))
     when T_23 : 
-      when nickel : state := UInt<3>(2)
-      when dime : state := UInt<3>(3)
+      when nickel : state <= UInt<3>(2)
+      when dime : state <= UInt<3>(3)
     node T_24 = eq(state, UInt<3>(2))
     when T_24 : 
-      when nickel : state := UInt<3>(3)
-      when dime : state := UInt<3>(4)
+      when nickel : state <= UInt<3>(3)
+      when dime : state <= UInt<3>(4)
     node T_25 = eq(state, UInt<3>(3))
     when T_25 : 
-      when nickel : state := UInt<3>(4)
-      when dime : state := UInt<3>(4)
+      when nickel : state <= UInt<3>(4)
+      when dime : state <= UInt<3>(4)
     node T_26 = eq(state, UInt<3>(4))
-    when T_26 : state := UInt<3>(0)
+    when T_26 : state <= UInt<3>(0)
     node T_27 = eq(state, UInt<3>(4))
-    valid := T_27
+    valid <= T_27
diff --git a/test/passes/jacktest/gcd.fir b/test/passes/jacktest/gcd.fir
index c461efe3..99667b3b 100644
--- a/test/passes/jacktest/gcd.fir
+++ b/test/passes/jacktest/gcd.fir
@@ -15,13 +15,13 @@ circuit GCD :
     node T_17 = gt(x, y)
     when T_17 : 
       node T_18 = subw(x, y)
-      x := T_18
+      x <= T_18
     else : 
       node T_19 = subw(y, x)
-      y := T_19
+      y <= T_19
     when e : 
-      x := a
-      y := b
-    z := x
+      x <= a
+      y <= b
+    z <= x
     node T_20 = eq(y, UInt<1>(0))
-    v := T_20
+    v <= T_20
diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir
index a28dc5a5..fdc80ee1 100644
--- a/test/passes/jacktest/risc.fir
+++ b/test/passes/jacktest/risc.fir
@@ -14,7 +14,7 @@ circuit Risc :
     cmem file : UInt<32>[256],clk
     cmem code : UInt<32>[256],clk
     reg pc : UInt<8>,clk,reset
-    onreset pc := UInt<8>(0)
+    onreset pc <= UInt<8>(0)
     infer accessor inst = code[pc]
     node op = bits(inst, 31, 24)
     node rci = bits(inst, 23, 16)
@@ -27,28 +27,28 @@ circuit Risc :
     infer accessor T_54 = file[rbi]
     node rb = mux(T_53, UInt<1>(0), T_54)
     wire rc : UInt<32>
-    valid := UInt<1>(0)
-    out := UInt<1>(0)
-    rc := UInt<1>(0)
+    valid <= UInt<1>(0)
+    out <= UInt<1>(0)
+    rc <= UInt<1>(0)
     when isWr : 
       infer accessor T_55 = code[wrAddr]
-      T_55 := wrData
-    else : when boot : pc := UInt<1>(0)
+      T_55 <= wrData
+    else : when boot : pc <= UInt<1>(0)
       else : 
         node T_56 = eq(UInt<1>(0), op)
         when T_56 : 
           node T_57 = addw(ra, rb)
-          rc := T_57
+          rc <= T_57
         node T_58 = eq(UInt<1>(1), op)
         when T_58 : 
           node T_59 = shl(rai, 8)
           node T_60 = or(T_59, rbi)
-          rc := T_60
-        out := rc
+          rc <= T_60
+        out <= rc
         node T_61 = eq(rci, UInt<8>(255))
-        when T_61 : valid := UInt<1>(1)
+        when T_61 : valid <= UInt<1>(1)
         else : 
           infer accessor T_62 = file[rci]
-          T_62 := rc
+          T_62 <= rc
         node T_63 = addw(pc, UInt<1>(1))
-        pc := T_63
+        pc <= T_63