Remove stanza (#231)

* Removed stanza implementation/tests.

In the future we can move the stanza tests over, but for now they should
be deleted.

* Added back integration .fir files

* Added Makefile to give Travis hooks

* Added firrtl script (was ignored before)

1 files changed, 0 insertions, 32 deletions

diff --git a/test/passes/jacktest/VendingMachine.fir b/test/passes/jacktest/VendingMachine.fir
deleted file mode 100644
index d7822a17..00000000
--- a/test/passes/jacktest/VendingMachine.fir
+++ /dev/null
@@ -1,32 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-;CHECK: Done!
-circuit VendingMachine : 
-  module VendingMachine : 
-    output valid : UInt<1>
-    input nickel : UInt<1>
-    input dime : UInt<1>
-    input clk : Clock
-    input reset : UInt<1>
-    
-    reg state : UInt<3>,clk with :
-       reset => (reset,UInt<3>(0))
-    node T_22 = eq(state, UInt<3>(0))
-    when T_22 : 
-      when nickel : state <= UInt<3>(1)
-      when dime : state <= UInt<3>(2)
-    node T_23 = eq(state, UInt<3>(1))
-    when T_23 : 
-      when nickel : state <= UInt<3>(2)
-      when dime : state <= UInt<3>(3)
-    node T_24 = eq(state, UInt<3>(2))
-    when T_24 : 
-      when nickel : state <= UInt<3>(3)
-      when dime : state <= UInt<3>(4)
-    node T_25 = eq(state, UInt<3>(3))
-    when T_25 : 
-      when nickel : state <= UInt<3>(4)
-      when dime : state <= UInt<3>(4)
-    node T_26 = eq(state, UInt<3>(4))
-    when T_26 : state <= UInt<3>(0)
-    node T_27 = eq(state, UInt<3>(4))
-    valid <= T_27