New memory works with verilog. Slowly changing tests and fixing bugs.

Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables

1 files changed, 7 insertions, 7 deletions

diff --git a/test/passes/jacktest/Stack.fir b/test/passes/jacktest/Stack.fir
index f4fd896c..ed718331 100644
--- a/test/passes/jacktest/Stack.fir
+++ b/test/passes/jacktest/Stack.fir
@@ -12,26 +12,26 @@ circuit Stack :
     
     cmem stack_mem : UInt<32>[16],clk
     reg sp : UInt<5>,clk,reset
-    onreset sp := UInt<5>(0)
+    onreset sp <= UInt<5>(0)
     reg out : UInt<32>,clk,reset
-    onreset out := UInt<32>(0)
+    onreset out <= UInt<32>(0)
     when en : 
       node T_30 = lt(sp, UInt<5>(16))
       node T_31 = and(push, T_30)
       when T_31 : 
         infer accessor T_32 = stack_mem[sp]
-        T_32 := dataIn
+        T_32 <= dataIn
         node T_33 = addw(sp, UInt<1>(1))
-        sp := T_33
+        sp <= T_33
       else : 
         node T_34 = gt(sp, UInt<1>(0))
         node T_35 = and(pop, T_34)
         when T_35 : 
           node T_36 = subw(sp, UInt<1>(1))
-          sp := T_36
+          sp <= T_36
       node T_37 = gt(sp, UInt<1>(0))
       when T_37 : 
         node T_38 = subw(sp, UInt<1>(1))
         infer accessor T_39 = stack_mem[T_38]
-        out := T_39
-    dataOut := out
+        out <= T_39
+    dataOut <= out