diff options
| author | azidar | 2016-01-24 16:36:13 -0800 |
|---|---|---|
| committer | azidar | 2016-01-24 16:36:13 -0800 |
| commit | 5cb43f0cb9ff16a448f8f7b76698b569d2d63125 (patch) | |
| tree | 574704c808e24bafae32c8b544725d435eeb455a /test/passes/jacktest/Stack.fir | |
| parent | a899ff3606421467400380fc35a6035290bef791 (diff) | |
Fixed tests that broke from changing verilog backend and removing mask from write mport declaration
Diffstat (limited to 'test/passes/jacktest/Stack.fir')
| -rw-r--r-- | test/passes/jacktest/Stack.fir | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/passes/jacktest/Stack.fir b/test/passes/jacktest/Stack.fir index c3ec4921..319e87d5 100644 --- a/test/passes/jacktest/Stack.fir +++ b/test/passes/jacktest/Stack.fir @@ -17,7 +17,7 @@ circuit Stack : node T_30 = lt(sp, UInt<5>(16)) node T_31 = and(push, T_30) when T_31 : - write mport T_32 = stack_mem[sp],clk,UInt(1) + write mport T_32 = stack_mem[sp],clk T_32 <= dataIn node T_33 = addw(sp, UInt<1>(1)) sp <= T_33 |