diff options
| -rw-r--r-- | test/passes/jacktest/Stack.fir | 2 | ||||
| -rw-r--r-- | test/passes/jacktest/Tbl.fir | 2 | ||||
| -rw-r--r-- | test/passes/jacktest/risc.fir | 4 | ||||
| -rw-r--r-- | test/passes/remove-accesses/simple8.fir | 8 | ||||
| -rw-r--r-- | test/passes/to-verilog/rd-mem.fir | 64 |
5 files changed, 39 insertions, 41 deletions
diff --git a/test/passes/jacktest/Stack.fir b/test/passes/jacktest/Stack.fir index c3ec4921..319e87d5 100644 --- a/test/passes/jacktest/Stack.fir +++ b/test/passes/jacktest/Stack.fir @@ -17,7 +17,7 @@ circuit Stack : node T_30 = lt(sp, UInt<5>(16)) node T_31 = and(push, T_30) when T_31 : - write mport T_32 = stack_mem[sp],clk,UInt(1) + write mport T_32 = stack_mem[sp],clk T_32 <= dataIn node T_33 = addw(sp, UInt<1>(1)) sp <= T_33 diff --git a/test/passes/jacktest/Tbl.fir b/test/passes/jacktest/Tbl.fir index 9b259d0f..f760af68 100644 --- a/test/passes/jacktest/Tbl.fir +++ b/test/passes/jacktest/Tbl.fir @@ -11,7 +11,7 @@ circuit Tbl : cmem m : UInt<10>[256] o <= UInt<1>(0) when we : - write mport T_13 = m[i],clk,UInt(1) + write mport T_13 = m[i],clk node T_14 = bits(d, 9, 0) T_13 <= T_14 else : diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir index eb823321..0c11e785 100644 --- a/test/passes/jacktest/risc.fir +++ b/test/passes/jacktest/risc.fir @@ -30,7 +30,7 @@ circuit Risc : out <= UInt<1>(0) rc <= UInt<1>(0) when isWr : - write mport T_55 = code[wrAddr],clk,UInt(1) + write mport T_55 = code[wrAddr],clk T_55 <= wrData else : when boot : pc <= UInt<1>(0) else : @@ -47,7 +47,7 @@ circuit Risc : node T_61 = eq(rci, UInt<8>(255)) when T_61 : valid <= UInt<1>(1) else : - write mport T_62 = file[rci],clk,UInt(1) + write mport T_62 = file[rci],clk T_62 <= rc node T_63 = addw(pc, UInt<1>(1)) pc <= T_63 diff --git a/test/passes/remove-accesses/simple8.fir b/test/passes/remove-accesses/simple8.fir index ae0d1ffd..6b084ed3 100644 --- a/test/passes/remove-accesses/simple8.fir +++ b/test/passes/remove-accesses/simple8.fir @@ -52,7 +52,7 @@ circuit top : wire T_114 : UInt<128> T_114 <= UInt<1>("h00") T_114 <= T_113 - write mport T_116 = T_84[waddr],clock,UInt(1) + write mport T_116 = T_84[waddr],clock T_116 <= T_114 skip node T_118 = neq(T_66, UInt<1>("h00")) @@ -90,7 +90,7 @@ circuit top : wire T_154 : UInt<128> T_154 <= UInt<1>("h00") T_154 <= T_153 - write mport T_156 = T_124[waddr],clock,UInt(1) + write mport T_156 = T_124[waddr],clock T_156 <= T_154 skip node T_158 = neq(T_66, UInt<1>("h00")) @@ -159,7 +159,7 @@ circuit top : wire T_241 : UInt<128> T_241 <= UInt<1>("h00") T_241 <= T_240 - write mport T_243 = T_211[waddr],clock,UInt(1) + write mport T_243 = T_211[waddr],clock T_243 <= T_241 skip node T_245 = neq(T_193, UInt<1>("h00")) @@ -197,7 +197,7 @@ circuit top : wire T_281 : UInt<128> T_281 <= UInt<1>("h00") T_281 <= T_280 - write mport T_283 = T_251[waddr],clock,UInt(1) + write mport T_283 = T_251[waddr],clock T_283 <= T_281 skip node T_285 = neq(T_193, UInt<1>("h00")) diff --git a/test/passes/to-verilog/rd-mem.fir b/test/passes/to-verilog/rd-mem.fir index 7146f026..909b034b 100644 --- a/test/passes/to-verilog/rd-mem.fir +++ b/test/passes/to-verilog/rd-mem.fir @@ -18,36 +18,34 @@ circuit top : m.c.clk <= clk rdata <= m.c.data -; CHECK: module top( -; CHECK: output [31:0] rdata, -; CHECK: input [1:0] index, -; CHECK: input ren, -; CHECK: input clk, -; CHECK: ); -; CHECK: reg [31:0] m [0:3]; -; CHECK: wire [31:0] m_c_data; -; CHECK: wire [1:0] m_c_addr; -; CHECK: wire m_c_en; -; CHECK: wire m_c_clk; -; CHECK: reg [1:0] GEN; -; CHECK: reg GEN_1; -; CHECK: assign rdata = m_c_data -; CHECK: assign m_c_addr = index -; CHECK: assign m_c_en = ren -; CHECK: assign m_c_clk = clk -; CHECK: `ifndef SYNTHESIS -; CHECK: integer initvar; -; CHECK: initial begin -; CHECK: #0.002; -; CHECK: for (initvar = 0; initvar < 4; initvar = initvar+1) -; CHECK: m[initvar] = {1{$random}}; -; CHECK: end -; CHECK: `endif -; CHECK: always @(posedge m_c_clk) begin -; CHECK: GEN <= m_c_addr -; CHECK: GEN_1 <= m_c_en -; CHECK: if(GEN_1) begin -; CHECK: m_c_data <= m[GEN] -; CHECK: end -; CHECK: end -; CHECK: endmodule +;CHECK: module top( +;CHECK: output [31:0] rdata, +;CHECK: input [1:0] index, +;CHECK: input ren, +;CHECK: input clk +;CHECK: ); +;CHECK: reg [31:0] m [0:3]; +;CHECK: wire [31:0] m_c_data; +;CHECK: wire [1:0] m_c_addr; +;CHECK: wire m_c_en; +;CHECK: wire m_c_clk; +;CHECK: reg [1:0] GEN; +;CHECK: reg GEN_1; +;CHECK: assign rdata = m_c_data; +;CHECK: assign m_c_addr = index; +;CHECK: assign m_c_en = ren; +;CHECK: assign m_c_clk = clk; +;CHECK: assign m_c_data = m[GEN]; +;CHECK: `ifndef SYNTHESIS +;CHECK: integer initvar; +;CHECK: initial begin +;CHECK: #0.002; +;CHECK: for (initvar = 0; initvar < 4; initvar = initvar+1) +;CHECK: m[initvar] = {1{$random}}; +;CHECK: end +;CHECK: `endif +;CHECK: always @(posedge m_c_clk) begin +;CHECK: GEN <= m_c_addr; +;CHECK: GEN_1 <= m_c_en; +;CHECK: end +;CHECK: endmodule |