diff options
Diffstat (limited to 'test/passes/to-verilog/rd-mem.fir')
| -rw-r--r-- | test/passes/to-verilog/rd-mem.fir | 64 |
1 files changed, 31 insertions, 33 deletions
diff --git a/test/passes/to-verilog/rd-mem.fir b/test/passes/to-verilog/rd-mem.fir index 7146f026..909b034b 100644 --- a/test/passes/to-verilog/rd-mem.fir +++ b/test/passes/to-verilog/rd-mem.fir @@ -18,36 +18,34 @@ circuit top : m.c.clk <= clk rdata <= m.c.data -; CHECK: module top( -; CHECK: output [31:0] rdata, -; CHECK: input [1:0] index, -; CHECK: input ren, -; CHECK: input clk, -; CHECK: ); -; CHECK: reg [31:0] m [0:3]; -; CHECK: wire [31:0] m_c_data; -; CHECK: wire [1:0] m_c_addr; -; CHECK: wire m_c_en; -; CHECK: wire m_c_clk; -; CHECK: reg [1:0] GEN; -; CHECK: reg GEN_1; -; CHECK: assign rdata = m_c_data -; CHECK: assign m_c_addr = index -; CHECK: assign m_c_en = ren -; CHECK: assign m_c_clk = clk -; CHECK: `ifndef SYNTHESIS -; CHECK: integer initvar; -; CHECK: initial begin -; CHECK: #0.002; -; CHECK: for (initvar = 0; initvar < 4; initvar = initvar+1) -; CHECK: m[initvar] = {1{$random}}; -; CHECK: end -; CHECK: `endif -; CHECK: always @(posedge m_c_clk) begin -; CHECK: GEN <= m_c_addr -; CHECK: GEN_1 <= m_c_en -; CHECK: if(GEN_1) begin -; CHECK: m_c_data <= m[GEN] -; CHECK: end -; CHECK: end -; CHECK: endmodule +;CHECK: module top( +;CHECK: output [31:0] rdata, +;CHECK: input [1:0] index, +;CHECK: input ren, +;CHECK: input clk +;CHECK: ); +;CHECK: reg [31:0] m [0:3]; +;CHECK: wire [31:0] m_c_data; +;CHECK: wire [1:0] m_c_addr; +;CHECK: wire m_c_en; +;CHECK: wire m_c_clk; +;CHECK: reg [1:0] GEN; +;CHECK: reg GEN_1; +;CHECK: assign rdata = m_c_data; +;CHECK: assign m_c_addr = index; +;CHECK: assign m_c_en = ren; +;CHECK: assign m_c_clk = clk; +;CHECK: assign m_c_data = m[GEN]; +;CHECK: `ifndef SYNTHESIS +;CHECK: integer initvar; +;CHECK: initial begin +;CHECK: #0.002; +;CHECK: for (initvar = 0; initvar < 4; initvar = initvar+1) +;CHECK: m[initvar] = {1{$random}}; +;CHECK: end +;CHECK: `endif +;CHECK: always @(posedge m_c_clk) begin +;CHECK: GEN <= m_c_addr; +;CHECK: GEN_1 <= m_c_en; +;CHECK: end +;CHECK: endmodule |