Fixed tests that broke from changing verilog backend and removing mask from write mport declaration

3 files changed, 4 insertions, 4 deletions

diff --git a/test/passes/jacktest/Stack.fir b/test/passes/jacktest/Stack.fir
index c3ec4921..319e87d5 100644
--- a/test/passes/jacktest/Stack.fir
+++ b/test/passes/jacktest/Stack.fir
@@ -17,7 +17,7 @@ circuit Stack :
       node T_30 = lt(sp, UInt<5>(16))
       node T_31 = and(push, T_30)
       when T_31 : 
-        write mport T_32 = stack_mem[sp],clk,UInt(1)
+        write mport T_32 = stack_mem[sp],clk
         T_32 <= dataIn
         node T_33 = addw(sp, UInt<1>(1))
         sp <= T_33
diff --git a/test/passes/jacktest/Tbl.fir b/test/passes/jacktest/Tbl.fir
index 9b259d0f..f760af68 100644
--- a/test/passes/jacktest/Tbl.fir
+++ b/test/passes/jacktest/Tbl.fir
@@ -11,7 +11,7 @@ circuit Tbl :
     cmem m : UInt<10>[256]
     o <= UInt<1>(0)
     when we : 
-      write mport T_13 = m[i],clk,UInt(1)
+      write mport T_13 = m[i],clk
       node T_14 = bits(d, 9, 0)
       T_13 <= T_14
     else : 
diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir
index eb823321..0c11e785 100644
--- a/test/passes/jacktest/risc.fir
+++ b/test/passes/jacktest/risc.fir
@@ -30,7 +30,7 @@ circuit Risc :
     out <= UInt<1>(0)
     rc <= UInt<1>(0)
     when isWr : 
-      write mport T_55 = code[wrAddr],clk,UInt(1)
+      write mport T_55 = code[wrAddr],clk
       T_55 <= wrData
     else : when boot : pc <= UInt<1>(0)
       else : 
@@ -47,7 +47,7 @@ circuit Risc :
         node T_61 = eq(rci, UInt<8>(255))
         when T_61 : valid <= UInt<1>(1)
         else : 
-          write mport T_62 = file[rci],clk,UInt(1)
+          write mport T_62 = file[rci],clk
           T_62 <= rc
         node T_63 = addw(pc, UInt<1>(1))
         pc <= T_63