diff options
| author | Adam Izraelevitz | 2016-08-15 10:32:41 -0700 |
|---|---|---|
| committer | GitHub | 2016-08-15 10:32:41 -0700 |
| commit | bebd04c4c68c320b2b72325e348c726dc33beae6 (patch) | |
| tree | 69f6d4da577977cc7ff428b0545bb4735507aad0 /test/passes/jacktest/ModuleVec.fir | |
| parent | cca37c46fc0848f5dbf5f95ba60755ed6d60712b (diff) | |
Remove stanza (#231)
* Removed stanza implementation/tests.
In the future we can move the stanza tests over, but for now they should
be deleted.
* Added back integration .fir files
* Added Makefile to give Travis hooks
* Added firrtl script (was ignored before)
Diffstat (limited to 'test/passes/jacktest/ModuleVec.fir')
| -rw-r--r-- | test/passes/jacktest/ModuleVec.fir | 28 |
1 files changed, 0 insertions, 28 deletions
diff --git a/test/passes/jacktest/ModuleVec.fir b/test/passes/jacktest/ModuleVec.fir deleted file mode 100644 index 6f9b699b..00000000 --- a/test/passes/jacktest/ModuleVec.fir +++ /dev/null @@ -1,28 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit ModuleVec : - module PlusOne : - input in : UInt<32> - output out : UInt<32> - - node T_33 = tail(add(in, UInt<1>(1)),1) - out <= T_33 - module PlusOne_25 : - input in : UInt<32> - output out : UInt<32> - - node T_34 = tail(add(in, UInt<1>(1)),1) - out <= T_34 - module ModuleVec : - input ins : UInt<32>[2] - output outs : UInt<32>[2] - - inst T_35 of PlusOne - inst T_36 of PlusOne_25 - wire pluses : {flip in : UInt<32>, out : UInt<32>}[2] - pluses[0] <= T_35 - pluses[1] <= T_36 - pluses[0].in <= ins[0] - outs[0] <= pluses[0].out - pluses[1].in <= ins[1] - outs[1] <= pluses[1].out |