Merge branch 'new-reg-prims' of github.com:ucb-bar/firrtl

1 files changed, 2 insertions, 2 deletions

diff --git a/test/passes/jacktest/ModuleVec.fir b/test/passes/jacktest/ModuleVec.fir
index 9a8e7f2c..6f9b699b 100644
--- a/test/passes/jacktest/ModuleVec.fir
+++ b/test/passes/jacktest/ModuleVec.fir
@@ -5,13 +5,13 @@ circuit ModuleVec :
     input in : UInt<32>
     output out : UInt<32>
     
-    node T_33 = addw(in, UInt<1>(1))
+    node T_33 = tail(add(in, UInt<1>(1)),1)
     out <= T_33
   module PlusOne_25 : 
     input in : UInt<32>
     output out : UInt<32>
     
-    node T_34 = addw(in, UInt<1>(1))
+    node T_34 = tail(add(in, UInt<1>(1)),1)
     out <= T_34
   module ModuleVec : 
     input ins : UInt<32>[2]