From 5ab30c681558d2a26000696e518ee5b28deb1303 Mon Sep 17 00:00:00 2001
From: azidar
Date: Tue, 26 Jan 2016 14:18:34 -0800
Subject: Updated all tests to pass

---
 test/passes/jacktest/ModuleVec.fir | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'test/passes/jacktest/ModuleVec.fir')

diff --git a/test/passes/jacktest/ModuleVec.fir b/test/passes/jacktest/ModuleVec.fir
index 9a8e7f2c..6f9b699b 100644
--- a/test/passes/jacktest/ModuleVec.fir
+++ b/test/passes/jacktest/ModuleVec.fir
@@ -5,13 +5,13 @@ circuit ModuleVec :
     input in : UInt<32>
     output out : UInt<32>
     
-    node T_33 = addw(in, UInt<1>(1))
+    node T_33 = tail(add(in, UInt<1>(1)),1)
     out <= T_33
   module PlusOne_25 : 
     input in : UInt<32>
     output out : UInt<32>
     
-    node T_34 = addw(in, UInt<1>(1))
+    node T_34 = tail(add(in, UInt<1>(1)),1)
     out <= T_34
   module ModuleVec : 
     input ins : UInt<32>[2]
-- 
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