diff options
| author | azidar | 2016-01-28 12:12:02 -0800 |
|---|---|---|
| committer | azidar | 2016-01-28 12:12:02 -0800 |
| commit | 9ed79a822f7f406c55af8082da04cb7739e772eb (patch) | |
| tree | 02b10696dd0a03faf54c8eafa046855ccfc26e8f | |
| parent | b7dcc8ccbb1459a604353a8137081a9b156d276e (diff) | |
| parent | 094c6b8e7b40a3c613547d6127b449d0b1503db3 (diff) | |
Merge branch 'new-reg-prims' of github.com:ucb-bar/firrtl
65 files changed, 1791 insertions, 573 deletions
diff --git a/spec/spec.tex b/spec/spec.tex index 12f2c91e..ae633ecc 100644 --- a/spec/spec.tex +++ b/spec/spec.tex @@ -1792,14 +1792,14 @@ The concrete syntax of FIRRTL is defined in section \ref{syntax_tree}. Productio %\section{TODO} % %- FIRRTL implementation -% - Rework readwrite port types ; limits optimizations but probably ok -% - Make register reset/init optional ; good -% - removed addw, added head and tail ; great! % - Add UBits ; andrew doesn't care, favors overloading UInt % - Add SBits % - Add partial connect algorithm ; % - Add oriented types to type checker % - Add memory read-under-write flag ; probably overengineering, but could be a wash +% - *FINISHED* Make register reset/init optional ; good +% - *FINISHED* removed addw, added head and tail ; great! +% - *FINISHED* Rework readwrite port types ; limits optimizations but probably ok % - *FINISHED* Add Mux expression ; that's lovely, need glitch-free mux for clock types % - *FINISHED* add rename pass for verilog % - *FINISHED* Add is invalid ; good @@ -1808,6 +1808,8 @@ The concrete syntax of FIRRTL is defined in section \ref{syntax_tree}. Productio %- Proposed changes to spec % - switch back to precise dynamic left shift % - have a wmode instead of rmode for readwrite ports +% - rename mod to rem +% - changed rmode to wmode \end{document} diff --git a/src/main/stanza/chirrtl.stanza b/src/main/stanza/chirrtl.stanza index 9b3b90ab..6bce8ce4 100644 --- a/src/main/stanza/chirrtl.stanza +++ b/src/main/stanza/chirrtl.stanza @@ -223,6 +223,7 @@ defstruct DataRef : male : Symbol female : Symbol mask : Symbol + rdwrite? : True|False public definterface Gender public val MALE = new Gender @@ -272,26 +273,26 @@ defn remove-chirrtl (c:Circuit) : (s:CDefMemory) : mport-types[name(s)] = type(s) val stmts = Vector<Stmt>() - val naddr = firrtl-gensym(`GEN,sh) + ;val naddr = firrtl-gensym(`GEN,sh) val taddr = UIntType(IntWidth(max(1,ceil-log2(size(s))))) - add(stmts,DefPoison(info(s),naddr,taddr)) - val ndata = firrtl-gensym(`GEN,sh) + ;add(stmts,DefPoison(info(s),naddr,taddr)) + ;val ndata = firrtl-gensym(`GEN,sh) val tdata = type(s) - add(stmts,DefPoison(info(s),ndata,tdata)) + ;add(stmts,DefPoison(info(s),ndata,tdata)) defn set-poison (vec:List<MPort>,addr:Symbol) -> False : for r in vec do : - add(stmts,Connect(info(s),SubField(SubField(Ref(name(s),ut),name(r),ut),addr,taddr),Ref(naddr,taddr))) + add(stmts,IsInvalid(info(s),SubField(SubField(Ref(name(s),ut),name(r),ut),addr,taddr))) add(stmts,Connect(info(s),SubField(SubField(Ref(name(s),ut),name(r),ut),`clk,taddr),clk(r))) defn set-enable (vec:List<MPort>,en:Symbol) -> False: for r in vec do : add(stmts,Connect(info(s),SubField(SubField(Ref(name(s),ut),name(r),ut),en,taddr),zero)) - defn set-rmode (vec:List<MPort>,rmode:Symbol) -> False: + defn set-wmode (vec:List<MPort>,wmode:Symbol) -> False: for r in vec do : - add(stmts,Connect(info(s),SubField(SubField(Ref(name(s),ut),name(r),ut),rmode,taddr),one)) + add(stmts,Connect(info(s),SubField(SubField(Ref(name(s),ut),name(r),ut),wmode,taddr),zero)) defn set-write (vec:List<MPort>,data:Symbol,mask:Symbol) -> False : val tmask = create-mask(type(s)) for r in vec do : - add(stmts,Connect(info(s),SubField(SubField(Ref(name(s),ut),name(r),ut),data,tdata),Ref(ndata,tdata))) + add(stmts,IsInvalid(info(s),SubField(SubField(Ref(name(s),ut),name(r),ut),data,tdata))) for x in create-exps(SubField(SubField(Ref(name(s),ut),name(r),ut),mask,tmask)) do : add(stmts,Connect(info(s),x,zero)) @@ -304,7 +305,7 @@ defn remove-chirrtl (c:Circuit) : set-write(wrs,`data,`mask) val rws = to-list $ readwriters $ get?(hash,name(s),EMPs()) set-poison(rws,`addr) - set-rmode(rws,`rmode) + set-wmode(rws,`wmode) set-enable(rws,`en) set-write(rws,`data,`mask) val read-l = @@ -317,21 +318,19 @@ defn remove-chirrtl (c:Circuit) : val addrs = Vector<Symbol>() val ens = Vector<Symbol>() val masks = Vector<Symbol>() - val rmodes = Vector<Symbol>() switch { _ == direction(s) } : MReadWrite : - repl[name(s)] = DataRef(SubField(Ref(mem(s),ut),name(s),ut),`rdata,`data,`mask) + repl[name(s)] = DataRef(SubField(Ref(mem(s),ut),name(s),ut),`rdata,`data,`mask,true) add(addrs,`addr) add(ens,`en) - add(rmodes,`rmode) add(masks,`mask) MWrite : - repl[name(s)] = DataRef(SubField(Ref(mem(s),ut),name(s),ut),`data,`data,`mask) + repl[name(s)] = DataRef(SubField(Ref(mem(s),ut),name(s),ut),`data,`data,`mask,false) add(addrs,`addr) add(ens,`en) add(masks,`mask) else : - repl[name(s)] = DataRef(SubField(Ref(mem(s),ut),name(s),ut),`data,`data,`blah) + repl[name(s)] = DataRef(SubField(Ref(mem(s),ut),name(s),ut),`data,`data,`blah,false) add(addrs,`addr) add(ens,`en) @@ -340,14 +339,13 @@ defn remove-chirrtl (c:Circuit) : add(stmts,Connect(info(s),SubField(SubField(Ref(mem(s),ut),name(s),ut),x,ut),exps(s)[0])) for x in ens do : add(stmts,Connect(info(s),SubField(SubField(Ref(mem(s),ut),name(s),ut),x,ut),one)) - for x in rmodes do : - add(stmts,Connect(info(s),SubField(SubField(Ref(mem(s),ut),name(s),ut),x,ut),zero)) Begin $ to-list $ stmts (s) : map(collect-refs,s) defn remove-chirrtl-s (s:Stmt) -> Stmt : var has-write-mport? = false + var has-readwrite-mport? = false defn remove-chirrtl-e (e:Expression,g:Gender) -> Expression : - match(map(remove-chirrtl-e{_,g},e)) : + match(e) : (e:Ref) : if key?(repl,name(e)) : val vt = repl[name(e)] @@ -355,9 +353,12 @@ defn remove-chirrtl (c:Circuit) : MALE : SubField(exp(vt),male(vt),type(e)) FEMALE : has-write-mport? = true + if rdwrite?(vt) == true : + has-readwrite-mport? = SubField(exp(vt),`wmode,UIntType(IntWidth(1))) SubField(exp(vt),female(vt),type(e)) else : e - (e) : e + (e:SubAccess) : SubAccess(remove-chirrtl-e(exp(e),g),remove-chirrtl-e(index(e),MALE),type(e)) + (e) : map(remove-chirrtl-e{_,g},e) defn get-mask (e:Expression) -> Expression : match(map(get-mask,e)) : (e:Ref) : @@ -377,6 +378,9 @@ defn remove-chirrtl (c:Circuit) : val e = get-mask(loc(s)) for x in create-exps(e) do : add(stmts,Connect(info(s),x,one)) + if has-readwrite-mport? != false : + val wmode = has-readwrite-mport? as Expression + add(stmts,Connect(info(s),wmode,one)) if length(stmts) > 1 : Begin(to-list(stmts)) else : stmts[0] (s:BulkConnect) : @@ -384,12 +388,15 @@ defn remove-chirrtl (c:Circuit) : val loc* = remove-chirrtl-e(loc(s),FEMALE) val roc* = remove-chirrtl-e(exp(s),MALE) add(stmts,BulkConnect(info(s),loc*,roc*)) - if has-write-mport? : + if has-write-mport? != false : val ls = get-valid-points(type(loc(s)),type(exp(s)),DEFAULT,DEFAULT) val locs = create-exps(get-mask(loc(s))) for x in ls do : val loc* = locs[x[0]] add(stmts,Connect(info(s),loc*,one)) + if has-readwrite-mport? != false : + val wmode = has-readwrite-mport? as Expression + add(stmts,Connect(info(s),wmode,one)) if length(stmts) > 1 : Begin(to-list(stmts)) else : stmts[0] (s) : map(remove-chirrtl-e{_,MALE}, map(remove-chirrtl-s,s)) diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza index 3ca4f8da..0d0191bf 100644 --- a/src/main/stanza/compilers.stanza +++ b/src/main/stanza/compilers.stanza @@ -78,8 +78,6 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> : ;=============== ConstProp() ;=============== - SplitExp() - ;=============== ResolveKinds() InferTypes() CheckTypes() @@ -98,6 +96,8 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> : InferWidths() CheckWidths() ;=============== + VerilogWrap() + SplitExp() VerilogRename() Verilog(with-output(c)) ;=============== @@ -152,8 +152,6 @@ public defmethod passes (c:StandardLoFIRRTL) -> List<Pass> : ;=============== ConstProp() ;=============== - SplitExp() - ;=============== ResolveKinds() InferTypes() CheckTypes() @@ -172,6 +170,8 @@ public defmethod passes (c:StandardLoFIRRTL) -> List<Pass> : InferWidths() CheckWidths() ;=============== + SplitExp() + ;=============== FIRRTL(with-output(c)) ] diff --git a/src/main/stanza/errors.stanza b/src/main/stanza/errors.stanza index 3e388a42..a0c48dc8 100644 --- a/src/main/stanza/errors.stanza +++ b/src/main/stanza/errors.stanza @@ -191,39 +191,34 @@ public defn check-high-form (c:Circuit) -> Circuit : SUB-OP : correct-num(2,0) MUL-OP : correct-num(2,0) DIV-OP : correct-num(2,0) - MOD-OP : correct-num(2,0) - QUO-OP : correct-num(2,0) REM-OP : correct-num(2,0) - ADD-WRAP-OP : correct-num(2,0) - SUB-WRAP-OP : correct-num(2,0) LESS-OP : correct-num(2,0) LESS-EQ-OP : correct-num(2,0) GREATER-OP : correct-num(2,0) GREATER-EQ-OP : correct-num(2,0) EQUAL-OP : correct-num(2,0) NEQUAL-OP : correct-num(2,0) - EQUIV-OP : correct-num(2,0) - NEQUIV-OP : correct-num(2,0) - ;MUX-OP : correct-num(3,0) PAD-OP : correct-num(1,1) AS-UINT-OP : correct-num(1,0) AS-SINT-OP : correct-num(1,0) - DYN-SHIFT-LEFT-OP : correct-num(2,0) - DYN-SHIFT-RIGHT-OP : correct-num(2,0) + AS-CLOCK-OP : correct-num(1,0) SHIFT-LEFT-OP : correct-num(1,1) SHIFT-RIGHT-OP : correct-num(1,1) + DYN-SHIFT-LEFT-OP : correct-num(2,0) + DYN-SHIFT-RIGHT-OP : correct-num(2,0) CONVERT-OP : correct-num(1,0) NEG-OP : correct-num(1,0) - BIT-NOT-OP : correct-num(1,0) - BIT-AND-OP : correct-num(2,0) - BIT-OR-OP : correct-num(2,0) - BIT-XOR-OP : correct-num(2,0) - BIT-AND-REDUCE-OP : correct-num(false,0) - BIT-OR-REDUCE-OP : correct-num(false,0) - BIT-XOR-REDUCE-OP : correct-num(false,0) + NOT-OP : correct-num(1,0) + AND-OP : correct-num(2,0) + OR-OP : correct-num(2,0) + XOR-OP : correct-num(2,0) + AND-REDUCE-OP : correct-num(false,0) + OR-REDUCE-OP : correct-num(false,0) + XOR-REDUCE-OP : correct-num(false,0) CONCAT-OP : correct-num(2,0) - BIT-SELECT-OP : correct-num(1,1) BITS-SELECT-OP : correct-num(1,2) + HEAD-OP : correct-num(1,1) + TAIL-OP : correct-num(1,1) defn check-fstring (s:String,i:Int) -> False : val valid-formats = "bedxs" @@ -481,48 +476,39 @@ defn check-types-primop (e:DoPrim, errors:Vector<PassException>,info:FileInfo) - error? = true if error? : add(errors,OpNotUInt(info,to-symbol $ op(e),to-symbol(x))) - all-ground(args(e)) - switch {op(e) == _} : - ADD-OP : false - SUB-OP : false - MUL-OP : false - DIV-OP : false - MOD-OP : false - QUO-OP : false - REM-OP : false - ADD-WRAP-OP : false - SUB-WRAP-OP : false - LESS-OP : false - LESS-EQ-OP : false - GREATER-OP : false - GREATER-EQ-OP : false - EQUAL-OP : false - NEQUAL-OP : false - EQUIV-OP : all-same-type(args(e)) - NEQUIV-OP : all-same-type(args(e)) - ;MUX-OP : - ; all-same-type(tail(args(e))) - ; is-uint(head(args(e))) - PAD-OP : false AS-UINT-OP : false AS-SINT-OP : false - DYN-SHIFT-LEFT-OP : is-uint(args(e)[1]) - DYN-SHIFT-RIGHT-OP : is-uint(args(e)[1]) - SHIFT-LEFT-OP : false - SHIFT-RIGHT-OP : false - CONVERT-OP : false - NEG-OP : false - BIT-NOT-OP : all-same-type(args(e)) ;can be either uint or sint - BIT-AND-OP : all-same-type(args(e)) ;can be either uint or sint - BIT-OR-OP : all-same-type(args(e)) ;can be either uint or sint - BIT-XOR-OP : all-same-type(args(e)) ;can be either uint or sint - BIT-SELECT-OP : false ;can be either uint or sint - BITS-SELECT-OP : false ;can be either uint or sint - BIT-AND-REDUCE-OP : false ;can be either uint or sint - BIT-OR-REDUCE-OP : false ;can be either uint or sint - BIT-XOR-REDUCE-OP : false ;can be either uint or sint - CONCAT-OP : false ;can be either uint or sint + AS-CLOCK-OP : false + DYN-SHIFT-LEFT-OP : (is-uint(args(e)[1]) all-ground(args(e))) + DYN-SHIFT-RIGHT-OP : (is-uint(args(e)[1]) all-ground(args(e))) + ADD-OP : all-ground(args(e)) + SUB-OP : all-ground(args(e)) + MUL-OP : all-ground(args(e)) + DIV-OP : all-ground(args(e)) + REM-OP : all-ground(args(e)) + LESS-OP : all-ground(args(e)) + LESS-EQ-OP : all-ground(args(e)) + GREATER-OP : all-ground(args(e)) + GREATER-EQ-OP : all-ground(args(e)) + EQUAL-OP : all-ground(args(e)) + NEQUAL-OP : all-ground(args(e)) + PAD-OP : all-ground(args(e)) + SHIFT-LEFT-OP : all-ground(args(e)) + SHIFT-RIGHT-OP : all-ground(args(e)) + CONVERT-OP : all-ground(args(e)) + NEG-OP : all-ground(args(e)) + NOT-OP : all-ground(args(e)) + AND-OP : all-ground(args(e)) + OR-OP : all-ground(args(e)) + XOR-OP : all-ground(args(e)) + AND-REDUCE-OP : all-ground(args(e)) + OR-REDUCE-OP : all-ground(args(e)) + XOR-REDUCE-OP : all-ground(args(e)) + CONCAT-OP : all-ground(args(e)) + BITS-SELECT-OP : all-ground(args(e)) + HEAD-OP : all-ground(args(e)) + TAIL-OP : all-ground(args(e)) ;----------------- Check Types Pass --------------------- public defn check-types (c:Circuit) -> Circuit : diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza index 4d906c70..e6c242bf 100644 --- a/src/main/stanza/firrtl-ir.stanza +++ b/src/main/stanza/firrtl-ir.stanza @@ -32,39 +32,34 @@ public val ADD-OP = new PrimOp public val SUB-OP = new PrimOp public val MUL-OP = new PrimOp public val DIV-OP = new PrimOp -public val MOD-OP = new PrimOp -public val QUO-OP = new PrimOp public val REM-OP = new PrimOp -public val ADD-WRAP-OP = new PrimOp -public val SUB-WRAP-OP = new PrimOp public val LESS-OP = new PrimOp public val LESS-EQ-OP = new PrimOp public val GREATER-OP = new PrimOp public val GREATER-EQ-OP = new PrimOp public val NEQUAL-OP = new PrimOp public val EQUAL-OP = new PrimOp -public val NEQUIV-OP = new PrimOp -public val EQUIV-OP = new PrimOp -;public val MUX-OP = new PrimOp public val PAD-OP = new PrimOp public val AS-UINT-OP = new PrimOp public val AS-SINT-OP = new PrimOp -public val DYN-SHIFT-LEFT-OP = new PrimOp -public val DYN-SHIFT-RIGHT-OP = new PrimOp +public val AS-CLOCK-OP = new PrimOp public val SHIFT-LEFT-OP = new PrimOp public val SHIFT-RIGHT-OP = new PrimOp +public val DYN-SHIFT-LEFT-OP = new PrimOp +public val DYN-SHIFT-RIGHT-OP = new PrimOp public val NEG-OP = new PrimOp public val CONVERT-OP = new PrimOp -public val BIT-NOT-OP = new PrimOp -public val BIT-AND-OP = new PrimOp -public val BIT-OR-OP = new PrimOp -public val BIT-XOR-OP = new PrimOp +public val NOT-OP = new PrimOp +public val AND-OP = new PrimOp +public val OR-OP = new PrimOp +public val XOR-OP = new PrimOp +public val AND-REDUCE-OP = new PrimOp +public val OR-REDUCE-OP = new PrimOp +public val XOR-REDUCE-OP = new PrimOp public val CONCAT-OP = new PrimOp -public val BIT-SELECT-OP = new PrimOp public val BITS-SELECT-OP = new PrimOp -public val BIT-AND-REDUCE-OP = new PrimOp -public val BIT-OR-REDUCE-OP = new PrimOp -public val BIT-XOR-REDUCE-OP = new PrimOp +public val HEAD-OP = new PrimOp +public val TAIL-OP = new PrimOp public definterface Expression public defmulti type (e:Expression) -> Type diff --git a/src/main/stanza/flo.stanza b/src/main/stanza/flo.stanza index 3b1dbf76..015da39a 100644 --- a/src/main/stanza/flo.stanza +++ b/src/main/stanza/flo.stanza @@ -31,7 +31,7 @@ defn flo-op-name (op:PrimOp, args:List<Expression>) -> String : SUB-WRAP-OP : "sub" MUL-OP : "mul" ;; todo: signed version DIV-OP : "div" ;; todo: signed version - MOD-OP : "mod" ;; todo: signed version + REM-OP : "mod" ;; todo: signed version QUO-OP : "div" ;; todo: signed version REM-OP : "mod" ;; todo: signed version LESS-OP : "lt" ;; todo: signed version diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza index e1083d50..139216c3 100644 --- a/src/main/stanza/ir-parser.stanza +++ b/src/main/stanza/ir-parser.stanza @@ -63,39 +63,35 @@ OPERATORS[`add] = ADD-OP OPERATORS[`sub] = SUB-OP OPERATORS[`mul] = MUL-OP OPERATORS[`div] = DIV-OP -OPERATORS[`mod] = MOD-OP -OPERATORS[`quo] = QUO-OP OPERATORS[`rem] = REM-OP -OPERATORS[`addw] = ADD-WRAP-OP -OPERATORS[`subw] = SUB-WRAP-OP OPERATORS[`lt] = LESS-OP OPERATORS[`leq] = LESS-EQ-OP OPERATORS[`gt] = GREATER-OP OPERATORS[`geq] = GREATER-EQ-OP OPERATORS[`eq] = EQUAL-OP OPERATORS[`neq] = NEQUAL-OP -OPERATORS[`eqv] = EQUIV-OP -OPERATORS[`neqv] = NEQUIV-OP -;OPERATORS[`mux] = MUX-OP OPERATORS[`pad] = PAD-OP OPERATORS[`neg] = NEG-OP OPERATORS[`asUInt] = AS-UINT-OP OPERATORS[`asSInt] = AS-SINT-OP -OPERATORS[`dshl] = DYN-SHIFT-LEFT-OP -OPERATORS[`dshr] = DYN-SHIFT-RIGHT-OP +OPERATORS[`asClock] = AS-CLOCK-OP OPERATORS[`shl] = SHIFT-LEFT-OP OPERATORS[`shr] = SHIFT-RIGHT-OP +OPERATORS[`dshl] = DYN-SHIFT-LEFT-OP +OPERATORS[`dshr] = DYN-SHIFT-RIGHT-OP OPERATORS[`cvt] = CONVERT-OP -OPERATORS[`andr] = BIT-AND-REDUCE-OP -OPERATORS[`orr] = BIT-OR-REDUCE-OP -OPERATORS[`xorr] = BIT-XOR-REDUCE-OP -OPERATORS[`not] = BIT-NOT-OP -OPERATORS[`and] = BIT-AND-OP -OPERATORS[`or] = BIT-OR-OP -OPERATORS[`xor] = BIT-XOR-OP +OPERATORS[`neg] = NEG-OP +OPERATORS[`not] = NOT-OP +OPERATORS[`and] = AND-OP +OPERATORS[`or] = OR-OP +OPERATORS[`xor] = XOR-OP +OPERATORS[`andr] = AND-REDUCE-OP +OPERATORS[`orr] = OR-REDUCE-OP +OPERATORS[`xorr] = XOR-REDUCE-OP OPERATORS[`cat] = CONCAT-OP -OPERATORS[`bit] = BIT-SELECT-OP OPERATORS[`bits] = BITS-SELECT-OP +OPERATORS[`head] = HEAD-OP +OPERATORS[`tail] = TAIL-OP ;======== Parser Rules ================== defsyntax firrtl : @@ -250,7 +246,7 @@ defsyntax firrtl : defrule mstat : mstat = (reader #=>! ?name:#id!) : Reader(name) mstat = (writer #=>! ?name:#id!) : Writer(name) - mstat = (read-writer #=>! ?name:#id!) : ReadWriter(name) + mstat = (readwriter #=>! ?name:#id!) : ReadWriter(name) mstat = (read-latency #=>! ?i:#int!) : ReadLatency(i) mstat = (write-latency #=>! ?i:#int!) : WriteLatency(i) mstat = (data-type #=>! ?t:#type!) : DataType(t) @@ -258,9 +254,8 @@ defsyntax firrtl : defrule statements : stmt = (skip) : Empty() stmt = (wire ?name:#id! #:! ?t:#type!) : DefWire(first-info(form),name, t) - stmt = (reg ?name:#id! #:! ?t:#type! ?clk:#exp! ?reset:#exp! ?init:#exp!) : DefRegister(first-info(form),name, t,clk,reset,init) - ;stmt = (mem ?name:#id! #:! ?data-type:#type! ?depth:#int ?writers:#id! ... ?wl:#int ?readers:#id! ... ?rl:#int ?readwriters:#id! ...) : - ; DefMemory(first-info(form),name,data-type,depth,wl,rl,readers,writers,readwriters) + stmt = (reg ?name:#id! #:! ?t:#type! ?clk:#exp! with #:! ( reset => (?reset:#exp! ?init:#exp!))) : DefRegister(first-info(form),name,t,clk,reset,init) + stmt = (reg ?name:#id! #:! ?t:#type! ?clk:#exp!) : DefRegister(first-info(form),name,t,clk,zero,Ref(name,UnknownType())) stmt = (cmem ?name:#id! #:! ?t:#vectype! ) : CDefMemory(first-info(form),name,type(t),size(t),false) stmt = (smem ?name:#id! #:! ?t:#vectype! ) : CDefMemory(first-info(form),name,type(t),size(t),true) diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza index cf9e03e2..24149649 100644 --- a/src/main/stanza/ir-utils.stanza +++ b/src/main/stanza/ir-utils.stanza @@ -100,17 +100,17 @@ public defn AND (e1:Expression,e2:Expression) -> Expression : else if e1 == zero or e2 == zero : zero else if e1 == one : e2 else if e2 == one : e1 - else : DoPrim(BIT-AND-OP,list(e1,e2),list(),UIntType(IntWidth(1))) + else : DoPrim(AND-OP,list(e1,e2),list(),UIntType(IntWidth(1))) public defn OR (e1:Expression,e2:Expression) -> Expression : if e1 == e2 : e1 else if e1 == one or e2 == one : one else if e1 == zero : e2 else if e2 == zero : e1 - else : DoPrim(BIT-OR-OP,list(e1,e2),list(),UIntType(IntWidth(1))) + else : DoPrim(OR-OP,list(e1,e2),list(),UIntType(IntWidth(1))) public defn EQV (e1:Expression,e2:Expression) -> Expression : - DoPrim(EQUIV-OP,list(e1,e2),list(),type(e1)) + DoPrim(EQUAL-OP,list(e1,e2),list(),type(e1)) public defn MUX (p:Expression,e1:Expression,e2:Expression) -> Expression : Mux(p,e1,e2,mux-type(type(e1),type(e2))) @@ -134,7 +134,7 @@ public defn CAT (e1:Expression,e2:Expression) -> Expression : public defn NOT (e1:Expression) -> Expression : if e1 == one : zero else if e1 == zero : one - else : DoPrim(EQUIV-OP,list(e1,zero),list(),UIntType(IntWidth(1))) + else : DoPrim(EQUAL-OP,list(e1,zero),list(),UIntType(IntWidth(1))) public defn children (e:Expression) -> List<Expression> : val es = Vector<Expression>() @@ -185,12 +185,12 @@ public defmethod get-type (s:Stmt) -> Type : val def-data = Field(`data,DEFAULT,data-type(s)) val rev-data = Field(`data,REVERSE,data-type(s)) val mask = Field(`mask,DEFAULT,create-mask(data-type(s))) - val rmode = Field(`rmode,DEFAULT,UIntType(IntWidth(1))) + val wmode = Field(`wmode,DEFAULT,UIntType(IntWidth(1))) val rdata = Field(`rdata,REVERSE,data-type(s)) val read-type = BundleType(to-list([rev-data,addr,en,clk])) val write-type = BundleType(to-list([def-data,mask,addr,en,clk])) - val readwrite-type = BundleType(to-list([rmode,rdata,def-data,mask,addr,en,clk])) + val readwrite-type = BundleType(to-list([wmode,rdata,def-data,mask,addr,en,clk])) val mem-fields = Vector<Field>() for x in readers(s) do : @@ -360,39 +360,34 @@ defmethod print (o:OutputStream, op:PrimOp) : SUB-OP : "sub" MUL-OP : "mul" DIV-OP : "div" - MOD-OP : "mod" - QUO-OP : "quo" REM-OP : "rem" - ADD-WRAP-OP : "addw" - SUB-WRAP-OP : "subw" LESS-OP : "lt" LESS-EQ-OP : "leq" GREATER-OP : "gt" GREATER-EQ-OP : "geq" - EQUIV-OP : "eqv" - NEQUIV-OP : "neqv" EQUAL-OP : "eq" NEQUAL-OP : "neq" - ;MUX-OP : "mux" PAD-OP : "pad" AS-UINT-OP : "asUInt" AS-SINT-OP : "asSInt" - DYN-SHIFT-LEFT-OP : "dshl" - DYN-SHIFT-RIGHT-OP : "dshr" + AS-CLOCK-OP : "asClock" SHIFT-LEFT-OP : "shl" SHIFT-RIGHT-OP : "shr" + DYN-SHIFT-LEFT-OP : "dshl" + DYN-SHIFT-RIGHT-OP : "dshr" CONVERT-OP : "cvt" NEG-OP : "neg" - BIT-NOT-OP : "not" - BIT-AND-OP : "and" - BIT-OR-OP : "or" - BIT-XOR-OP : "xor" - BIT-AND-REDUCE-OP : "andr" - BIT-OR-REDUCE-OP : "orr" - BIT-XOR-REDUCE-OP : "xorr" + NOT-OP : "not" + AND-OP : "and" + OR-OP : "or" + XOR-OP : "xor" + AND-REDUCE-OP : "andr" + OR-REDUCE-OP : "orr" + XOR-REDUCE-OP : "xorr" CONCAT-OP : "cat" - BIT-SELECT-OP : "bit" BITS-SELECT-OP : "bits" + HEAD-OP : "head" + TAIL-OP : "tail" defmethod print (o:OutputStream, e:Expression) : match(e) : @@ -420,17 +415,18 @@ defmethod print (o:OutputStream, c:Stmt) : (c:DefWire) : print-all(o,["wire " name(c) " : " type(c)]) (c:DefRegister) : - print-all(o,["reg " name(c) " : " type(c) ", " clock(c) ", " reset(c) ", " init(c)]) + print-all(o,["reg " name(c) " : " type(c) ", " clock(c) " with :"]) + print-all(io,["\nreset => (" reset(c) ", " init(c) ")"]) (c:DefMemory) : print-all(o,["mem " name(c) " : "]) print-debug(o,c) - print-all(io,["\ndata-type: " data-type(c)]) - print-all(io,["\ndepth: " depth(c)]) - print-all(io,["\nwrite-latency: " write-latency(c)]) - print-all(io,["\nread-latency: " read-latency(c)]) - for r in readers(c) do : print-all(io,["\nreader: " r]) - for w in writers(c) do : print-all(io,["\nwriter: " w]) - for rw in readwriters(c) do : print-all(io,["\nread-writer: " rw]) + print-all(io,["\ndata-type => " data-type(c)]) + print-all(io,["\ndepth => " depth(c)]) + print-all(io,["\nwrite-latency => " write-latency(c)]) + print-all(io,["\nread-latency => " read-latency(c)]) + for r in readers(c) do : print-all(io,["\nreader => " r]) + for w in writers(c) do : print-all(io,["\nwriter => " w]) + for rw in readwriters(c) do : print-all(io,["\nreadwriter => " rw]) (c:DefInstance) : print-all(o,["inst " name(c) " of " module(c)]) (c:DefNode) : diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index 68922044..503e16c4 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -322,6 +322,8 @@ defmethod map (f: Type -> Type, e: WSubAccess) : defmethod map (f: Type -> Type, s: WDefInstance) : WDefInstance(info(s),name(s),module(s),f(type(s))) +defmethod map (f: Symbol -> Symbol, s: WDefInstance) : + WDefInstance(info(s),f(name(s)),module(s),type(s)) ;================ WIDTH LIBRARY ==================== @@ -336,6 +338,8 @@ public defstruct MinusWidth <: Width : arg2 : Width public defstruct MaxWidth <: Width : args : List<Width> +public defstruct MinWidth <: Width : + args : List<Width> public defstruct ExpWidth <: Width : arg1 : Width val width-name-hash = HashTable<Symbol,Int>(symbol-hash) @@ -344,6 +348,7 @@ public defmulti map<?T> (f: Width -> Width, w:?T&Width) -> T defmethod map (f: Width -> Width, w:Width) -> Width : match(w) : (w:MaxWidth) : MaxWidth(map(f,args(w))) + (w:MinWidth) : MinWidth(map(f,args(w))) (w:PlusWidth) : PlusWidth(f(arg1(w)),f(arg2(w))) (w:MinusWidth) : MinusWidth(f(arg1(w)),f(arg2(w))) (w:ExpWidth) : ExpWidth(f(arg1(w))) @@ -353,6 +358,8 @@ public defmethod print (o:OutputStream, w:VarWidth) : print(o,name(w)) public defmethod print (o:OutputStream, w:MaxWidth) : print-all(o,["max" args(w)]) +public defmethod print (o:OutputStream, w:MinWidth) : + print-all(o,["min" args(w)]) public defmethod print (o:OutputStream, w:PlusWidth) : print-all(o,[ "(" arg1(w) " + " arg2(w) ")"]) public defmethod print (o:OutputStream, w:MinusWidth) : @@ -376,6 +383,13 @@ defmethod equal? (w1:Width,w2:Width) -> True|False : for w in args(w1) do : if not contains?(args(w2),w) : ret(false) ret(true) + (w1:MinWidth,w2:MinWidth) : + label<True|False> ret : + if not length(args(w1)) == length(args(w2)) : ret(false) + else : + for w in args(w1) do : + if not contains?(args(w2),w) : ret(false) + ret(true) (w1:IntWidth,w2:IntWidth) : width(w1) == width(w2) (w1:PlusWidth,w2:PlusWidth) : (arg1(w1) == arg1(w2) and arg2(w1) == arg2(w2)) or (arg1(w1) == arg2(w2) and arg2(w1) == arg1(w2)) @@ -1408,6 +1422,14 @@ defn solve-constraints (l:List<WGeq>) -> HashTable<Symbol,Width> : h defn simplify (w:Width) -> Width : match(map(simplify,w)) : + (w:MinWidth) : + val v = Vector<Width>() + for w* in args(w) do : + match(w*) : + (w*:MinWidth) : + for x in args(w*) do : add(v,x) + (w*) : add(v,w*) + MinWidth(unique(v)) (w:MaxWidth) : val v = Vector<Width>() for w* in args(w) do : @@ -1549,6 +1571,9 @@ defn reduce-var-widths (c:Circuit,h:HashTable<Symbol,Width>) -> Circuit : defn max (a:Long,b:Long) -> Long : if a >= b : a else : b + defn min (a:Long,b:Long) -> Long : + if a >= b : b + else : a defn solve (w:Width) -> False|Long : match(w) : (w:VarWidth) : @@ -1558,6 +1583,7 @@ defn reduce-var-widths (c:Circuit,h:HashTable<Symbol,Width>) -> Circuit : (w:False) : false (w) : solve(w as Width) (w:MaxWidth) : apply-l(map(solve,args(w)),max) + (w:MinWidth) : apply-l(map(solve,args(w)),min) (w:PlusWidth) : apply(solve(arg1(w)),solve(arg2(w)),{plus(_,_)}) (w:MinusWidth) : apply(solve(arg1(w)),solve(arg2(w)),{minus(_,_)}) (w:ExpWidth) : apply(to-long(2),solve(arg1(w)),{minus(pow(_,_),to-long(1))}) @@ -1741,7 +1767,54 @@ defn resolve (c:Circuit) -> Circuit : ; val top = (for m in modules(c) find : name(m) == main(c)) as InModule ; Circuit(info(c),list(InModule(info(top),name(top),ports(top),inline-inst(body(top)))),main(c)) +;;================= Verilog Wrap ======================== + +; --------- Utils -------------- + +;---------- Pass --------------- +;; Intended to only work on low firrtl +public defstruct VerilogWrap <: Pass +public defmethod pass (b:VerilogWrap) -> (Circuit -> Circuit) : v-wrap +public defmethod name (b:VerilogWrap) -> String : "Verilog Wrap" +public defmethod short-name (b:VerilogWrap) -> String : "v-wrap" + +public definterface WPrimOp <: PrimOp +val ADDW-OP = new WPrimOp +val SUBW-OP = new WPrimOp + +defmethod print (o:OutputStream,op:WPrimOp) : + print{o, _} $ switch {op == _} : + ADDW-OP : "addw" + SUBW-OP : "subw" + +defn v-wrap-e (e:Expression) -> Expression : + match(map(v-wrap-e,e)) : + (e:DoPrim) : + defn a0 () : args(e)[0] + if op(e) == TAIL-OP : + match(a0()) : + (e0:DoPrim) : + if op(e0) == ADD-OP : + DoPrim(ADDW-OP,args(e0),list(),type(e)) + else if op(e0) == SUB-OP : + DoPrim(SUBW-OP,args(e0),list(),type(e)) + else : e + (e0) : e + else : e + (e) : e +defn v-wrap-s (s:Stmt) -> Stmt : + map{v-wrap-e,_} $ map(v-wrap-s,s) +defn v-wrap (c:Circuit) -> Circuit : + val modules* = for m in modules(c) map : + match(m) : + (m:InModule) : + mname = name(m) + InModule(info(m),name(m),ports(m),v-wrap-s(body(m))) + (m:ExModule) : m + Circuit(info(c),modules*,main(c)) + ;;================= Split Expressions ======================== + ;; Intended to only work on low firrtl public defstruct SplitExp <: Pass public defmethod pass (b:SplitExp) -> (Circuit -> Circuit) : split-exp @@ -1763,7 +1836,7 @@ defn split-exp (m:InModule) -> InModule : add(v,DefNode(info(s),n,e)) WRef(n,type(e),kind(e),gender(e)) defn split-exp-e (e:Expression,i:Int) -> Expression : - match(map(split-exp-e{_,i + 1},e)) : + match(map(split-exp-e{_,i + 1},e)) : (e:DoPrim) : if i > 0 : split(e) else : e @@ -2015,13 +2088,11 @@ defn const-prop-e (e:Expression) -> Expression : (x:UIntValue) : val b = bits(value(x),consts(e)[0] + 1,consts(e)[1]) UIntValue(b,width(type(e) as UIntType)) - (x) : e - BIT-SELECT-OP : - match(args(e)[0]) : - (x:UIntValue) : - val i = bit(value(x),consts(e)[0]) - UIntValue(i,width(type(e) as UIntType)) - (x) : e + (x) : + if long!(type(e)) == long!(type(x)) : + if type(x) typeof UIntType : x + else : DoPrim(AS-UINT-OP,list(x),list(),type(e)) + else : e else : e (e) : e @@ -2457,6 +2528,10 @@ defn op-stream (doprim:DoPrim) -> Streamable : match(type(doprim)) : (t:UIntType) : e (t:SIntType) : ["$signed(" e ")"] + defn cast-as (e:Expression) -> ? : + match(type(e)) : + (t:UIntType) : e + (t:SIntType) : ["$signed(" e ")"] defn a0 () -> Expression : args(doprim)[0] defn a1 () -> Expression : args(doprim)[1] defn a2 () -> Expression : args(doprim)[2] @@ -2465,23 +2540,18 @@ defn op-stream (doprim:DoPrim) -> Streamable : switch {_ == op(doprim)} : ADD-OP : [cast-if(a0()) " + " cast-if(a1())] + ADDW-OP : [cast-if(a0()) " + " cast-if(a1())] SUB-OP : [cast-if(a0()) " - " cast-if(a1())] + SUBW-OP : [cast-if(a0()) " - " cast-if(a1())] MUL-OP : [cast-if(a0()) " * " cast-if(a1()) ] DIV-OP : [cast-if(a0()) " / " cast-if(a1()) ] - MOD-OP : [cast-if(a0()) " % " cast-if(a1()) ] - QUO-OP : [cast-if(a0()) " / " cast-if(a1()) ] REM-OP : [cast-if(a0()) " % " cast-if(a1()) ] - ADD-WRAP-OP : [cast-if(a0()), " + " cast-if(a1())] - SUB-WRAP-OP : [cast-if(a0()), " - " cast-if(a1())] LESS-OP : [cast-if(a0()) " < " cast-if(a1())] LESS-EQ-OP : [cast-if(a0()) " <= " cast-if(a1())] GREATER-OP : [cast-if(a0()) " > " cast-if(a1())] GREATER-EQ-OP : [cast-if(a0()) " >= " cast-if(a1())] - NEQUIV-OP : [cast-if(a0()) " != " cast-if(a1())] - EQUIV-OP : [cast-if(a0()) " == " cast-if(a1())] - NEQUAL-OP : [cast-if(a0()) " != " cast-if(a1())] EQUAL-OP : [cast-if(a0()) " == " cast-if(a1())] - ;MUX-OP : [a0() " ? " cast(a1()) " : " cast(a2())] + NEQUAL-OP : [cast-if(a0()) " != " cast-if(a1())] PAD-OP : val w = long!(type(a0())) val diff = (to-long(c0()) - w) @@ -2491,6 +2561,7 @@ defn op-stream (doprim:DoPrim) -> Streamable : (t) : ["{{" diff "'d0 }, " a0() " }"] AS-UINT-OP : ["$unsigned(" a0() ")"] AS-SINT-OP : ["$signed(" a0() ")"] + AS-CLOCK-OP : ["$unsigned(" a0() ")"] DYN-SHIFT-LEFT-OP : [cast(a0()) " << " a1()] DYN-SHIFT-RIGHT-OP : match(type(doprim)) : @@ -2503,28 +2574,38 @@ defn op-stream (doprim:DoPrim) -> Streamable : match(type(a0())) : (t:UIntType) : ["{1'b0," cast(a0()) "}"] (t:SIntType) : [cast(a0())] - BIT-NOT-OP : ["~ " cast(a0())] - BIT-AND-OP : [cast(a0()) " & " cast(a1())] - BIT-OR-OP : [cast(a0()) " | " cast(a1())] - BIT-XOR-OP : [cast(a0()) " ^ " cast(a1())] - CONCAT-OP : ["{" cast(a0()) "," cast(a1()) "}"] - BIT-SELECT-OP : [a0() "[" c0() "]"] - BITS-SELECT-OP : [a0() "[" c0() ":" c1() "]"] - BIT-AND-REDUCE-OP : + NOT-OP : ["~ " a0()] + AND-OP : [cast-as(a0()) " & " cast-as(a1())] + OR-OP : [cast-as(a0()) " | " cast-as(a1())] + XOR-OP : [cast-as(a0()) " ^ " cast-as(a1())] + AND-REDUCE-OP : val v = Vector<Streamable>() for b in 0 to to-int(long!(type(doprim))) do : add(v,[cast(a0()) "[" b "]"]) join(v," & ") - BIT-OR-REDUCE-OP : + OR-REDUCE-OP : val v = Vector<Streamable>() for b in 0 to to-int(long!(type(doprim))) do : add(v,[cast(a0() ) "[" b "]"]) join(v," | ") - BIT-XOR-REDUCE-OP : + XOR-REDUCE-OP : val v = Vector<Streamable>() for b in 0 to to-int(long!(type(doprim))) do : add(v,[cast(a0() ) "[" b "]"]) join(v," ^ ") + CONCAT-OP : ["{" cast(a0()) "," cast(a1()) "}"] + BITS-SELECT-OP : + if c0() == c1() : [a0() "[" c0() "]"] + else : [a0() "[" c0() ":" c1() "]"] + HEAD-OP : + val w = long!(type(a0())) + val high = w - to-long(1) + val low = w - to-long(c0()) + [a0() "[" high ":" low "]"] + TAIL-OP : + val w = long!(type(a0())) + val low = w - to-long(c0()) - to-long(1) + [a0() "[" low ":" 0 "]"] defn emit-verilog (m:InModule) -> Module : mname = name(m) @@ -2723,7 +2804,7 @@ defn emit-verilog (m:InModule) -> Module : update(mem-port,data*,clk,AND(en*,mask*)) for rw in readwriters(s) do : - val rmode = mem-exp(rw,`rmode) + val wmode = mem-exp(rw,`wmode) val rdata = mem-exp(rw,`rdata) val data = mem-exp(rw,`data) val mask = mem-exp(rw,`mask) @@ -2731,7 +2812,7 @@ defn emit-verilog (m:InModule) -> Module : val en = mem-exp(rw,`en) val clk = mem-exp(rw,`clk) - declare(`wire,lowered-name(rmode),type(rmode)) + declare(`wire,lowered-name(wmode),type(wmode)) declare(`wire,lowered-name(rdata),type(rdata)) declare(`wire,lowered-name(data),type(data)) declare(`wire,lowered-name(mask),type(mask)) @@ -2746,13 +2827,13 @@ defn emit-verilog (m:InModule) -> Module : assign(addr,netlist[addr]) assign(mask,netlist[mask]) assign(en,netlist[en]) - assign(rmode,netlist[rmode]) + assign(wmode,netlist[wmode]) ; Delay new signals by latency val raddr* = delay(addr,read-latency(s),clk) val waddr* = delay(addr,write-latency(s) - 1,clk) val en* = delay(en,write-latency(s) - 1,clk) - val rmod* = delay(rmode,write-latency(s) - 1,clk) + val rmod* = delay(wmode,write-latency(s) - 1,clk) val data* = delay(data,write-latency(s) - 1,clk) val mask* = delay(mask,write-latency(s) - 1,clk) @@ -2761,7 +2842,7 @@ defn emit-verilog (m:InModule) -> Module : val rmem-port = WSubAccess(mem,raddr*,UnknownType(),UNKNOWN-GENDER) assign(rdata,rmem-port) val wmem-port = WSubAccess(mem,waddr*,UnknownType(),UNKNOWN-GENDER) - update(wmem-port,data*,clk,AND(AND(en*,mask*),NOT(rmode))) + update(wmem-port,data*,clk,AND(AND(en*,mask*),wmode)) (s:Begin) : map(build-streams,s) s diff --git a/src/main/stanza/primop.stanza b/src/main/stanza/primop.stanza index 4b8d0cbc..3d0b06a4 100644 --- a/src/main/stanza/primop.stanza +++ b/src/main/stanza/primop.stanza @@ -12,6 +12,7 @@ public defn set-primop-type (e:DoPrim) -> DoPrim : defn MAX (w1:Width,w2:Width) -> Width : MaxWidth(list(w1,w2)) defn MINUS (w1:Width,w2:Width) -> Width : MinusWidth(w1,w2) defn POW (w1:Width) -> Width : ExpWidth(w1) + defn MIN (w1:Width,w2:Width) -> Width : MinWidth(list(w1,w2)) val o = op(e) val a = args(e) val c = consts(e) @@ -38,20 +39,6 @@ public defn set-primop-type (e:DoPrim) -> DoPrim : (t1:SIntType, t2:UIntType) : SIntType(PLUS(MAX(w1(),w2()),ONE)) (t1:SIntType, t2:SIntType) : SIntType(PLUS(MAX(w1(),w2()),ONE)) (t1, t2) : UnknownType() - ADD-WRAP-OP : DoPrim{o,a,c,_} $ - match(t1(),t2()) : - (t1:UIntType, t2:UIntType) : UIntType(MAX(w1(),w2())) - (t1:UIntType, t2:SIntType) : SIntType(MAX(w1(),w2())) - (t1:SIntType, t2:UIntType) : SIntType(MAX(w1(),w2())) - (t1:SIntType, t2:SIntType) : SIntType(MAX(w1(),w2())) - (t1, t2) : UnknownType() - SUB-WRAP-OP : DoPrim{o,a,c,_} $ - match(t1(),t2()) : - (t1:UIntType, t2:UIntType) : UIntType(MAX(w1(),w2())) - (t1:UIntType, t2:SIntType) : SIntType(MAX(w1(),w2())) - (t1:SIntType, t2:UIntType) : SIntType(MAX(w1(),w2())) - (t1:SIntType, t2:SIntType) : SIntType(MAX(w1(),w2())) - (t1, t2) : UnknownType() MUL-OP : DoPrim{o,a,c,_} $ match(t1(),t2()) : (t1:UIntType, t2:UIntType) : UIntType(PLUS(w1(),w2())) @@ -62,58 +49,63 @@ public defn set-primop-type (e:DoPrim) -> DoPrim : DIV-OP : DoPrim{o,a,c,_} $ match(t1(),t2()) : (t1:UIntType, t2:UIntType) : UIntType(w1()) - (t1:UIntType, t2:SIntType) : SIntType(PLUS(w1(),w2())) + (t1:UIntType, t2:SIntType) : SIntType(PLUS(w1(),ONE)) (t1:SIntType, t2:UIntType) : SIntType(w1()) - (t1:SIntType, t2:SIntType) : SIntType(PLUS(w1(),w2())) + (t1:SIntType, t2:SIntType) : SIntType(PLUS(w1(),ONE)) (t1, t2) : UnknownType() - MOD-OP : DoPrim{o,a,c,_} $ + REM-OP : DoPrim{o,a,c,_} $ match(t1(),t2()) : - (t1:UIntType, t2:UIntType) : UIntType(w2()) - (t1:UIntType, t2:SIntType) : UIntType(w2()) - (t1:SIntType, t2:UIntType) : SIntType(PLUS(w2(),ONE)) - (t1:SIntType, t2:SIntType) : SIntType(w2()) + (t1:UIntType, t2:UIntType) : UIntType(MIN(w1(),w2())) + (t1:UIntType, t2:SIntType) : UIntType(MIN(w1(),w2())) + (t1:SIntType, t2:UIntType) : SIntType(MIN(w1(),PLUS(w2(),ONE))) + (t1:SIntType, t2:SIntType) : SIntType(MIN(w1(),w2())) (t1, t2) : UnknownType() - QUO-OP : DoPrim{o,a,c,_} $ + LESS-OP : DoPrim{o,a,c,_} $ match(t1(),t2()) : - (t1:UIntType, t2:UIntType) : UIntType(PLUS(w1(),ONE)) - (t1:UIntType, t2:SIntType) : SIntType(w1()) - (t1:SIntType, t2:UIntType) : SIntType(PLUS(w1(),ONE)) - (t1:SIntType, t2:SIntType) : SIntType(w1()) + (t1:UIntType|SIntType, t2:UIntType|SIntType) : BoolType() (t1, t2) : UnknownType() - REM-OP : DoPrim{o,a,c,_} $ + LESS-EQ-OP : DoPrim{o,a,c,_} $ match(t1(),t2()) : - (t1:UIntType, t2:UIntType) : UIntType(w2()) - (t1:UIntType, t2:SIntType) : SIntType(w2()) - (t1:SIntType, t2:UIntType) : UIntType(PLUS(w2(),ONE)) - (t1:SIntType, t2:SIntType) : SIntType(w2()) + (t1:UIntType|SIntType, t2:UIntType|SIntType) : BoolType() + (t1, t2) : UnknownType() + GREATER-OP : DoPrim{o,a,c,_} $ + match(t1(),t2()) : + (t1:UIntType|SIntType, t2:UIntType|SIntType) : BoolType() + (t1, t2) : UnknownType() + GREATER-EQ-OP : DoPrim{o,a,c,_} $ + match(t1(),t2()) : + (t1:UIntType|SIntType, t2:UIntType|SIntType) : BoolType() + (t1, t2) : UnknownType() + EQUAL-OP : DoPrim{o,a,c,_} $ + match(t1(),t2()) : + (t1:UIntType|SIntType, t2:UIntType|SIntType) : BoolType() + (t1, t2) : UnknownType() + NEQUAL-OP : DoPrim{o,a,c,_} $ + match(t1(),t2()) : + (t1:UIntType|SIntType, t2:UIntType|SIntType) : BoolType() (t1, t2) : UnknownType() - LESS-OP : DoPrim(o,a,c,BoolType()) - LESS-EQ-OP : DoPrim(o,a,c,BoolType()) - GREATER-OP : DoPrim(o,a,c,BoolType()) - GREATER-EQ-OP : DoPrim(o,a,c,BoolType()) - EQUAL-OP : DoPrim(o,a,c,BoolType()) - NEQUAL-OP : DoPrim(o,a,c,BoolType()) - EQUIV-OP : DoPrim(o,a,c,BoolType()) - NEQUIV-OP : DoPrim(o,a,c,BoolType()) - ;MUX-OP : DoPrim{o,a,c,_} $ - ; match(t2(),t3()) : - ; (t2:UIntType, t3:UIntType) : UIntType(MAX(w2(),w3())) - ; (t2:SIntType, t3:SIntType) : SIntType(MAX(w2(),w3())) - ; (t2, t3) : UnknownType() PAD-OP : DoPrim{o,a,c,_} $ match(t1()) : - (t1:UIntType) : UIntType(c1()) - (t1:SIntType) : SIntType(c1()) + (t1:UIntType) : UIntType(MAX(w1(),c1())) + (t1:SIntType) : SIntType(MAX(w1(),c1())) (t1) : UnknownType() AS-UINT-OP : DoPrim{o,a,c,_} $ match(t1()) : (t1:UIntType) : UIntType(w1()) (t1:SIntType) : UIntType(w1()) + (t1:ClockType) : UIntType(ONE) (t1) : UnknownType() AS-SINT-OP : DoPrim{o,a,c,_} $ match(t1()) : (t1:UIntType) : SIntType(w1()) (t1:SIntType) : SIntType(w1()) + (t1:ClockType) : SIntType(ONE) + (t1) : UnknownType() + AS-CLOCK-OP : DoPrim{o,a,c,_} $ + match(t1()) : + (t1:UIntType) : ClockType() + (t1:SIntType) : ClockType() + (t1:ClockType) : ClockType() (t1) : UnknownType() SHIFT-LEFT-OP : DoPrim{o,a,c,_} $ match(t1()) : @@ -143,30 +135,52 @@ public defn set-primop-type (e:DoPrim) -> DoPrim : NEG-OP : DoPrim{o,a,c,_} $ match(t1()) : (t1:UIntType) : SIntType(PLUS(w1(),ONE)) - (t1:SIntType) : SIntType(w1()) + (t1:SIntType) : SIntType(PLUS(w1(),ONE)) + (t1) : UnknownType() + NOT-OP : DoPrim{o,a,c,_} $ + match(t1()) : + (t1:UIntType|SIntType) : UIntType(w1()) + (t1) : UnknownType() + AND-OP : DoPrim{o,a,c,_} $ + match(t1(),t2()) : + (t1:UIntType|SIntType, t2:UIntType|SIntType) : UIntType(MAX(w1(),w2())) + (t1,t2) : UnknownType() + OR-OP : DoPrim{o,a,c,_} $ + match(t1(),t2()) : + (t1:UIntType|SIntType, t2:UIntType|SIntType) : UIntType(MAX(w1(),w2())) + (t1,t2) : UnknownType() + XOR-OP : DoPrim{o,a,c,_} $ + match(t1(),t2()) : + (t1:UIntType|SIntType, t2:UIntType|SIntType) : UIntType(MAX(w1(),w2())) + (t1,t2) : UnknownType() + AND-REDUCE-OP : DoPrim{o,a,c,_} $ + match(t1()) : + (t1:UIntType|SIntType) : BoolType() + (t1) : UnknownType() + OR-REDUCE-OP : DoPrim{o,a,c,_} $ + match(t1()) : + (t1:UIntType|SIntType) : BoolType() + (t1) : UnknownType() + XOR-REDUCE-OP : DoPrim{o,a,c,_} $ + match(t1()) : + (t1:UIntType|SIntType) : BoolType() (t1) : UnknownType() - BIT-NOT-OP : DoPrim(o,a,c,t1()) - BIT-AND-OP : DoPrim{o,a,c,_} $ + CONCAT-OP : DoPrim{o,a,c,_} $ + match(t1(),t2()) : + (t1:UIntType|SIntType, t2:UIntType|SIntType) : UIntType(PLUS(w1(),w2())) + (t1, t2) : UnknownType() + BITS-SELECT-OP : DoPrim{o,a,c,_} $ match(t1()) : - (t1:UIntType) : UIntType(MAX(w1(),w2())) - (t1:SIntType) : SIntType(MAX(w1(),w2())) + (t1:UIntType|SIntType) : UIntType(PLUS(MINUS(c1(),c2()),ONE)) (t1) : UnknownType() - BIT-OR-OP : DoPrim{o,a,c,_} $ + HEAD-OP : DoPrim{o,a,c,_} $ match(t1()) : - (t1:UIntType) : UIntType(MAX(w1(),w2())) - (t1:SIntType) : SIntType(MAX(w1(),w2())) + (t1:UIntType|SIntType) : UIntType(c1()) (t1) : UnknownType() - BIT-XOR-OP : DoPrim{o,a,c,_} $ + TAIL-OP : DoPrim{o,a,c,_} $ match(t1()) : - (t1:UIntType) : UIntType(MAX(w1(),w2())) - (t1:SIntType) : SIntType(MAX(w1(),w2())) + (t1:UIntType|SIntType) : UIntType(MINUS(w1(),c1())) (t1) : UnknownType() - BIT-AND-REDUCE-OP : DoPrim(o,a,c,BoolType()) - BIT-OR-REDUCE-OP : DoPrim(o,a,c,BoolType()) - BIT-XOR-REDUCE-OP : DoPrim(o,a,c,BoolType()) - CONCAT-OP : DoPrim(o,a,c,UIntType(PLUS(w1(),w2()))) - BIT-SELECT-OP : DoPrim(o,a,c,BoolType()) - BITS-SELECT-OP : DoPrim(o,a,c,UIntType(PLUS(MINUS(c1(),c2()),ONE))) ;public defn primop-gen-constraints (e:DoPrim,v:Vector<WGeq>) -> Type : ; defn get-max (i0:Int,i1:Int) -> Width : get-max(list(i0,i1)) @@ -185,7 +199,7 @@ public defn set-primop-type (e:DoPrim) -> DoPrim : ; (t0:UIntType,t1:SIntType) : PlusWidth(width!(args(e)[0]),IntWidth(1)) ; (t0:SIntType,t1:SIntType) : PlusWidth(width!(args(e)[0]),IntWidth(1)) ; (t0,t1) : width!(args(e)[0]) -; MOD-OP : +; REM-OP : ; match(type(args(e)[0]),type(args(e)[1])) : ; (t0:SIntType,t1:UIntType) : PlusWidth(width!(args(e)[1]),IntWidth(1)) ; (t0,t1) : width!(args(e)[1]) diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza index 21931dd9..9040a8bd 100644 --- a/src/main/stanza/verilog.stanza +++ b/src/main/stanza/verilog.stanza @@ -96,7 +96,7 @@ defn emit (e:Expression) -> String : SUB-OP : [emit-signed-if-any(args(e)[0],args(e)) " - " emit-signed-if-any(args(e)[1],args(e))] MUL-OP : [emit-signed-if-any(args(e)[0],args(e)) " * " emit-signed-if-any(args(e)[1],args(e)) ] DIV-OP : [emit-signed-if-any(args(e)[0],args(e)) " / " emit-signed-if-any(args(e)[1],args(e)) ] - MOD-OP : [emit-signed-if-any(args(e)[0],args(e)) " % " emit-signed-if-any(args(e)[1],args(e)) ] + REM-OP : [emit-signed-if-any(args(e)[0],args(e)) " % " emit-signed-if-any(args(e)[1],args(e)) ] QUO-OP : [emit-signed-if-any(args(e)[0],args(e)) " / " emit-signed-if-any(args(e)[1],args(e)) ] REM-OP : [emit-signed-if-any(args(e)[0],args(e)) " % " emit-signed-if-any(args(e)[1],args(e)) ] ADD-WRAP-OP : [emit-signed-if-any(args(e)[0],args(e)), " + " emit-signed-if-any(args(e)[1],args(e))] diff --git a/test/chirrtl/wacc-wdc.fir b/test/chirrtl/wacc-wdc.fir index 779722da..6610d295 100644 --- a/test/chirrtl/wacc-wdc.fir +++ b/test/chirrtl/wacc-wdc.fir @@ -24,17 +24,15 @@ circuit top : ; CHECK: wire p : UInt ; CHECK: wire q : UInt ; CHECK: mem m : -; CHECK: data-type: { a : UInt<4>, b : UInt<4>} -; CHECK: depth: 10 -; CHECK: write-latency: 1 -; CHECK: read-latency: 0 -; CHECK: writer: a -; CHECK: poison GEN_0 : UInt<4> -; CHECK: poison GEN_1 : { a : UInt<4>, b : UInt<4>} -; CHECK: m.a.addr <= GEN_0 +; CHECK: data-type => { a : UInt<4>, b : UInt<4>} +; CHECK: depth => 10 +; CHECK: write-latency => 1 +; CHECK: read-latency => 0 +; CHECK: writer => a +; CHECK: m.a.addr is invalid ; CHECK: m.a.clk <= clk ; CHECK: m.a.en <= UInt("h0") -; CHECK: m.a.data <= GEN_1 +; CHECK: m.a.data is invalid ; CHECK: m.a.mask.a <= UInt("h0") ; CHECK: m.a.mask.b <= UInt("h0") ; CHECK: p <= UInt("h1") diff --git a/test/errors/gender/BulkWrong.fir b/test/errors/gender/BulkWrong.fir index 1becd104..c9b24aa2 100644 --- a/test/errors/gender/BulkWrong.fir +++ b/test/errors/gender/BulkWrong.fir @@ -18,7 +18,7 @@ circuit BTB : in.y <- w.y in.y.z <- w.y.z - w.x <= addw(in.x,in.y.z) + w.x <= add(in.x,in.y.z) out <- in in.y <- out.y diff --git a/test/errors/high-form/RemoveChar.fir b/test/errors/high-form/RemoveChar.fir index 9341468c..aa5e8227 100644 --- a/test/errors/high-form/RemoveChar.fir +++ b/test/errors/high-form/RemoveChar.fir @@ -6,7 +6,7 @@ circuit Top : wire x_1 : UInt<1> x_1 <= UInt(1) wire x : UInt<1> - x <= addw(addw(UInt(1),UInt(1)),UInt(1)) + x <= add(add(UInt(1),UInt(1)),UInt(1)) diff --git a/test/features/IsInvalid.fir b/test/features/IsInvalid.fir index cf898fe9..dc7c56b4 100644 --- a/test/features/IsInvalid.fir +++ b/test/features/IsInvalid.fir @@ -12,9 +12,10 @@ circuit Top : write-latency => 1 reader => r writer => w - read-writer => rw + readwriter => rw wire x : { w : UInt<42>, x : UInt<20>} - reg c : { w : UInt<42>, x : UInt<20>},clk,reset,x + reg c : { w : UInt<42>, x : UInt<20>},clk with : + reset => (reset,x) inst other of Other clk is invalid @@ -52,7 +53,7 @@ circuit Top : ;CHECK: m.w.addr is invalid ;CHECK: m.w.en is invalid ;CHECK: m.w.clk is invalid -;CHECK: m.rw.rmode is invalid +;CHECK: m.rw.wmode is invalid ;CHECK: m.rw.data[0] is invalid ;CHECK: m.rw.data[1] is invalid ;CHECK: m.rw.data[2] is invalid diff --git a/test/features/OptionalRegisterReset.fir b/test/features/OptionalRegisterReset.fir new file mode 100644 index 00000000..54a90b67 --- /dev/null +++ b/test/features/OptionalRegisterReset.fir @@ -0,0 +1,17 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s +circuit Top : + module Top : + input clk : Clock + input reset : UInt<1> + input a : UInt<32> + input p : UInt<1> + output b : UInt<32> + reg r1:UInt<32> clk with : + reset => (reset, a) + when p : + b <= r1 + else : + b <= r1 + + +;CHECK: Done! diff --git a/test/features/Poison.fir b/test/features/Poison.fir index a4cb1a25..9aafe63f 100644 --- a/test/features/Poison.fir +++ b/test/features/Poison.fir @@ -16,7 +16,7 @@ circuit Poison : write-latency => 2 reader => r writer => w - read-writer => rw + readwriter => rw m.r.addr <= index m.r.en <= UInt(1) m.r.clk <= clk @@ -29,7 +29,7 @@ circuit Poison : m.rw.clk <= clk m.rw.addr <= index m.rw.en <= UInt(1) - m.rw.rmode <= UInt(1) + m.rw.wmode <= UInt(1) m.rw.mask <= wmask m.rw.data <= q when p : diff --git a/test/features/Printf.fir b/test/features/Printf.fir index 4e8682ff..d4d2f77d 100644 --- a/test/features/Printf.fir +++ b/test/features/Printf.fir @@ -17,5 +17,5 @@ circuit Top : ;CHECK: printf(clk, en, "Hello World!\n") ;CHECK: printf(clk, en, "Hello World! %x\n", x.y) ;CHECK: printf(clk, and(p, en), "In consequence\n") -;CHECK: printf(clk, and(eqv(p, UInt("h0")), en), "In alternate\n") +;CHECK: printf(clk, and(eq(p, UInt("h0")), en), "In alternate\n") ;CHECK: Done! diff --git a/test/features/Queue.fir b/test/features/Queue.fir index 9b19caf4..3ce58e31 100644 --- a/test/features/Queue.fir +++ b/test/features/Queue.fir @@ -7,6 +7,7 @@ circuit Queue : input clk : Clock input reset : UInt<1> - reg r : UInt<10>,clk,reset,in + reg r : UInt<10>,clk with : + reset => (reset,in) r <= in out <= r diff --git a/test/features/TwoClocks.fir b/test/features/TwoClocks.fir index 6562d3e1..3753ee8d 100644 --- a/test/features/TwoClocks.fir +++ b/test/features/TwoClocks.fir @@ -5,14 +5,18 @@ circuit Top : input clk2 : Clock input reset1 : UInt<1> input reset2 : UInt<1> - reg src : UInt<10>, clk1, reset1, UInt(0) - reg sink : UInt<10>, clk2, reset2, UInt(0) + reg src : UInt<10>, clk1 with : + reset => ( reset1, UInt(0)) + reg sink : UInt<10>, clk2 with : + reset => ( reset2, UInt(0)) - src <= addw(src,UInt(1)) + src <= add(src,UInt(1)) - reg sync_A : UInt<10>, clk2, reset2, UInt(0) + reg sync_A : UInt<10>, clk2 with : + reset => ( reset2, UInt(0)) sync_A <= src - reg sync_B : UInt<10>, clk2, reset2, UInt(0) + reg sync_B : UInt<10>, clk2 with : + reset => ( reset2, UInt(0)) sync_B <= sync_A sink <= sync_B diff --git a/test/features/VerilogReg.fir b/test/features/VerilogReg.fir index 33c4417f..96022933 100644 --- a/test/features/VerilogReg.fir +++ b/test/features/VerilogReg.fir @@ -7,7 +7,8 @@ circuit Poison : input p1 : UInt<1> input p2 : UInt<1> input p3 : UInt<1> - reg r : UInt<32>,clk,reset,r + reg r : UInt<32>,clk with : + reset => (reset,r) when p1 : r <= UInt(1) when p2 : diff --git a/test/passes/expand-whens/bundle-init.fir b/test/passes/expand-whens/bundle-init.fir index c4b9f314..f4ae9f6a 100644 --- a/test/passes/expand-whens/bundle-init.fir +++ b/test/passes/expand-whens/bundle-init.fir @@ -5,7 +5,8 @@ circuit top : input clk : Clock input reset : UInt<1> wire w : { x : UInt, y : UInt} - reg r : { x : UInt, y : UInt},clk,reset,w + reg r : { x : UInt, y : UInt},clk with : + reset => (reset,w) wire a : UInt wire b : UInt a <= UInt(1) diff --git a/test/passes/expand-whens/nested-whens.fir b/test/passes/expand-whens/nested-whens.fir index 9a9d56d4..68409931 100644 --- a/test/passes/expand-whens/nested-whens.fir +++ b/test/passes/expand-whens/nested-whens.fir @@ -12,7 +12,8 @@ circuit top : wire y : UInt wire z : UInt wire w : UInt - reg r : UInt, clk, reset, w + reg r : UInt, clk with : + reset => (reset, w) p <= UInt(1) q <= UInt(1) a <= UInt(1) diff --git a/test/passes/expand-whens/partial-init.fir b/test/passes/expand-whens/partial-init.fir index 490ac995..2fb54717 100644 --- a/test/passes/expand-whens/partial-init.fir +++ b/test/passes/expand-whens/partial-init.fir @@ -17,7 +17,8 @@ circuit top : init[7] <= x init[8] <= x init[9] <= x - reg r : UInt<1>[10],clk,reset,init + reg r : UInt<1>[10],clk with : + reset => (reset,init) r[0] <= UInt(1) r[1] <= UInt(1) r[2] <= UInt(1) diff --git a/test/passes/expand-whens/reg-dwc.fir b/test/passes/expand-whens/reg-dwc.fir index 024b527c..e8267861 100644 --- a/test/passes/expand-whens/reg-dwc.fir +++ b/test/passes/expand-whens/reg-dwc.fir @@ -5,7 +5,8 @@ circuit top : input reset : UInt<1> wire p : UInt p <= UInt(1) - reg r : UInt,clk,reset,r + reg r : UInt,clk with : + reset => (reset,r) when p : r <= UInt(2) diff --git a/test/passes/expand-whens/reg-wdc.fir b/test/passes/expand-whens/reg-wdc.fir index 4ddea427..b19b8bca 100644 --- a/test/passes/expand-whens/reg-wdc.fir +++ b/test/passes/expand-whens/reg-wdc.fir @@ -6,7 +6,8 @@ circuit top : wire p : UInt p <= UInt(1) when p : - reg r : UInt,clk,reset,r + reg r : UInt,clk with : + reset => (reset,r) r <= UInt(2) ; CHECK: Expand Whens @@ -14,7 +15,8 @@ circuit top : ; CHECK: circuit top : ; CHECK: module top : ; CHECK: wire p : UInt -; CHECK: reg r : UInt<2>, clk, reset, r +; CHECK: reg r : UInt<2>, clk with : +; CHECK: reset => (reset, r) ; CHECK: p <= UInt("h1") ; CHECK-NOT: r <= mux(p, UInt("h2"), r) ; CHECK: r <= UInt("h2") diff --git a/test/passes/infer-types/gcd.fir b/test/passes/infer-types/gcd.fir index 938cb345..d419ce35 100644 --- a/test/passes/infer-types/gcd.fir +++ b/test/passes/infer-types/gcd.fir @@ -6,8 +6,8 @@ circuit top : input x : UInt input y : UInt output z : UInt - z <= subw(x, y) - ;CHECK: z@<t:UInt> <= subw(x@<t:UInt>, y@<t:UInt>)@<t:UInt> + z <= tail(sub(x, y),1) + ;CHECK: z@<t:UInt> <= tail(sub(x@<t:UInt>, y@<t:UInt>)@<t:SInt>, 1)@<t:UInt> module gcd : input a : UInt<16> input b : UInt<16> @@ -15,9 +15,12 @@ circuit top : input clk : Clock input reset : UInt<1> output z : UInt<16> - reg x : UInt,clk,reset,UInt(0) - reg y : UInt,clk,reset,UInt(42) - ; CHECK: reg x : UInt, clk@<t:Clock>, reset@<t:UInt>, UInt("h0")@<t:UInt>@<t:UInt> + reg x : UInt,clk with : + reset => (reset,UInt(0)) + reg y : UInt,clk with : + reset => (reset,UInt(42)) + ; CHECK: reg x : UInt, clk@<t:Clock> with : + ;CHECK:reset => (reset@<t:UInt>, UInt("h0")@<t:UInt>) when gt(x, y) : ;CHECK: when gt(x@<t:UInt>, y@<t:UInt>)@<t:UInt> : inst s of subtracter diff --git a/test/passes/infer-types/primops.fir b/test/passes/infer-types/primops.fir index 102a94ae..de0f9f1d 100644 --- a/test/passes/infer-types/primops.fir +++ b/test/passes/infer-types/primops.fir @@ -3,6 +3,7 @@ ;CHECK: Infer Types circuit top : module top : + input clk : Clock wire a : UInt<16> wire b : UInt<8> wire c : SInt<16> @@ -39,36 +40,12 @@ circuit top : node ydiv = div(c, b) ;CHECK: node ydiv = div(c@<t:SInt>, b@<t:UInt>)@<t:SInt> node zdiv = div(c, d) ;CHECK: node zdiv = div(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - node vmod = mod(a, c) ;CHECK: node vmod = mod(a@<t:UInt>, c@<t:SInt>)@<t:UInt> - node wmod = mod(a, b) ;CHECK: node wmod = mod(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xmod = mod(a, d) ;CHECK: node xmod = mod(a@<t:UInt>, d@<t:SInt>)@<t:UInt> - node ymod = mod(c, b) ;CHECK: node ymod = mod(c@<t:SInt>, b@<t:UInt>)@<t:SInt> - node zmod = mod(c, d) ;CHECK: node zmod = mod(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - - node vquo = quo(a, c) ;CHECK: node vquo = quo(a@<t:UInt>, c@<t:SInt>)@<t:SInt> - node wquo = quo(a, b) ;CHECK: node wquo = quo(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xquo = quo(a, d) ;CHECK: node xquo = quo(a@<t:UInt>, d@<t:SInt>)@<t:SInt> - node yquo = quo(c, b) ;CHECK: node yquo = quo(c@<t:SInt>, b@<t:UInt>)@<t:SInt> - node zquo = quo(c, d) ;CHECK: node zquo = quo(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - - node vrem = rem(a, c) ;CHECK: node vrem = rem(a@<t:UInt>, c@<t:SInt>)@<t:SInt> + node vrem = rem(a, c) ;CHECK: node vrem = rem(a@<t:UInt>, c@<t:SInt>)@<t:UInt> node wrem = rem(a, b) ;CHECK: node wrem = rem(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xrem = rem(a, d) ;CHECK: node xrem = rem(a@<t:UInt>, d@<t:SInt>)@<t:SInt> - node yrem = rem(c, b) ;CHECK: node yrem = rem(c@<t:SInt>, b@<t:UInt>)@<t:UInt> + node xrem = rem(a, d) ;CHECK: node xrem = rem(a@<t:UInt>, d@<t:SInt>)@<t:UInt> + node yrem = rem(c, b) ;CHECK: node yrem = rem(c@<t:SInt>, b@<t:UInt>)@<t:SInt> node zrem = rem(c, d) ;CHECK: node zrem = rem(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - node vaddw = addw(a, c) ;CHECK: node vaddw = addw(a@<t:UInt>, c@<t:SInt>)@<t:SInt> - node waddw = addw(a, b) ;CHECK: node waddw = addw(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xaddw = addw(a, d) ;CHECK: node xaddw = addw(a@<t:UInt>, d@<t:SInt>)@<t:SInt> - node yaddw = addw(c, b) ;CHECK: node yaddw = addw(c@<t:SInt>, b@<t:UInt>)@<t:SInt> - node zaddw = addw(c, d) ;CHECK: node zaddw = addw(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - - node vsubw = subw(a, c) ;CHECK: node vsubw = subw(a@<t:UInt>, c@<t:SInt>)@<t:SInt> - node wsubw = subw(a, b) ;CHECK: node wsubw = subw(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xsubw = subw(a, d) ;CHECK: node xsubw = subw(a@<t:UInt>, d@<t:SInt>)@<t:SInt> - node ysubw = subw(c, b) ;CHECK: node ysubw = subw(c@<t:SInt>, b@<t:UInt>)@<t:SInt> - node zsubw = subw(c, d) ;CHECK: node zsubw = subw(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - node vlt = lt(a, c) ;CHECK: node vlt = lt(a@<t:UInt>, c@<t:SInt>)@<t:UInt> node wlt = lt(a, b) ;CHECK: node wlt = lt(a@<t:UInt>, b@<t:UInt>)@<t:UInt> node xlt = lt(a, d) ;CHECK: node xlt = lt(a@<t:UInt>, d@<t:SInt>)@<t:UInt> @@ -105,29 +82,21 @@ circuit top : node yneq = neq(c, b) ;CHECK: node yneq = neq(c@<t:SInt>, b@<t:UInt>)@<t:UInt> node zneq = neq(c, d) ;CHECK: node zneq = neq(c@<t:SInt>, d@<t:SInt>)@<t:UInt> - node vneqv = neqv(a, b) ;CHECK: node vneqv = neqv(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node wneqv = neqv(a, b) ;CHECK: node wneqv = neqv(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node zneqv = neqv(c, d) ;CHECK: node zneqv = neqv(c@<t:SInt>, d@<t:SInt>)@<t:UInt> - - node veqv = eqv(a, b) ;CHECK: node veqv = eqv(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node weqv = eqv(a, b) ;CHECK: node weqv = eqv(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node zeqv = eqv(c, d) ;CHECK: node zeqv = eqv(c@<t:SInt>, d@<t:SInt>)@<t:UInt> - - node vmux = mux(e, a, b) ;CHECK: node vmux = mux(e@<t:UInt>, a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node wmux = mux(e, a, b) ;CHECK: node wmux = mux(e@<t:UInt>, a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node zmux = mux(e, c, d) ;CHECK: node zmux = mux(e@<t:UInt>, c@<t:SInt>, d@<t:SInt>)@<t:SInt> - node vpad = pad(a, 10) ;CHECK: node vpad = pad(a@<t:UInt>, 10)@<t:UInt> node wpad = pad(a, 10) ;CHECK: node wpad = pad(a@<t:UInt>, 10)@<t:UInt> node zpad = pad(c, 10) ;CHECK: node zpad = pad(c@<t:SInt>, 10)@<t:SInt> - node vasUInt = asUInt(d) ;CHECK: node vasUInt = asUInt(d@<t:SInt>)@<t:UInt> + node vasUInt = asUInt(d) ;CHECK: node vasUInt = asUInt(d@<t:SInt>)@<t:UInt> node wasUInt = asUInt(a) ;CHECK: node wasUInt = asUInt(a@<t:UInt>)@<t:UInt> - node zasUInt = asUInt(c) ;CHECK: node zasUInt = asUInt(c@<t:SInt>)@<t:UInt> + node zasUInt = asUInt(clk) ;CHECK: node zasUInt = asUInt(clk@<t:Clock>)@<t:UInt> + + node vasSInt = asSInt(a) ;CHECK: node vasSInt = asSInt(a@<t:UInt>)@<t:SInt> + node wasSInt = asSInt(c) ;CHECK: node wasSInt = asSInt(c@<t:SInt>)@<t:SInt> + node zasSInt = asSInt(clk) ;CHECK: node zasSInt = asSInt(clk@<t:Clock>)@<t:SInt> - node vasSInt = asSInt(a) ;CHECK: node vasSInt = asSInt(a@<t:UInt>)@<t:SInt> - node wasSInt = asSInt(a) ;CHECK: node wasSInt = asSInt(a@<t:UInt>)@<t:SInt> - node zasSInt = asSInt(c) ;CHECK: node zasSInt = asSInt(c@<t:SInt>)@<t:SInt> + node vasClock = asClock(a) ;CHECK: node vasClock = asClock(a@<t:UInt>)@<t:Clock> + node wasClock = asClock(c) ;CHECK: node wasClock = asClock(c@<t:SInt>)@<t:Clock> + node zasClock = asClock(clk) ;CHECK: node zasClock = asClock(clk@<t:Clock>)@<t:Clock> node vshl = shl(a, 10) ;CHECK: node vshl = shl(a@<t:UInt>, 10)@<t:UInt> node wshl = shl(a, 10) ;CHECK: node wshl = shl(a@<t:UInt>, 10)@<t:UInt> @@ -145,7 +114,6 @@ circuit top : node wshr = shr(a, 10) ;CHECK: node wshr = shr(a@<t:UInt>, 10)@<t:UInt> node zshr = shr(c, 10) ;CHECK: node zshr = shr(c@<t:SInt>, 10)@<t:SInt> - node vcvt = cvt(a) ;CHECK: node vcvt = cvt(a@<t:UInt>)@<t:SInt> node wcvt = cvt(a) ;CHECK: node wcvt = cvt(a@<t:UInt>)@<t:SInt> node zcvt = cvt(c) ;CHECK: node zcvt = cvt(c@<t:SInt>)@<t:SInt> @@ -155,19 +123,16 @@ circuit top : node zneg = neg(c) ;CHECK: node zneg = neg(c@<t:SInt>)@<t:SInt> node wnot = not(a) ;CHECK: node wnot = not(a@<t:UInt>)@<t:UInt> - node unot = not(c) ;CHECK: node unot = not(c@<t:SInt>)@<t:SInt> + node unot = not(c) ;CHECK: node unot = not(c@<t:SInt>)@<t:UInt> node WAND = and(a, b) ;CHECK: node WAND = and(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node uand = and(c, d) ;CHECK: node uand = and(c@<t:SInt>, d@<t:SInt>)@<t:SInt> + node uand = and(c, d) ;CHECK: node uand = and(c@<t:SInt>, d@<t:SInt>)@<t:UInt> node WOR = or(a, b) ;CHECK: node WOR = or(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node uor = or(c, d) ;CHECK: node uor = or(c@<t:SInt>, d@<t:SInt>)@<t:SInt> + node uor = or(c, d) ;CHECK: node uor = or(c@<t:SInt>, d@<t:SInt>)@<t:UInt> node wxor = xor(a, b) ;CHECK: node wxor = xor(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node uxor = xor(c, d) ;CHECK: node uxor = xor(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - - node wbit = bit(a, 0) ;CHECK: node wbit = bit(a@<t:UInt>, 0)@<t:UInt> - node ubit = bit(c, 0) ;CHECK: node ubit = bit(c@<t:SInt>, 0)@<t:UInt> + node uxor = xor(c, d) ;CHECK: node uxor = xor(c@<t:SInt>, d@<t:SInt>)@<t:UInt> node wbits = bits(a, 2, 0) ;CHECK: node wbits = bits(a@<t:UInt>, 2, 0)@<t:UInt> node ubits = bits(c, 2, 0) ;CHECK: node ubits = bits(c@<t:SInt>, 2, 0)@<t:UInt> @@ -178,4 +143,10 @@ circuit top : node uorr = orr(a, b, a) ;CHECK: node uorr = orr(a@<t:UInt>, b@<t:UInt>, a@<t:UInt>)@<t:UInt> node uxorr = xorr(a, b, a) ;CHECK: node uxorr = xorr(a@<t:UInt>, b@<t:UInt>, a@<t:UInt>)@<t:UInt> + node whead = head(a, 2) ;CHECK: node whead = head(a@<t:UInt>, 2)@<t:UInt> + node uhead = head(c, 2) ;CHECK: node uhead = head(c@<t:SInt>, 2)@<t:UInt> + + node wtail = tail(a, 2) ;CHECK: node wtail = tail(a@<t:UInt>, 2)@<t:UInt> + node utail = tail(c, 2) ;CHECK: node utail = tail(c@<t:SInt>, 2)@<t:UInt> + ;CHECK: Finished Infer Types diff --git a/test/passes/infer-widths/gcd.fir b/test/passes/infer-widths/gcd.fir index 7745a933..1333fbda 100644 --- a/test/passes/infer-widths/gcd.fir +++ b/test/passes/infer-widths/gcd.fir @@ -6,7 +6,7 @@ circuit top : input x : UInt input y : UInt output q : UInt - q <= subw(x, y) + q <= tail(sub(x, y),1) module gcd : input a : UInt<16> input b : UInt<16> @@ -14,8 +14,10 @@ circuit top : input clk : Clock input reset : UInt<1> output z : UInt<16> - reg x : UInt,clk,reset,UInt(0) - reg y : UInt,clk,reset,UInt(42) + reg x : UInt,clk with : + reset => (reset,UInt(0)) + reg y : UInt,clk with : + reset => (reset,UInt(42)) when gt(x, y) : inst s of subtracter s.x <= x diff --git a/test/passes/infer-widths/shr.fir b/test/passes/infer-widths/shr.fir index 67b6896e..6a918ba9 100644 --- a/test/passes/infer-widths/shr.fir +++ b/test/passes/infer-widths/shr.fir @@ -20,11 +20,16 @@ circuit MemSerdes : node T_218961 = cat(wide.req_cmd.bits.tag, wide.req_cmd.bits.rw) node T_218962 = cat(wide.req_cmd.bits.addr, T_218961) - reg out_buf : UInt, clock, reset, out_buf - reg in_buf : UInt, clock, reset, in_buf - reg state : UInt<3>, clock, reset,UInt<3>("h00") - reg send_cnt : UInt<3>, clock, reset, UInt<3>("h00") - reg data_send_cnt : UInt<2>, clock, reset, UInt<2>("h00") + reg out_buf : UInt, clock with : + reset => ( reset, out_buf) + reg in_buf : UInt, clock with : + reset => ( reset, in_buf) + reg state : UInt<3>, clock with : + reset => ( reset,UInt<3>("h00")) + reg send_cnt : UInt<3>, clock with : + reset => ( reset, UInt<3>("h00")) + reg data_send_cnt : UInt<2>, clock with : + reset => ( reset, UInt<2>("h00")) node T_218984 = eq(send_cnt, UInt<2>("h02")) node adone = and(narrow.req.ready, T_218984) node T_218987 = eq(send_cnt, UInt<3>("h07")) @@ -32,7 +37,7 @@ circuit MemSerdes : node T_218989 = and(narrow.req.valid, narrow.req.ready) when T_218989 : - node T_218991 = addw(send_cnt, UInt<1>("h01")) + node T_218991 = tail(add(send_cnt, UInt<1>("h01")),1) send_cnt <= T_218991 node T_218992 = shr(out_buf, 16) out_buf <= T_218992 @@ -87,24 +92,27 @@ circuit MemSerdes : node T_219015 = eq(state, UInt<3>("h04")) node T_219016 = and(T_219015, ddone) when T_219016 : - node T_219018 = addw(data_send_cnt, UInt<1>("h01")) + node T_219018 = tail(add(data_send_cnt, UInt<1>("h01")),1) data_send_cnt <= T_219018 node T_219020 = eq(data_send_cnt, UInt<2>("h03")) node T_219021 = mux(T_219020, UInt<3>("h00"), UInt<3>("h03")) state <= T_219021 send_cnt <= UInt<1>("h00") - reg recv_cnt : UInt<4>, clock, reset, UInt<4>("h00") - reg data_recv_cnt : UInt<2>, clock, reset, UInt<2>("h00") - reg resp_val : UInt<1>, clock, reset, UInt<1>("h00") + reg recv_cnt : UInt<4>, clock with : + reset => ( reset, UInt<4>("h00")) + reg data_recv_cnt : UInt<2>, clock with : + reset => ( reset, UInt<2>("h00")) + reg resp_val : UInt<1>, clock with : + reset => ( reset, UInt<1>("h00")) resp_val <= UInt<1>("h00") when narrow.resp.valid : - node T_219031 = addw(recv_cnt, UInt<1>("h01")) + node T_219031 = tail(add(recv_cnt, UInt<1>("h01")),1) recv_cnt <= T_219031 node T_219033 = eq(recv_cnt, UInt<4>("h08")) when T_219033 : recv_cnt <= UInt<1>("h00") - node T_219036 = addw(data_recv_cnt, UInt<1>("h01")) + node T_219036 = tail(add(data_recv_cnt, UInt<1>("h01")),1) data_recv_cnt <= T_219036 resp_val <= UInt<1>("h01") node T_219038 = bits(in_buf, 143, 16) diff --git a/test/passes/infer-widths/simple.fir b/test/passes/infer-widths/simple.fir index dc3007f9..63b31a32 100644 --- a/test/passes/infer-widths/simple.fir +++ b/test/passes/infer-widths/simple.fir @@ -7,7 +7,8 @@ circuit top : input reset : UInt<1> wire e : UInt<30> e <= UInt(1) - reg y : UInt,clk,reset,y + reg y : UInt,clk with : + reset => (reset,y) y <= e wire a : UInt<20> diff --git a/test/passes/jacktest/ALUTop.fir b/test/passes/jacktest/ALUTop.fir index 74abe0bd..a0aadb11 100644 --- a/test/passes/jacktest/ALUTop.fir +++ b/test/passes/jacktest/ALUTop.fir @@ -9,8 +9,8 @@ circuit ALUTop : input alu_op : UInt<4> node shamt = bits(B, 4, 0) - node T_157 = addw(A, B) - node T_158 = subw(A, B) + node T_157 = tail(add(A, B),1) + node T_158 = tail(sub(A, B),1) node T_159 = cvt(A) node T_160 = dshr(T_159, shamt) node T_161 = asUInt(T_160) @@ -50,10 +50,10 @@ circuit ALUTop : node oot = mux(T_194, T_157, T_193) node T_195 = bits(oot, 31, 0) out <= T_195 - node T_196 = bit(alu_op, 0) - node T_197 = subw(UInt<1>(0), B) + node T_196 = bits(alu_op, 0, 0) + node T_197 = tail(sub(UInt<1>(0), B),1) node T_198 = mux(T_196, T_197, B) - node T_199 = addw(A, T_198) + node T_199 = tail(add(A, T_198),1) sum <= T_199 module ALUdec : input opcode : UInt<7> diff --git a/test/passes/jacktest/Counter.fir b/test/passes/jacktest/Counter.fir index 4e23ba26..266c1849 100644 --- a/test/passes/jacktest/Counter.fir +++ b/test/passes/jacktest/Counter.fir @@ -8,9 +8,10 @@ circuit Counter : output tot : UInt<8> input amt : UInt<4> - reg T_13 : UInt<8>,clk,reset,UInt<8>(0) + reg T_13 : UInt<8>,clk with : + reset => (reset,UInt<8>(0)) when inc : - node T_14 = addw(T_13, amt) + node T_14 = tail(add(T_13, amt),1) node T_15 = gt(T_14, UInt<8>(255)) node T_16 = mux(T_15, UInt<1>(0), T_14) T_13 <= T_16 diff --git a/test/passes/jacktest/EnableShiftRegister.fir b/test/passes/jacktest/EnableShiftRegister.fir index d7e91665..9927e83f 100644 --- a/test/passes/jacktest/EnableShiftRegister.fir +++ b/test/passes/jacktest/EnableShiftRegister.fir @@ -8,10 +8,14 @@ circuit EnableShiftRegister : output out : UInt<4> input shift : UInt<1> - reg r0 : UInt<4>,clk,reset,UInt<4>(0) - reg r1 : UInt<4>,clk,reset,UInt<4>(0) - reg r2 : UInt<4>,clk,reset,UInt<4>(0) - reg r3 : UInt<4>,clk,reset,UInt<4>(0) + reg r0 : UInt<4>,clk with : + reset => (reset,UInt<4>(0)) + reg r1 : UInt<4>,clk with : + reset => (reset,UInt<4>(0)) + reg r2 : UInt<4>,clk with : + reset => (reset,UInt<4>(0)) + reg r3 : UInt<4>,clk with : + reset => (reset,UInt<4>(0)) when shift : r0 <= in r1 <= r0 diff --git a/test/passes/jacktest/LFSR16.fir b/test/passes/jacktest/LFSR16.fir index a4052623..b3fb05cc 100644 --- a/test/passes/jacktest/LFSR16.fir +++ b/test/passes/jacktest/LFSR16.fir @@ -7,14 +7,15 @@ circuit LFSR16 : input clk : Clock input reset : UInt<1> - reg res : UInt<16>,clk,reset,UInt<16>(1) + reg res : UInt<16>,clk with : + reset => (reset,UInt<16>(1)) when inc : - node T_16 = bit(res, 0) - node T_17 = bit(res, 2) + node T_16 = bits(res, 0, 0) + node T_17 = bits(res, 2, 2) node T_18 = xor(T_16, T_17) - node T_19 = bit(res, 3) + node T_19 = bits(res, 3, 3) node T_20 = xor(T_18, T_19) - node T_21 = bit(res, 5) + node T_21 = bits(res, 5, 5) node T_22 = xor(T_20, T_21) node T_23 = bits(res, 15, 1) node T_24 = cat(T_22, T_23) diff --git a/test/passes/jacktest/MemorySearch.fir b/test/passes/jacktest/MemorySearch.fir index 1abc50a2..39c19dda 100644 --- a/test/passes/jacktest/MemorySearch.fir +++ b/test/passes/jacktest/MemorySearch.fir @@ -9,7 +9,8 @@ circuit MemorySearch : input reset : UInt<1> output done : UInt<1> - reg index : UInt<3>,clk,reset,UInt<3>(0) + reg index : UInt<3>,clk with : + reset => (reset,UInt<3>(0)) wire elts : UInt<4>[7] elts[0] <= UInt<4>(0) elts[1] <= UInt<4>(4) @@ -28,7 +29,7 @@ circuit MemorySearch : else : node T_39 = not(end) when T_39 : - node T_40 = addw(index, UInt<1>(1)) + node T_40 = tail(add(index, UInt<1>(1)),1) index <= T_40 done <= end address <= index diff --git a/test/passes/jacktest/ModuleVec.fir b/test/passes/jacktest/ModuleVec.fir index 9a8e7f2c..6f9b699b 100644 --- a/test/passes/jacktest/ModuleVec.fir +++ b/test/passes/jacktest/ModuleVec.fir @@ -5,13 +5,13 @@ circuit ModuleVec : input in : UInt<32> output out : UInt<32> - node T_33 = addw(in, UInt<1>(1)) + node T_33 = tail(add(in, UInt<1>(1)),1) out <= T_33 module PlusOne_25 : input in : UInt<32> output out : UInt<32> - node T_34 = addw(in, UInt<1>(1)) + node T_34 = tail(add(in, UInt<1>(1)),1) out <= T_34 module ModuleVec : input ins : UInt<32>[2] diff --git a/test/passes/jacktest/RegisterVecShift.fir b/test/passes/jacktest/RegisterVecShift.fir index 61376a62..f138d00a 100644 --- a/test/passes/jacktest/RegisterVecShift.fir +++ b/test/passes/jacktest/RegisterVecShift.fir @@ -9,7 +9,8 @@ circuit RegisterVecShift : input shift : UInt<1> input ins : UInt<4>[4] - reg delays : UInt<4>[4],clk,reset,delays + reg delays : UInt<4>[4],clk with : + reset => (reset,delays) when reset : wire T_33 : UInt<4>[4] T_33[0] <= UInt<4>(0) diff --git a/test/passes/jacktest/RouterUnitTest.fir b/test/passes/jacktest/RouterUnitTest.fir new file mode 100644 index 00000000..dec4083e --- /dev/null +++ b/test/passes/jacktest/RouterUnitTest.fir @@ -0,0 +1,1076 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s +; CHECK: Done! + +circuit RouterUnitTester : + module Router : + input clk : Clock + input reset : UInt<1> + output io : {read_routing_table_request : {ready : UInt<1>, flip valid : UInt<1>, flip bits : {addr : UInt<32>}}, read_routing_table_response : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<8>}, load_routing_table_request : {ready : UInt<1>, flip valid : UInt<1>, flip bits : {addr : UInt<32>, data : UInt<32>}}, in : {ready : UInt<1>, flip valid : UInt<1>, flip bits : {header : UInt<8>, body : UInt<64>}}, outs : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : UInt<8>, body : UInt<64>}}[4]} + + io.outs[0].bits.body <= UInt<1>("h00") + io.outs[0].bits.header <= UInt<1>("h00") + io.outs[0].valid <= UInt<1>("h00") + io.outs[1].bits.body <= UInt<1>("h00") + io.outs[1].bits.header <= UInt<1>("h00") + io.outs[1].valid <= UInt<1>("h00") + io.outs[2].bits.body <= UInt<1>("h00") + io.outs[2].bits.header <= UInt<1>("h00") + io.outs[2].valid <= UInt<1>("h00") + io.outs[3].bits.body <= UInt<1>("h00") + io.outs[3].bits.header <= UInt<1>("h00") + io.outs[3].valid <= UInt<1>("h00") + io.in.ready <= UInt<1>("h00") + io.load_routing_table_request.ready <= UInt<1>("h00") + io.read_routing_table_response.bits <= UInt<1>("h00") + io.read_routing_table_response.valid <= UInt<1>("h00") + io.read_routing_table_request.ready <= UInt<1>("h00") + cmem tbl : UInt<3>[15] + when reset : + infer mport T_115 = tbl[UInt<1>("h00")], clk + T_115 <= UInt<32>("h00") + infer mport T_118 = tbl[UInt<1>("h01")], clk + T_118 <= UInt<32>("h00") + infer mport T_121 = tbl[UInt<2>("h02")], clk + T_121 <= UInt<32>("h00") + infer mport T_124 = tbl[UInt<2>("h03")], clk + T_124 <= UInt<32>("h00") + infer mport T_127 = tbl[UInt<3>("h04")], clk + T_127 <= UInt<32>("h00") + infer mport T_130 = tbl[UInt<3>("h05")], clk + T_130 <= UInt<32>("h00") + infer mport T_133 = tbl[UInt<3>("h06")], clk + T_133 <= UInt<32>("h00") + infer mport T_136 = tbl[UInt<3>("h07")], clk + T_136 <= UInt<32>("h00") + infer mport T_139 = tbl[UInt<4>("h08")], clk + T_139 <= UInt<32>("h00") + infer mport T_142 = tbl[UInt<4>("h09")], clk + T_142 <= UInt<32>("h00") + infer mport T_145 = tbl[UInt<4>("h0a")], clk + T_145 <= UInt<32>("h00") + infer mport T_148 = tbl[UInt<4>("h0b")], clk + T_148 <= UInt<32>("h00") + infer mport T_151 = tbl[UInt<4>("h0c")], clk + T_151 <= UInt<32>("h00") + infer mport T_154 = tbl[UInt<4>("h0d")], clk + T_154 <= UInt<32>("h00") + infer mport T_157 = tbl[UInt<4>("h0e")], clk + T_157 <= UInt<32>("h00") + skip + io.read_routing_table_request.ready <= UInt<1>("h01") + io.load_routing_table_request.ready <= UInt<1>("h01") + io.read_routing_table_response.valid <= UInt<1>("h00") + io.read_routing_table_response.bits <= UInt<1>("h00") + io.in.ready <= UInt<1>("h01") + io.outs[0].valid <= UInt<1>("h00") + io.outs[0].bits.body <= UInt<1>("h00") + io.outs[0].bits.header <= UInt<1>("h00") + io.outs[1].valid <= UInt<1>("h00") + io.outs[1].bits.body <= UInt<1>("h00") + io.outs[1].bits.header <= UInt<1>("h00") + io.outs[2].valid <= UInt<1>("h00") + io.outs[2].bits.body <= UInt<1>("h00") + io.outs[2].bits.header <= UInt<1>("h00") + io.outs[3].valid <= UInt<1>("h00") + io.outs[3].bits.body <= UInt<1>("h00") + io.outs[3].bits.header <= UInt<1>("h00") + node T_176 = and(io.read_routing_table_request.valid, io.read_routing_table_response.ready) + when T_176 : + io.read_routing_table_request.ready <= UInt<1>("h01") + infer mport T_178 = tbl[io.read_routing_table_request.bits.addr], clk + io.read_routing_table_response.valid <= UInt<1>("h01") + io.read_routing_table_response.bits <= T_178 + skip + node T_181 = eq(T_176, UInt<1>("h00")) + node T_182 = and(T_181, io.load_routing_table_request.valid) + when T_182 : + io.load_routing_table_request.ready <= UInt<1>("h01") + infer mport T_184 = tbl[io.load_routing_table_request.bits.addr], clk + T_184 <= io.load_routing_table_request.bits.data + node T_186 = eq(reset, UInt<1>("h00")) + when T_186 : + printf(clk, UInt<1>(1), "setting tbl(%d) to %d", io.load_routing_table_request.bits.addr, io.load_routing_table_request.bits.data) + skip + skip + node T_188 = eq(T_176, UInt<1>("h00")) + node T_190 = eq(io.load_routing_table_request.valid, UInt<1>("h00")) + node T_191 = and(T_188, T_190) + node T_192 = and(T_191, io.in.valid) + when T_192 : + node T_193 = bits(io.in.bits.header, 4, 0) + infer mport T_194 = tbl[T_193], clk + when io.outs[T_194].ready : + io.in.ready <= UInt<1>("h01") + io.outs[T_194].valid <= UInt<1>("h01") + io.outs[T_194].bits <- io.in.bits + infer mport T_215 = tbl[io.in.bits.header], clk + node T_217 = eq(reset, UInt<1>("h00")) + when T_217 : + printf(clk, UInt<1>(1), "got packet to route header %d, data %d, being routed to out(%d) ", io.in.bits.header, io.in.bits.body, T_215) + skip + skip + skip + + module RouterUnitTester : + input clk : Clock + input reset : UInt<1> + output io : {} + + inst device_under_test of Router + device_under_test.io.outs[0].ready <= UInt<1>("h00") + device_under_test.io.outs[1].ready <= UInt<1>("h00") + device_under_test.io.outs[2].ready <= UInt<1>("h00") + device_under_test.io.outs[3].ready <= UInt<1>("h00") + device_under_test.io.in.bits.body <= UInt<1>("h00") + device_under_test.io.in.bits.header <= UInt<1>("h00") + device_under_test.io.in.valid <= UInt<1>("h00") + device_under_test.io.load_routing_table_request.bits.data <= UInt<1>("h00") + device_under_test.io.load_routing_table_request.bits.addr <= UInt<1>("h00") + device_under_test.io.load_routing_table_request.valid <= UInt<1>("h00") + device_under_test.io.read_routing_table_response.ready <= UInt<1>("h00") + device_under_test.io.read_routing_table_request.bits.addr <= UInt<1>("h00") + device_under_test.io.read_routing_table_request.valid <= UInt<1>("h00") + device_under_test.clk <= clk + device_under_test.reset <= reset + reg T_19 : UInt<8>, clk with : + reset => (reset, UInt<8>("h00")) + reg T_21 : UInt<1>, clk with : + reset => (reset, UInt<1>("h00")) + reg T_23 : UInt<8>, clk with : + reset => (reset, UInt<8>("h00")) + reg T_25 : UInt<1>, clk with : + reset => (reset, UInt<1>("h00")) + node T_26 = and(T_21, T_25) + when T_26 : + node T_28 = eq(reset, UInt<1>("h00")) + when T_28 : + printf(clk, UInt<1>(1), "All input and output events completed +") + skip + node T_30 = eq(reset, UInt<1>("h00")) + when T_30 : + stop(clk, UInt<1>(1), 0) + skip + skip + reg T_32 : UInt<10>, clk with : + reset => (reset, UInt<10>("h00")) + node T_34 = tail(add(T_32, UInt<1>("h01")),1) + T_32 <= T_34 + node T_36 = gt(T_32, UInt<10>("h03e8")) + when T_36 : + node T_39 = eq(reset, UInt<1>("h00")) + when T_39 : + printf(clk, UInt<1>(1), "Exceeded maximum allowed %d ticks in OrderedDecoupledHWIOTester, If you think code is correct use: +DecoupleTester.max_tick_count = <some-higher-value> +in the OrderedDecoupledHWIOTester subclass +", UInt<10>("h03e8")) + skip + node T_41 = eq(reset, UInt<1>("h00")) + when T_41 : + stop(clk, UInt<1>(1), 0) + skip + skip + wire T_97 : UInt<1>[54] + T_97[0] <= UInt<1>("h00") + T_97[1] <= UInt<1>("h00") + T_97[2] <= UInt<1>("h00") + T_97[3] <= UInt<1>("h00") + T_97[4] <= UInt<1>("h00") + T_97[5] <= UInt<1>("h00") + T_97[6] <= UInt<1>("h00") + T_97[7] <= UInt<1>("h00") + T_97[8] <= UInt<1>("h00") + T_97[9] <= UInt<1>("h00") + T_97[10] <= UInt<1>("h00") + T_97[11] <= UInt<1>("h00") + T_97[12] <= UInt<1>("h00") + T_97[13] <= UInt<1>("h01") + T_97[14] <= UInt<1>("h01") + T_97[15] <= UInt<1>("h01") + T_97[16] <= UInt<1>("h01") + T_97[17] <= UInt<1>("h00") + T_97[18] <= UInt<1>("h00") + T_97[19] <= UInt<1>("h00") + T_97[20] <= UInt<1>("h00") + T_97[21] <= UInt<1>("h00") + T_97[22] <= UInt<1>("h00") + T_97[23] <= UInt<1>("h00") + T_97[24] <= UInt<1>("h00") + T_97[25] <= UInt<1>("h00") + T_97[26] <= UInt<1>("h00") + T_97[27] <= UInt<1>("h00") + T_97[28] <= UInt<1>("h00") + T_97[29] <= UInt<1>("h00") + T_97[30] <= UInt<1>("h00") + T_97[31] <= UInt<1>("h00") + T_97[32] <= UInt<1>("h01") + T_97[33] <= UInt<1>("h01") + T_97[34] <= UInt<1>("h01") + T_97[35] <= UInt<1>("h01") + T_97[36] <= UInt<1>("h01") + T_97[37] <= UInt<1>("h01") + T_97[38] <= UInt<1>("h01") + T_97[39] <= UInt<1>("h01") + T_97[40] <= UInt<1>("h01") + T_97[41] <= UInt<1>("h01") + T_97[42] <= UInt<1>("h01") + T_97[43] <= UInt<1>("h01") + T_97[44] <= UInt<1>("h01") + T_97[45] <= UInt<1>("h01") + T_97[46] <= UInt<1>("h01") + T_97[47] <= UInt<1>("h01") + T_97[48] <= UInt<1>("h01") + T_97[49] <= UInt<1>("h01") + T_97[50] <= UInt<1>("h01") + T_97[51] <= UInt<1>("h01") + T_97[52] <= UInt<1>("h01") + T_97[53] <= UInt<1>("h00") + reg T_154 : UInt<5>, clk with : + reset => (reset, UInt<5>("h00")) + wire T_182 : UInt<4>[26] + T_182[0] <= UInt<1>("h00") + T_182[1] <= UInt<1>("h01") + T_182[2] <= UInt<2>("h02") + T_182[3] <= UInt<2>("h03") + T_182[4] <= UInt<1>("h00") + T_182[5] <= UInt<1>("h01") + T_182[6] <= UInt<2>("h02") + T_182[7] <= UInt<2>("h03") + T_182[8] <= UInt<3>("h04") + T_182[9] <= UInt<3>("h05") + T_182[10] <= UInt<3>("h06") + T_182[11] <= UInt<3>("h07") + T_182[12] <= UInt<4>("h08") + T_182[13] <= UInt<4>("h09") + T_182[14] <= UInt<4>("h0a") + T_182[15] <= UInt<4>("h0b") + T_182[16] <= UInt<4>("h0c") + T_182[17] <= UInt<4>("h0d") + T_182[18] <= UInt<4>("h0e") + T_182[19] <= UInt<1>("h00") + T_182[20] <= UInt<1>("h01") + T_182[21] <= UInt<2>("h02") + T_182[22] <= UInt<2>("h03") + T_182[23] <= UInt<3>("h04") + T_182[24] <= UInt<3>("h05") + T_182[25] <= UInt<1>("h00") + wire T_237 : UInt<31>[26] + T_237[0] <= UInt<1>("h00") + T_237[1] <= UInt<2>("h03") + T_237[2] <= UInt<3>("h06") + T_237[3] <= UInt<4>("h09") + T_237[4] <= UInt<31>("h07dcd07ac") + T_237[5] <= UInt<31>("h070890d84") + T_237[6] <= UInt<26>("h02f45883") + T_237[7] <= UInt<31>("h0787ada79") + T_237[8] <= UInt<29>("h016866878") + T_237[9] <= UInt<30>("h02331b107") + T_237[10] <= UInt<30>("h0280e4938") + T_237[11] <= UInt<29>("h0107fb3ac") + T_237[12] <= UInt<30>("h02f19d47b") + T_237[13] <= UInt<29>("h012c3d7cc") + T_237[14] <= UInt<31>("h05a432a9c") + T_237[15] <= UInt<26>("h02f9778f") + T_237[16] <= UInt<22>("h02d705a") + T_237[17] <= UInt<31>("h045fb9184") + T_237[18] <= UInt<25>("h012e47af") + T_237[19] <= UInt<31>("h07b744e21") + T_237[20] <= UInt<31>("h0480ebc3d") + T_237[21] <= UInt<28>("h0d5ff365") + T_237[22] <= UInt<30>("h0205e7973") + T_237[23] <= UInt<31>("h05004cbd2") + T_237[24] <= UInt<30>("h024988736") + T_237[25] <= UInt<1>("h00") + device_under_test.io.in.bits.header <= T_182[T_154] + device_under_test.io.in.bits.body <= T_237[T_154] + device_under_test.io.in.valid <= T_97[T_19] + node T_268 = and(device_under_test.io.in.valid, device_under_test.io.in.ready) + when T_268 : + node T_270 = eq(T_154, UInt<5>("h018")) + node T_272 = and(UInt<1>("h01"), T_270) + node T_275 = tail(add(T_154, UInt<1>("h01")),1) + node T_276 = mux(T_272, UInt<1>("h00"), T_275) + T_154 <= T_276 + node T_278 = eq(T_21, UInt<1>("h00")) + when T_278 : + node T_280 = eq(T_19, UInt<6>("h034")) + when T_280 : + T_21 <= UInt<1>("h01") + skip + node T_283 = tail(add(T_19, UInt<1>("h01")),1) + T_19 <= T_283 + skip + skip + wire T_339 : UInt<1>[54] + T_339[0] <= UInt<1>("h00") + T_339[1] <= UInt<1>("h01") + T_339[2] <= UInt<1>("h00") + T_339[3] <= UInt<1>("h01") + T_339[4] <= UInt<1>("h00") + T_339[5] <= UInt<1>("h01") + T_339[6] <= UInt<1>("h00") + T_339[7] <= UInt<1>("h01") + T_339[8] <= UInt<1>("h00") + T_339[9] <= UInt<1>("h00") + T_339[10] <= UInt<1>("h00") + T_339[11] <= UInt<1>("h00") + T_339[12] <= UInt<1>("h00") + T_339[13] <= UInt<1>("h00") + T_339[14] <= UInt<1>("h00") + T_339[15] <= UInt<1>("h00") + T_339[16] <= UInt<1>("h00") + T_339[17] <= UInt<1>("h01") + T_339[18] <= UInt<1>("h01") + T_339[19] <= UInt<1>("h01") + T_339[20] <= UInt<1>("h01") + T_339[21] <= UInt<1>("h01") + T_339[22] <= UInt<1>("h01") + T_339[23] <= UInt<1>("h01") + T_339[24] <= UInt<1>("h01") + T_339[25] <= UInt<1>("h01") + T_339[26] <= UInt<1>("h01") + T_339[27] <= UInt<1>("h01") + T_339[28] <= UInt<1>("h01") + T_339[29] <= UInt<1>("h01") + T_339[30] <= UInt<1>("h01") + T_339[31] <= UInt<1>("h01") + T_339[32] <= UInt<1>("h00") + T_339[33] <= UInt<1>("h00") + T_339[34] <= UInt<1>("h00") + T_339[35] <= UInt<1>("h00") + T_339[36] <= UInt<1>("h00") + T_339[37] <= UInt<1>("h00") + T_339[38] <= UInt<1>("h00") + T_339[39] <= UInt<1>("h00") + T_339[40] <= UInt<1>("h00") + T_339[41] <= UInt<1>("h00") + T_339[42] <= UInt<1>("h00") + T_339[43] <= UInt<1>("h00") + T_339[44] <= UInt<1>("h00") + T_339[45] <= UInt<1>("h00") + T_339[46] <= UInt<1>("h00") + T_339[47] <= UInt<1>("h00") + T_339[48] <= UInt<1>("h00") + T_339[49] <= UInt<1>("h00") + T_339[50] <= UInt<1>("h00") + T_339[51] <= UInt<1>("h00") + T_339[52] <= UInt<1>("h00") + T_339[53] <= UInt<1>("h00") + reg T_396 : UInt<5>, clk with : + reset => (reset, UInt<5>("h00")) + wire T_418 : UInt<2>[20] + T_418[0] <= UInt<1>("h01") + T_418[1] <= UInt<2>("h02") + T_418[2] <= UInt<2>("h03") + T_418[3] <= UInt<1>("h00") + T_418[4] <= UInt<2>("h02") + T_418[5] <= UInt<2>("h03") + T_418[6] <= UInt<1>("h00") + T_418[7] <= UInt<2>("h02") + T_418[8] <= UInt<2>("h02") + T_418[9] <= UInt<1>("h01") + T_418[10] <= UInt<2>("h02") + T_418[11] <= UInt<1>("h00") + T_418[12] <= UInt<2>("h02") + T_418[13] <= UInt<2>("h03") + T_418[14] <= UInt<1>("h01") + T_418[15] <= UInt<1>("h01") + T_418[16] <= UInt<1>("h01") + T_418[17] <= UInt<2>("h02") + T_418[18] <= UInt<2>("h03") + T_418[19] <= UInt<1>("h00") + wire T_461 : UInt<4>[20] + T_461[0] <= UInt<1>("h00") + T_461[1] <= UInt<1>("h01") + T_461[2] <= UInt<2>("h02") + T_461[3] <= UInt<2>("h03") + T_461[4] <= UInt<1>("h00") + T_461[5] <= UInt<1>("h01") + T_461[6] <= UInt<2>("h02") + T_461[7] <= UInt<2>("h03") + T_461[8] <= UInt<3>("h04") + T_461[9] <= UInt<3>("h05") + T_461[10] <= UInt<3>("h06") + T_461[11] <= UInt<3>("h07") + T_461[12] <= UInt<4>("h08") + T_461[13] <= UInt<4>("h09") + T_461[14] <= UInt<4>("h0a") + T_461[15] <= UInt<4>("h0b") + T_461[16] <= UInt<4>("h0c") + T_461[17] <= UInt<4>("h0d") + T_461[18] <= UInt<4>("h0e") + T_461[19] <= UInt<1>("h00") + device_under_test.io.load_routing_table_request.bits.data <= T_418[T_396] + device_under_test.io.load_routing_table_request.bits.addr <= T_461[T_396] + device_under_test.io.load_routing_table_request.valid <= T_339[T_19] + node T_486 = and(device_under_test.io.load_routing_table_request.valid, device_under_test.io.load_routing_table_request.ready) + when T_486 : + node T_488 = eq(T_396, UInt<5>("h012")) + node T_490 = and(UInt<1>("h01"), T_488) + node T_493 = tail(add(T_396, UInt<1>("h01")),1) + node T_494 = mux(T_490, UInt<1>("h00"), T_493) + T_396 <= T_494 + node T_496 = eq(T_21, UInt<1>("h00")) + when T_496 : + node T_498 = eq(T_19, UInt<6>("h034")) + when T_498 : + T_21 <= UInt<1>("h01") + skip + node T_501 = tail(add(T_19, UInt<1>("h01")),1) + T_19 <= T_501 + skip + skip + wire T_557 : UInt<1>[54] + T_557[0] <= UInt<1>("h01") + T_557[1] <= UInt<1>("h00") + T_557[2] <= UInt<1>("h01") + T_557[3] <= UInt<1>("h00") + T_557[4] <= UInt<1>("h01") + T_557[5] <= UInt<1>("h00") + T_557[6] <= UInt<1>("h01") + T_557[7] <= UInt<1>("h00") + T_557[8] <= UInt<1>("h01") + T_557[9] <= UInt<1>("h01") + T_557[10] <= UInt<1>("h01") + T_557[11] <= UInt<1>("h01") + T_557[12] <= UInt<1>("h01") + T_557[13] <= UInt<1>("h00") + T_557[14] <= UInt<1>("h00") + T_557[15] <= UInt<1>("h00") + T_557[16] <= UInt<1>("h00") + T_557[17] <= UInt<1>("h00") + T_557[18] <= UInt<1>("h00") + T_557[19] <= UInt<1>("h00") + T_557[20] <= UInt<1>("h00") + T_557[21] <= UInt<1>("h00") + T_557[22] <= UInt<1>("h00") + T_557[23] <= UInt<1>("h00") + T_557[24] <= UInt<1>("h00") + T_557[25] <= UInt<1>("h00") + T_557[26] <= UInt<1>("h00") + T_557[27] <= UInt<1>("h00") + T_557[28] <= UInt<1>("h00") + T_557[29] <= UInt<1>("h00") + T_557[30] <= UInt<1>("h00") + T_557[31] <= UInt<1>("h00") + T_557[32] <= UInt<1>("h00") + T_557[33] <= UInt<1>("h00") + T_557[34] <= UInt<1>("h00") + T_557[35] <= UInt<1>("h00") + T_557[36] <= UInt<1>("h00") + T_557[37] <= UInt<1>("h00") + T_557[38] <= UInt<1>("h00") + T_557[39] <= UInt<1>("h00") + T_557[40] <= UInt<1>("h00") + T_557[41] <= UInt<1>("h00") + T_557[42] <= UInt<1>("h00") + T_557[43] <= UInt<1>("h00") + T_557[44] <= UInt<1>("h00") + T_557[45] <= UInt<1>("h00") + T_557[46] <= UInt<1>("h00") + T_557[47] <= UInt<1>("h00") + T_557[48] <= UInt<1>("h00") + T_557[49] <= UInt<1>("h00") + T_557[50] <= UInt<1>("h00") + T_557[51] <= UInt<1>("h00") + T_557[52] <= UInt<1>("h00") + T_557[53] <= UInt<1>("h00") + reg T_614 : UInt<4>, clk with : + reset => (reset, UInt<4>("h00")) + wire T_626 : UInt<2>[10] + T_626[0] <= UInt<1>("h00") + T_626[1] <= UInt<1>("h00") + T_626[2] <= UInt<1>("h01") + T_626[3] <= UInt<2>("h02") + T_626[4] <= UInt<2>("h03") + T_626[5] <= UInt<2>("h03") + T_626[6] <= UInt<2>("h02") + T_626[7] <= UInt<1>("h01") + T_626[8] <= UInt<1>("h00") + T_626[9] <= UInt<1>("h00") + device_under_test.io.read_routing_table_request.bits.addr <= T_626[T_614] + device_under_test.io.read_routing_table_request.valid <= T_557[T_19] + node T_640 = and(device_under_test.io.read_routing_table_request.valid, device_under_test.io.read_routing_table_request.ready) + when T_640 : + node T_642 = eq(T_614, UInt<4>("h08")) + node T_644 = and(UInt<1>("h01"), T_642) + node T_647 = tail(add(T_614, UInt<1>("h01")),1) + node T_648 = mux(T_644, UInt<1>("h00"), T_647) + T_614 <= T_648 + node T_650 = eq(T_21, UInt<1>("h00")) + when T_650 : + node T_652 = eq(T_19, UInt<6>("h034")) + when T_652 : + T_21 <= UInt<1>("h01") + skip + node T_655 = tail(add(T_19, UInt<1>("h01")),1) + T_19 <= T_655 + skip + skip + wire T_711 : UInt<1>[54] + T_711[0] <= UInt<1>("h00") + T_711[1] <= UInt<1>("h00") + T_711[2] <= UInt<1>("h00") + T_711[3] <= UInt<1>("h00") + T_711[4] <= UInt<1>("h00") + T_711[5] <= UInt<1>("h00") + T_711[6] <= UInt<1>("h00") + T_711[7] <= UInt<1>("h00") + T_711[8] <= UInt<1>("h00") + T_711[9] <= UInt<1>("h00") + T_711[10] <= UInt<1>("h00") + T_711[11] <= UInt<1>("h00") + T_711[12] <= UInt<1>("h01") + T_711[13] <= UInt<1>("h00") + T_711[14] <= UInt<1>("h00") + T_711[15] <= UInt<1>("h01") + T_711[16] <= UInt<1>("h00") + T_711[17] <= UInt<1>("h00") + T_711[18] <= UInt<1>("h00") + T_711[19] <= UInt<1>("h00") + T_711[20] <= UInt<1>("h01") + T_711[21] <= UInt<1>("h00") + T_711[22] <= UInt<1>("h00") + T_711[23] <= UInt<1>("h00") + T_711[24] <= UInt<1>("h00") + T_711[25] <= UInt<1>("h00") + T_711[26] <= UInt<1>("h00") + T_711[27] <= UInt<1>("h00") + T_711[28] <= UInt<1>("h00") + T_711[29] <= UInt<1>("h00") + T_711[30] <= UInt<1>("h01") + T_711[31] <= UInt<1>("h00") + T_711[32] <= UInt<1>("h00") + T_711[33] <= UInt<1>("h00") + T_711[34] <= UInt<1>("h00") + T_711[35] <= UInt<1>("h00") + T_711[36] <= UInt<1>("h00") + T_711[37] <= UInt<1>("h00") + T_711[38] <= UInt<1>("h00") + T_711[39] <= UInt<1>("h00") + T_711[40] <= UInt<1>("h00") + T_711[41] <= UInt<1>("h00") + T_711[42] <= UInt<1>("h00") + T_711[43] <= UInt<1>("h00") + T_711[44] <= UInt<1>("h00") + T_711[45] <= UInt<1>("h00") + T_711[46] <= UInt<1>("h00") + T_711[47] <= UInt<1>("h00") + T_711[48] <= UInt<1>("h00") + T_711[49] <= UInt<1>("h00") + T_711[50] <= UInt<1>("h00") + T_711[51] <= UInt<1>("h00") + T_711[52] <= UInt<1>("h00") + T_711[53] <= UInt<1>("h00") + reg T_768 : UInt<6>, clk with : + reset => (reset, UInt<6>("h00")) + wire T_775 : UInt<29>[5] + T_775[0] <= UInt<4>("h09") + T_775[1] <= UInt<26>("h02f45883") + T_775[2] <= UInt<29>("h0107fb3ac") + T_775[3] <= UInt<28>("h0d5ff365") + T_775[4] <= UInt<1>("h00") + device_under_test.io.outs[0].ready <= T_711[T_23] + node T_783 = and(device_under_test.io.outs[0].ready, device_under_test.io.outs[0].valid) + when T_783 : + node T_786 = eq(reset, UInt<1>("h00")) + when T_786 : + printf(clk, UInt<1>(1), "output test event %d testing outs(0).bits.body = %d, should be %d +", T_23, device_under_test.io.outs[0].bits.body, T_775[T_768]) + skip + node T_788 = neq(device_under_test.io.outs[0].bits.body, T_775[T_768]) + when T_788 : + node T_791 = eq(reset, UInt<1>("h00")) + when T_791 : + printf(clk, UInt<1>(1), "Error: event %d outs(0).bits.body was %d should be %d +", T_23, device_under_test.io.outs[0].bits.body, T_775[T_768]) + skip + node T_794 = eq(reset, UInt<1>("h00")) + when T_794 : + node T_796 = eq(UInt<1>("h00"), UInt<1>("h00")) + when T_796 : + node T_798 = eq(reset, UInt<1>("h00")) + when T_798 : + printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno)") + skip + stop(clk, UInt<1>(1), 1) + skip + skip + node T_800 = eq(reset, UInt<1>("h00")) + when T_800 : + stop(clk, UInt<1>(1), 0) + skip + skip + node T_802 = eq(T_768, UInt<6>("h021")) + node T_804 = and(UInt<1>("h01"), T_802) + node T_807 = tail(add(T_768, UInt<1>("h01")),1) + node T_808 = mux(T_804, UInt<1>("h00"), T_807) + T_768 <= T_808 + node T_810 = eq(T_25, UInt<1>("h00")) + when T_810 : + node T_812 = eq(T_23, UInt<6>("h021")) + when T_812 : + T_25 <= UInt<1>("h01") + skip + node T_815 = tail(add(T_23, UInt<1>("h01")),1) + T_23 <= T_815 + skip + skip + wire T_871 : UInt<1>[54] + T_871[0] <= UInt<1>("h00") + T_871[1] <= UInt<1>("h00") + T_871[2] <= UInt<1>("h00") + T_871[3] <= UInt<1>("h00") + T_871[4] <= UInt<1>("h00") + T_871[5] <= UInt<1>("h00") + T_871[6] <= UInt<1>("h00") + T_871[7] <= UInt<1>("h00") + T_871[8] <= UInt<1>("h00") + T_871[9] <= UInt<1>("h00") + T_871[10] <= UInt<1>("h00") + T_871[11] <= UInt<1>("h01") + T_871[12] <= UInt<1>("h00") + T_871[13] <= UInt<1>("h00") + T_871[14] <= UInt<1>("h01") + T_871[15] <= UInt<1>("h00") + T_871[16] <= UInt<1>("h00") + T_871[17] <= UInt<1>("h00") + T_871[18] <= UInt<1>("h00") + T_871[19] <= UInt<1>("h00") + T_871[20] <= UInt<1>("h00") + T_871[21] <= UInt<1>("h00") + T_871[22] <= UInt<1>("h01") + T_871[23] <= UInt<1>("h00") + T_871[24] <= UInt<1>("h00") + T_871[25] <= UInt<1>("h00") + T_871[26] <= UInt<1>("h00") + T_871[27] <= UInt<1>("h01") + T_871[28] <= UInt<1>("h00") + T_871[29] <= UInt<1>("h01") + T_871[30] <= UInt<1>("h00") + T_871[31] <= UInt<1>("h00") + T_871[32] <= UInt<1>("h00") + T_871[33] <= UInt<1>("h00") + T_871[34] <= UInt<1>("h00") + T_871[35] <= UInt<1>("h00") + T_871[36] <= UInt<1>("h00") + T_871[37] <= UInt<1>("h00") + T_871[38] <= UInt<1>("h00") + T_871[39] <= UInt<1>("h00") + T_871[40] <= UInt<1>("h00") + T_871[41] <= UInt<1>("h00") + T_871[42] <= UInt<1>("h00") + T_871[43] <= UInt<1>("h00") + T_871[44] <= UInt<1>("h00") + T_871[45] <= UInt<1>("h00") + T_871[46] <= UInt<1>("h00") + T_871[47] <= UInt<1>("h00") + T_871[48] <= UInt<1>("h00") + T_871[49] <= UInt<1>("h00") + T_871[50] <= UInt<1>("h00") + T_871[51] <= UInt<1>("h00") + T_871[52] <= UInt<1>("h00") + T_871[53] <= UInt<1>("h00") + reg T_928 : UInt<6>, clk with : + reset => (reset, UInt<6>("h00")) + wire T_936 : UInt<31>[6] + T_936[0] <= UInt<3>("h06") + T_936[1] <= UInt<31>("h070890d84") + T_936[2] <= UInt<29>("h012c3d7cc") + T_936[3] <= UInt<25>("h012e47af") + T_936[4] <= UInt<31>("h0480ebc3d") + T_936[5] <= UInt<1>("h00") + device_under_test.io.outs[3].ready <= T_871[T_23] + node T_945 = and(device_under_test.io.outs[3].ready, device_under_test.io.outs[3].valid) + when T_945 : + node T_948 = eq(reset, UInt<1>("h00")) + when T_948 : + printf(clk, UInt<1>(1), "output test event %d testing outs(3).bits.body = %d, should be %d +", T_23, device_under_test.io.outs[3].bits.body, T_936[T_928]) + skip + node T_950 = neq(device_under_test.io.outs[3].bits.body, T_936[T_928]) + when T_950 : + node T_953 = eq(reset, UInt<1>("h00")) + when T_953 : + printf(clk, UInt<1>(1), "Error: event %d outs(3).bits.body was %d should be %d +", T_23, device_under_test.io.outs[3].bits.body, T_936[T_928]) + skip + node T_956 = eq(reset, UInt<1>("h00")) + when T_956 : + node T_958 = eq(UInt<1>("h00"), UInt<1>("h00")) + when T_958 : + node T_960 = eq(reset, UInt<1>("h00")) + when T_960 : + printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno)") + skip + stop(clk, UInt<1>(1), 1) + skip + skip + node T_962 = eq(reset, UInt<1>("h00")) + when T_962 : + stop(clk, UInt<1>(1), 0) + skip + skip + node T_964 = eq(T_928, UInt<6>("h021")) + node T_966 = and(UInt<1>("h01"), T_964) + node T_969 = tail(add(T_928, UInt<1>("h01")),1) + node T_970 = mux(T_966, UInt<1>("h00"), T_969) + T_928 <= T_970 + node T_972 = eq(T_25, UInt<1>("h00")) + when T_972 : + node T_974 = eq(T_23, UInt<6>("h021")) + when T_974 : + T_25 <= UInt<1>("h01") + skip + node T_977 = tail(add(T_23, UInt<1>("h01")),1) + T_23 <= T_977 + skip + skip + wire T_1033 : UInt<1>[54] + T_1033[0] <= UInt<1>("h00") + T_1033[1] <= UInt<1>("h00") + T_1033[2] <= UInt<1>("h00") + T_1033[3] <= UInt<1>("h00") + T_1033[4] <= UInt<1>("h00") + T_1033[5] <= UInt<1>("h00") + T_1033[6] <= UInt<1>("h00") + T_1033[7] <= UInt<1>("h00") + T_1033[8] <= UInt<1>("h00") + T_1033[9] <= UInt<1>("h01") + T_1033[10] <= UInt<1>("h00") + T_1033[11] <= UInt<1>("h00") + T_1033[12] <= UInt<1>("h00") + T_1033[13] <= UInt<1>("h00") + T_1033[14] <= UInt<1>("h00") + T_1033[15] <= UInt<1>("h00") + T_1033[16] <= UInt<1>("h00") + T_1033[17] <= UInt<1>("h00") + T_1033[18] <= UInt<1>("h01") + T_1033[19] <= UInt<1>("h00") + T_1033[20] <= UInt<1>("h00") + T_1033[21] <= UInt<1>("h00") + T_1033[22] <= UInt<1>("h00") + T_1033[23] <= UInt<1>("h01") + T_1033[24] <= UInt<1>("h01") + T_1033[25] <= UInt<1>("h01") + T_1033[26] <= UInt<1>("h00") + T_1033[27] <= UInt<1>("h00") + T_1033[28] <= UInt<1>("h00") + T_1033[29] <= UInt<1>("h00") + T_1033[30] <= UInt<1>("h00") + T_1033[31] <= UInt<1>("h00") + T_1033[32] <= UInt<1>("h00") + T_1033[33] <= UInt<1>("h01") + T_1033[34] <= UInt<1>("h00") + T_1033[35] <= UInt<1>("h00") + T_1033[36] <= UInt<1>("h00") + T_1033[37] <= UInt<1>("h00") + T_1033[38] <= UInt<1>("h00") + T_1033[39] <= UInt<1>("h00") + T_1033[40] <= UInt<1>("h00") + T_1033[41] <= UInt<1>("h00") + T_1033[42] <= UInt<1>("h00") + T_1033[43] <= UInt<1>("h00") + T_1033[44] <= UInt<1>("h00") + T_1033[45] <= UInt<1>("h00") + T_1033[46] <= UInt<1>("h00") + T_1033[47] <= UInt<1>("h00") + T_1033[48] <= UInt<1>("h00") + T_1033[49] <= UInt<1>("h00") + T_1033[50] <= UInt<1>("h00") + T_1033[51] <= UInt<1>("h00") + T_1033[52] <= UInt<1>("h00") + T_1033[53] <= UInt<1>("h00") + reg T_1090 : UInt<6>, clk with : + reset => (reset, UInt<6>("h00")) + wire T_1099 : UInt<31>[7] + T_1099[0] <= UInt<1>("h00") + T_1099[1] <= UInt<30>("h02331b107") + T_1099[2] <= UInt<31>("h05a432a9c") + T_1099[3] <= UInt<26>("h02f9778f") + T_1099[4] <= UInt<22>("h02d705a") + T_1099[5] <= UInt<30>("h024988736") + T_1099[6] <= UInt<1>("h00") + device_under_test.io.outs[1].ready <= T_1033[T_23] + node T_1109 = and(device_under_test.io.outs[1].ready, device_under_test.io.outs[1].valid) + when T_1109 : + node T_1112 = eq(reset, UInt<1>("h00")) + when T_1112 : + printf(clk, UInt<1>(1), "output test event %d testing outs(1).bits.body = %d, should be %d +", T_23, device_under_test.io.outs[1].bits.body, T_1099[T_1090]) + skip + node T_1114 = neq(device_under_test.io.outs[1].bits.body, T_1099[T_1090]) + when T_1114 : + node T_1117 = eq(reset, UInt<1>("h00")) + when T_1117 : + printf(clk, UInt<1>(1), "Error: event %d outs(1).bits.body was %d should be %d +", T_23, device_under_test.io.outs[1].bits.body, T_1099[T_1090]) + skip + node T_1120 = eq(reset, UInt<1>("h00")) + when T_1120 : + node T_1122 = eq(UInt<1>("h00"), UInt<1>("h00")) + when T_1122 : + node T_1124 = eq(reset, UInt<1>("h00")) + when T_1124 : + printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno)") + skip + stop(clk, UInt<1>(1), 1) + skip + skip + node T_1126 = eq(reset, UInt<1>("h00")) + when T_1126 : + stop(clk, UInt<1>(1), 0) + skip + skip + node T_1128 = eq(T_1090, UInt<6>("h021")) + node T_1130 = and(UInt<1>("h01"), T_1128) + node T_1133 = tail(add(T_1090, UInt<1>("h01")),1) + node T_1134 = mux(T_1130, UInt<1>("h00"), T_1133) + T_1090 <= T_1134 + node T_1136 = eq(T_25, UInt<1>("h00")) + when T_1136 : + node T_1138 = eq(T_23, UInt<6>("h021")) + when T_1138 : + T_25 <= UInt<1>("h01") + skip + node T_1141 = tail(add(T_23, UInt<1>("h01")),1) + T_23 <= T_1141 + skip + skip + wire T_1197 : UInt<1>[54] + T_1197[0] <= UInt<1>("h00") + T_1197[1] <= UInt<1>("h00") + T_1197[2] <= UInt<1>("h00") + T_1197[3] <= UInt<1>("h00") + T_1197[4] <= UInt<1>("h00") + T_1197[5] <= UInt<1>("h00") + T_1197[6] <= UInt<1>("h00") + T_1197[7] <= UInt<1>("h00") + T_1197[8] <= UInt<1>("h00") + T_1197[9] <= UInt<1>("h00") + T_1197[10] <= UInt<1>("h01") + T_1197[11] <= UInt<1>("h00") + T_1197[12] <= UInt<1>("h00") + T_1197[13] <= UInt<1>("h01") + T_1197[14] <= UInt<1>("h00") + T_1197[15] <= UInt<1>("h00") + T_1197[16] <= UInt<1>("h01") + T_1197[17] <= UInt<1>("h01") + T_1197[18] <= UInt<1>("h00") + T_1197[19] <= UInt<1>("h01") + T_1197[20] <= UInt<1>("h00") + T_1197[21] <= UInt<1>("h01") + T_1197[22] <= UInt<1>("h00") + T_1197[23] <= UInt<1>("h00") + T_1197[24] <= UInt<1>("h00") + T_1197[25] <= UInt<1>("h00") + T_1197[26] <= UInt<1>("h01") + T_1197[27] <= UInt<1>("h00") + T_1197[28] <= UInt<1>("h01") + T_1197[29] <= UInt<1>("h00") + T_1197[30] <= UInt<1>("h00") + T_1197[31] <= UInt<1>("h01") + T_1197[32] <= UInt<1>("h01") + T_1197[33] <= UInt<1>("h00") + T_1197[34] <= UInt<1>("h00") + T_1197[35] <= UInt<1>("h00") + T_1197[36] <= UInt<1>("h00") + T_1197[37] <= UInt<1>("h00") + T_1197[38] <= UInt<1>("h00") + T_1197[39] <= UInt<1>("h00") + T_1197[40] <= UInt<1>("h00") + T_1197[41] <= UInt<1>("h00") + T_1197[42] <= UInt<1>("h00") + T_1197[43] <= UInt<1>("h00") + T_1197[44] <= UInt<1>("h00") + T_1197[45] <= UInt<1>("h00") + T_1197[46] <= UInt<1>("h00") + T_1197[47] <= UInt<1>("h00") + T_1197[48] <= UInt<1>("h00") + T_1197[49] <= UInt<1>("h00") + T_1197[50] <= UInt<1>("h00") + T_1197[51] <= UInt<1>("h00") + T_1197[52] <= UInt<1>("h00") + T_1197[53] <= UInt<1>("h00") + reg T_1254 : UInt<6>, clk with : + reset => (reset, UInt<6>("h00")) + wire T_1267 : UInt<31>[11] + T_1267[0] <= UInt<2>("h03") + T_1267[1] <= UInt<31>("h07dcd07ac") + T_1267[2] <= UInt<31>("h0787ada79") + T_1267[3] <= UInt<29>("h016866878") + T_1267[4] <= UInt<30>("h0280e4938") + T_1267[5] <= UInt<30>("h02f19d47b") + T_1267[6] <= UInt<31>("h045fb9184") + T_1267[7] <= UInt<31>("h07b744e21") + T_1267[8] <= UInt<30>("h0205e7973") + T_1267[9] <= UInt<31>("h05004cbd2") + T_1267[10] <= UInt<1>("h00") + device_under_test.io.outs[2].ready <= T_1197[T_23] + node T_1281 = and(device_under_test.io.outs[2].ready, device_under_test.io.outs[2].valid) + when T_1281 : + node T_1284 = eq(reset, UInt<1>("h00")) + when T_1284 : + printf(clk, UInt<1>(1), "output test event %d testing outs(2).bits.body = %d, should be %d +", T_23, device_under_test.io.outs[2].bits.body, T_1267[T_1254]) + skip + node T_1286 = neq(device_under_test.io.outs[2].bits.body, T_1267[T_1254]) + when T_1286 : + node T_1289 = eq(reset, UInt<1>("h00")) + when T_1289 : + printf(clk, UInt<1>(1), "Error: event %d outs(2).bits.body was %d should be %d +", T_23, device_under_test.io.outs[2].bits.body, T_1267[T_1254]) + skip + node T_1292 = eq(reset, UInt<1>("h00")) + when T_1292 : + node T_1294 = eq(UInt<1>("h00"), UInt<1>("h00")) + when T_1294 : + node T_1296 = eq(reset, UInt<1>("h00")) + when T_1296 : + printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno)") + skip + stop(clk, UInt<1>(1), 1) + skip + skip + node T_1298 = eq(reset, UInt<1>("h00")) + when T_1298 : + stop(clk, UInt<1>(1), 0) + skip + skip + node T_1300 = eq(T_1254, UInt<6>("h021")) + node T_1302 = and(UInt<1>("h01"), T_1300) + node T_1305 = tail(add(T_1254, UInt<1>("h01")),1) + node T_1306 = mux(T_1302, UInt<1>("h00"), T_1305) + T_1254 <= T_1306 + node T_1308 = eq(T_25, UInt<1>("h00")) + when T_1308 : + node T_1310 = eq(T_23, UInt<6>("h021")) + when T_1310 : + T_25 <= UInt<1>("h01") + skip + node T_1313 = tail(add(T_23, UInt<1>("h01")),1) + T_23 <= T_1313 + skip + skip + wire T_1369 : UInt<1>[54] + T_1369[0] <= UInt<1>("h01") + T_1369[1] <= UInt<1>("h01") + T_1369[2] <= UInt<1>("h01") + T_1369[3] <= UInt<1>("h01") + T_1369[4] <= UInt<1>("h01") + T_1369[5] <= UInt<1>("h01") + T_1369[6] <= UInt<1>("h01") + T_1369[7] <= UInt<1>("h01") + T_1369[8] <= UInt<1>("h01") + T_1369[9] <= UInt<1>("h00") + T_1369[10] <= UInt<1>("h00") + T_1369[11] <= UInt<1>("h00") + T_1369[12] <= UInt<1>("h00") + T_1369[13] <= UInt<1>("h00") + T_1369[14] <= UInt<1>("h00") + T_1369[15] <= UInt<1>("h00") + T_1369[16] <= UInt<1>("h00") + T_1369[17] <= UInt<1>("h00") + T_1369[18] <= UInt<1>("h00") + T_1369[19] <= UInt<1>("h00") + T_1369[20] <= UInt<1>("h00") + T_1369[21] <= UInt<1>("h00") + T_1369[22] <= UInt<1>("h00") + T_1369[23] <= UInt<1>("h00") + T_1369[24] <= UInt<1>("h00") + T_1369[25] <= UInt<1>("h00") + T_1369[26] <= UInt<1>("h00") + T_1369[27] <= UInt<1>("h00") + T_1369[28] <= UInt<1>("h00") + T_1369[29] <= UInt<1>("h00") + T_1369[30] <= UInt<1>("h00") + T_1369[31] <= UInt<1>("h00") + T_1369[32] <= UInt<1>("h00") + T_1369[33] <= UInt<1>("h00") + T_1369[34] <= UInt<1>("h00") + T_1369[35] <= UInt<1>("h00") + T_1369[36] <= UInt<1>("h00") + T_1369[37] <= UInt<1>("h00") + T_1369[38] <= UInt<1>("h00") + T_1369[39] <= UInt<1>("h00") + T_1369[40] <= UInt<1>("h00") + T_1369[41] <= UInt<1>("h00") + T_1369[42] <= UInt<1>("h00") + T_1369[43] <= UInt<1>("h00") + T_1369[44] <= UInt<1>("h00") + T_1369[45] <= UInt<1>("h00") + T_1369[46] <= UInt<1>("h00") + T_1369[47] <= UInt<1>("h00") + T_1369[48] <= UInt<1>("h00") + T_1369[49] <= UInt<1>("h00") + T_1369[50] <= UInt<1>("h00") + T_1369[51] <= UInt<1>("h00") + T_1369[52] <= UInt<1>("h00") + T_1369[53] <= UInt<1>("h00") + reg T_1426 : UInt<6>, clk with : + reset => (reset, UInt<6>("h00")) + wire T_1438 : UInt<2>[10] + T_1438[0] <= UInt<1>("h00") + T_1438[1] <= UInt<1>("h01") + T_1438[2] <= UInt<2>("h02") + T_1438[3] <= UInt<2>("h03") + T_1438[4] <= UInt<1>("h00") + T_1438[5] <= UInt<1>("h00") + T_1438[6] <= UInt<2>("h03") + T_1438[7] <= UInt<2>("h02") + T_1438[8] <= UInt<1>("h01") + T_1438[9] <= UInt<1>("h00") + device_under_test.io.read_routing_table_response.ready <= T_1369[T_23] + node T_1451 = and(device_under_test.io.read_routing_table_response.ready, device_under_test.io.read_routing_table_response.valid) + when T_1451 : + node T_1454 = eq(reset, UInt<1>("h00")) + when T_1454 : + printf(clk, UInt<1>(1), "output test event %d testing read_routing_table_response.bits = %d, should be %d +", T_23, device_under_test.io.read_routing_table_response.bits, T_1438[T_1426]) + skip + node T_1456 = neq(device_under_test.io.read_routing_table_response.bits, T_1438[T_1426]) + when T_1456 : + node T_1459 = eq(reset, UInt<1>("h00")) + when T_1459 : + printf(clk, UInt<1>(1), "Error: event %d read_routing_table_response.bits was %d should be %d +", T_23, device_under_test.io.read_routing_table_response.bits, T_1438[T_1426]) + skip + node T_1462 = eq(reset, UInt<1>("h00")) + when T_1462 : + node T_1464 = eq(UInt<1>("h00"), UInt<1>("h00")) + when T_1464 : + node T_1466 = eq(reset, UInt<1>("h00")) + when T_1466 : + printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno)") + skip + stop(clk, UInt<1>(1), 1) + skip + skip + node T_1468 = eq(reset, UInt<1>("h00")) + when T_1468 : + stop(clk, UInt<1>(1), 0) + skip + skip + node T_1470 = eq(T_1426, UInt<6>("h021")) + node T_1472 = and(UInt<1>("h01"), T_1470) + node T_1475 = tail(add(T_1426, UInt<1>("h01")),1) + node T_1476 = mux(T_1472, UInt<1>("h00"), T_1475) + T_1426 <= T_1476 + node T_1478 = eq(T_25, UInt<1>("h00")) + when T_1478 : + node T_1480 = eq(T_23, UInt<6>("h021")) + when T_1480 : + T_25 <= UInt<1>("h01") + skip + node T_1483 = tail(add(T_23, UInt<1>("h01")),1) + T_23 <= T_1483 + skip + skip + node T_1485 = eq(reset, UInt<1>("h00")) + when T_1485 : + printf(clk, UInt<1>(1), "in_event_counter %d, out_event_counter %d +", T_19, T_23) + skip + + + diff --git a/test/passes/jacktest/Stack.fir b/test/passes/jacktest/Stack.fir index 319e87d5..3eb9c67c 100644 --- a/test/passes/jacktest/Stack.fir +++ b/test/passes/jacktest/Stack.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s ;CHECK: Done! circuit Stack : module Stack : @@ -11,25 +11,27 @@ circuit Stack : input dataIn : UInt<32> cmem stack_mem : UInt<32>[16] - reg sp : UInt<5>,clk,reset,UInt<5>(0) - reg out : UInt<32>,clk,reset,UInt<32>(0) + reg sp : UInt<5>,clk with : + reset => (reset,UInt<5>(0)) + reg out : UInt<32>,clk with : + reset => (reset,UInt<32>(0)) when en : node T_30 = lt(sp, UInt<5>(16)) node T_31 = and(push, T_30) when T_31 : write mport T_32 = stack_mem[sp],clk T_32 <= dataIn - node T_33 = addw(sp, UInt<1>(1)) + node T_33 = tail(add(sp, UInt<1>(1)),1) sp <= T_33 else : node T_34 = gt(sp, UInt<1>(0)) node T_35 = and(pop, T_34) when T_35 : - node T_36 = subw(sp, UInt<1>(1)) + node T_36 = tail(sub(sp, UInt<1>(1)),1) sp <= T_36 node T_37 = gt(sp, UInt<1>(0)) when T_37 : - node T_38 = subw(sp, UInt<1>(1)) + node T_38 = tail(sub(sp, UInt<1>(1)),1) read mport T_39 = stack_mem[T_38],clk out <= T_39 dataOut <= out diff --git a/test/passes/jacktest/VendingMachine.fir b/test/passes/jacktest/VendingMachine.fir index 79cebbe1..d7822a17 100644 --- a/test/passes/jacktest/VendingMachine.fir +++ b/test/passes/jacktest/VendingMachine.fir @@ -8,7 +8,8 @@ circuit VendingMachine : input clk : Clock input reset : UInt<1> - reg state : UInt<3>,clk,reset,UInt<3>(0) + reg state : UInt<3>,clk with : + reset => (reset,UInt<3>(0)) node T_22 = eq(state, UInt<3>(0)) when T_22 : when nickel : state <= UInt<3>(1) diff --git a/test/passes/jacktest/gcd.fir b/test/passes/jacktest/gcd.fir index dd3443f1..31ca30b2 100644 --- a/test/passes/jacktest/gcd.fir +++ b/test/passes/jacktest/gcd.fir @@ -10,14 +10,16 @@ circuit GCD : input a : UInt<16> input b : UInt<16> - reg x : UInt<16>,clk,reset,x - reg y : UInt<16>,clk,reset,y + reg x : UInt<16>,clk with : + reset => (reset,x) + reg y : UInt<16>,clk with : + reset => (reset,y) node T_17 = gt(x, y) when T_17 : - node T_18 = subw(x, y) + node T_18 = tail(sub(x, y),1) x <= T_18 else : - node T_19 = subw(y, x) + node T_19 = tail(sub(y, x),1) y <= T_19 when e : x <= a diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir index 46f5a1c2..f722cf97 100644 --- a/test/passes/jacktest/risc.fir +++ b/test/passes/jacktest/risc.fir @@ -13,7 +13,8 @@ circuit Risc : cmem file : UInt<32>[256] cmem code : UInt<32>[256] - reg pc : UInt<8>,clk,reset,UInt<8>(0) + reg pc : UInt<8>,clk with : + reset => (reset,UInt<8>(0)) read mport inst = code[pc],clk node op = bits(inst, 31, 24) node rci = bits(inst, 23, 16) @@ -36,7 +37,7 @@ circuit Risc : else : node T_56 = eq(UInt<1>(0), op) when T_56 : - node T_57 = addw(ra, rb) + node T_57 = tail(add(ra, rb),1) rc <= T_57 node T_58 = eq(UInt<1>(1), op) when T_58 : @@ -49,5 +50,5 @@ circuit Risc : else : write mport T_62 = file[rci],clk T_62 <= rc - node T_63 = addw(pc, UInt<1>(1)) + node T_63 = tail(add(pc, UInt<1>(1)),1) pc <= T_63 diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir index 64a4a4b6..cf581ab7 100644 --- a/test/passes/lower-to-ground/bundle-vecs.fir +++ b/test/passes/lower-to-ground/bundle-vecs.fir @@ -19,26 +19,20 @@ circuit top : j <= a[i] a[i] <= j -;CHECK: wire GEN_0 : UInt<32> -;CHECK: wire GEN_1 : UInt<32> -;CHECK: wire GEN_2 : UInt<32> -;CHECK: wire GEN_3 : UInt<32> -;CHECK: j_x <= GEN_0 -;CHECK: j_y <= GEN_3 -;CHECK: node GEN_4 = eqv(UInt("h0"), i) -;CHECK: a_0_x <= mux(GEN_4, GEN_2, UInt("h0")) -;CHECK: node GEN_5 = eqv(UInt("h0"), i) -;CHECK: a_0_y <= mux(GEN_5, GEN_1, UInt("h0")) -;CHECK: node GEN_6 = eqv(UInt("h1"), i) -;CHECK: a_1_x <= mux(GEN_6, GEN_2, UInt("h0")) -;CHECK: node GEN_7 = eqv(UInt("h1"), i) -;CHECK: a_1_y <= mux(GEN_7, GEN_1, UInt("h0")) -;CHECK: node GEN_8 = eqv(UInt("h1"), i) -;CHECK: GEN_0 <= mux(GEN_8, a_1_x, a_0_x) -;CHECK: GEN_1 <= j_y -;CHECK: GEN_2 <= j_x -;CHECK: node GEN_9 = eqv(UInt("h1"), i) -;CHECK: GEN_3 <= mux(GEN_9, a_1_y, a_0_y) +; CHECK: wire GEN_0 : UInt<32> +; CHECK: wire GEN_1 : UInt<32> +; CHECK: wire GEN_2 : UInt<32> +; CHECK: wire GEN_3 : UInt<32> +; CHECK: j_x <= GEN_0 +; CHECK: j_y <= GEN_3 +; CHECK: a_0_x <= mux(eq(UInt("h0"), i), GEN_2, UInt("h0")) +; CHECK: a_0_y <= mux(eq(UInt("h0"), i), GEN_1, UInt("h0")) +; CHECK: a_1_x <= mux(eq(UInt("h1"), i), GEN_2, UInt("h0")) +; CHECK: a_1_y <= mux(eq(UInt("h1"), i), GEN_1, UInt("h0")) +; CHECK: GEN_0 <= mux(eq(UInt("h1"), i), a_1_x, a_0_x) +; CHECK: GEN_1 <= j_y +; CHECK: GEN_2 <= j_x +; CHECK: GEN_3 <= mux(eq(UInt("h1"), i), a_1_y, a_0_y) ; CHECK: Finished Lower Types diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir index 0d4f5bf0..fcdee5bc 100644 --- a/test/passes/lower-to-ground/nested-vec.fir +++ b/test/passes/lower-to-ground/nested-vec.fir @@ -41,17 +41,17 @@ circuit top : m.c.data <= k ;CHECK: mem m_x : -;CHECK: data-type: UInt<32> -;CHECK: depth: 2 -;CHECK: write-latency: 1 -;CHECK: read-latency: 0 -;CHECK: writer: c +;CHECK: data-type => UInt<32> +;CHECK: depth => 2 +;CHECK: write-latency => 1 +;CHECK: read-latency => 0 +;CHECK: writer => c ;CHECK: mem m_y : -;CHECK: data-type: UInt<32> -;CHECK: depth: 2 -;CHECK: write-latency: 1 -;CHECK: read-latency: 0 -;CHECK: writer: c +;CHECK: data-type => UInt<32> +;CHECK: depth => 2 +;CHECK: write-latency => 1 +;CHECK: read-latency => 0 +;CHECK: writer => c ;CHECK: m_x.c.data <= k_x ;CHECK: m_y.c.data <= k_y ;CHECK: m_x.c.mask <= UInt("h1") diff --git a/test/passes/lower-to-ground/register.fir b/test/passes/lower-to-ground/register.fir index 66d1cfb3..648964bd 100644 --- a/test/passes/lower-to-ground/register.fir +++ b/test/passes/lower-to-ground/register.fir @@ -11,11 +11,14 @@ wire q : { x : UInt, y : SInt } q.x <= UInt(0) q.y <= SInt(0) - reg r1 : { x : UInt, y : SInt },clk,reset,q + reg r1 : { x : UInt, y : SInt } clk with : + reset => (reset,q) ; CHECK: wire q{{[_$]+}}x : UInt ; CHECK: wire q{{[_$]+}}y : SInt - ; CHECK: reg r1{{[_$]+}}x : UInt<1>, clk, reset, q_x - ; CHECK: reg r1{{[_$]+}}y : SInt<1>, clk, reset, q_y + ; CHECK: reg r1{{[_$]+}}x : UInt<1>, clk with : + ;CHECK: reset => (reset, q_x) + ; CHECK: reg r1{{[_$]+}}y : SInt<1>, clk with : + ;CHECK: reset => (reset, q_y) ; CHECK: Finished Lower Types diff --git a/test/passes/remove-accesses/bundle-vecs.fir b/test/passes/remove-accesses/bundle-vecs.fir index e916bfa8..e618892e 100644 --- a/test/passes/remove-accesses/bundle-vecs.fir +++ b/test/passes/remove-accesses/bundle-vecs.fir @@ -31,11 +31,11 @@ circuit top : ; CHECK: wire b : { x : UInt<32>, flip y : UInt<32>} ; CHECK: wire GEN_0 : UInt<32> ; CHECK: GEN_0 <= a[0].x -; CHECK: when eqv(UInt("h1"), i) : GEN_0 <= a[1].x +; CHECK: when eq(UInt("h1"), i) : GEN_0 <= a[1].x ; CHECK: b.x <= GEN_0 ; CHECK: wire GEN_1 : UInt<32> -; CHECK: when eqv(UInt("h0"), i) : a[0].y <= GEN_1 -; CHECK: when eqv(UInt("h1"), i) : a[1].y <= GEN_1 +; CHECK: when eq(UInt("h0"), i) : a[0].y <= GEN_1 +; CHECK: when eq(UInt("h1"), i) : a[1].y <= GEN_1 ; CHECK: GEN_1 <= b.y ; CHECK: j <= b.x ; CHECK: b.y <= UInt("h1") diff --git a/test/passes/remove-accesses/simple11.fir b/test/passes/remove-accesses/simple11.fir index e35bfb3c..b27f1a46 100644 --- a/test/passes/remove-accesses/simple11.fir +++ b/test/passes/remove-accesses/simple11.fir @@ -11,10 +11,14 @@ circuit DecoupledAdderTests : io.out.bits.c <= UInt<1>("h00") io.out.valid <= UInt<1>("h00") io.in.ready <= UInt<1>("h00") - reg ready : UInt<1>, clock, reset, ready - reg busy : UInt<1>, clock, reset, busy - reg a_reg : UInt<16>, clock, reset, a_reg - reg b_reg : UInt<16>, clock, reset, b_reg + reg ready : UInt<1>, clock with : + reset => ( reset, ready) + reg busy : UInt<1>, clock with : + reset => ( reset, busy) + reg a_reg : UInt<16>, clock with : + reset => ( reset, a_reg) + reg b_reg : UInt<16>, clock with : + reset => ( reset, b_reg) io.in.ready <= ready when io.in.valid : a_reg <= io.in.bits.a @@ -25,7 +29,7 @@ circuit DecoupledAdderTests : skip node T_45 = and(busy, io.out.ready) when T_45 : - node T_46 = addw(a_reg, b_reg) + node T_46 = tail(add(a_reg, b_reg),1) io.out.bits.c <= T_46 io.out.valid <= UInt<1>("h01") io.in.ready <= UInt<1>("h01") @@ -44,8 +48,9 @@ circuit DecoupledAdderTests : device_under_test.io.in.valid <= UInt<1>("h00") device_under_test.clock <= clock device_under_test.reset <= reset - reg T_10 : UInt<33>, clock, reset, UInt<33>("h00") - node T_12 = addw(T_10, UInt<1>("h01")) + reg T_10 : UInt<33>, clock with : + reset => ( reset, UInt<33>("h00")) + node T_12 = tail(add(T_10, UInt<1>("h01")),1) T_10 <= T_12 node T_14 = eq(reset, UInt<1>("h00")) when T_14 : @@ -66,8 +71,10 @@ circuit DecoupledAdderTests : when T_22 : printf(clock,UInt(1), "device in ready %d, valid %d", device_under_test.io.in.ready, device_under_test.io.in.valid) skip - reg T_24 : UInt<1>, clock, reset, UInt<1>("h00") - reg T_26 : UInt<1>, clock, reset, UInt<1>("h00") + reg T_24 : UInt<1>, clock with : + reset => ( reset, UInt<1>("h00")) + reg T_26 : UInt<1>, clock with : + reset => ( reset, UInt<1>("h00")) node T_27 = and(T_24, T_26) when T_27 : node T_29 = eq(reset, UInt<1>("h00")) @@ -75,8 +82,10 @@ circuit DecoupledAdderTests : stop(clock,UInt(1), 0) skip skip - reg T_31 : UInt<1>, clock, reset, UInt<1>("h00") - reg T_33 : UInt<1>, clock, reset, UInt<1>("h00") + reg T_31 : UInt<1>, clock with : + reset => ( reset, UInt<1>("h00")) + reg T_33 : UInt<1>, clock with : + reset => ( reset, UInt<1>("h00")) wire T_43 : {flip ready : UInt<1>, valid : UInt<1>, bits : {a : UInt<16>, b : UInt<16>}}[1] T_43[0].bits.b <= UInt(0) T_43[0].bits.a <= UInt(1) @@ -108,14 +117,14 @@ circuit DecoupledAdderTests : node T_113 = and(T_103, T_43[T_31].ready) when T_113 : T_43[T_31].valid <= UInt<1>("h01") - node T_125 = addw(T_31, UInt<1>("h01")) + node T_125 = tail(add(T_31, UInt<1>("h01")),1) T_31 <= T_125 node T_127 = geq(T_31, UInt<1>("h00")) T_24 <= T_127 skip node T_129 = eq(T_26, UInt<1>("h00")) when T_129 : - node T_131 = addw(T_33, UInt<1>("h01")) + node T_131 = tail(add(T_33, UInt<1>("h01")),1) T_33 <= T_131 node T_133 = geq(T_33, UInt<1>("h00")) T_26 <= T_133 diff --git a/test/passes/remove-accesses/simple3.fir b/test/passes/remove-accesses/simple3.fir index b19c4130..6305e0c9 100644 --- a/test/passes/remove-accesses/simple3.fir +++ b/test/passes/remove-accesses/simple3.fir @@ -13,8 +13,8 @@ circuit top : a <= in ;CHECK: wire GEN_0 : UInt<32> -;CHECK: when eqv(UInt("h0"), i) : m[0] <= GEN_0 -;CHECK: when eqv(UInt("h1"), i) : m[1] <= GEN_0 +;CHECK: when eq(UInt("h0"), i) : m[0] <= GEN_0 +;CHECK: when eq(UInt("h1"), i) : m[1] <= GEN_0 ;CHECK: GEN_0 <= a ;CHECK: Finished Remove Accesses diff --git a/test/passes/remove-accesses/simple4.fir b/test/passes/remove-accesses/simple4.fir index 06ff7481..4766214c 100644 --- a/test/passes/remove-accesses/simple4.fir +++ b/test/passes/remove-accesses/simple4.fir @@ -12,8 +12,8 @@ circuit top : m[1].y <= UInt("h1") m[i].x <= in.x -;CHECK: when eqv(UInt("h0"), i) : m[0].x <= GEN_0 -;CHECK: when eqv(UInt("h1"), i) : m[1].x <= GEN_0 +;CHECK: when eq(UInt("h0"), i) : m[0].x <= GEN_0 +;CHECK: when eq(UInt("h1"), i) : m[1].x <= GEN_0 ;CHECK: GEN_0 <= in ;CHECK: Finished Remove Accesses ;CHECK: Done! diff --git a/test/passes/remove-accesses/simple5.fir b/test/passes/remove-accesses/simple5.fir index 0a1baed6..d2e31537 100644 --- a/test/passes/remove-accesses/simple5.fir +++ b/test/passes/remove-accesses/simple5.fir @@ -15,7 +15,7 @@ circuit top : ;CHECK: when i : ;CHECK: GEN_0 <= m[0] -;CHECK: when eqv(UInt("h1"), i) : GEN_0 <= m[1] +;CHECK: when eq(UInt("h1"), i) : GEN_0 <= m[1] ;CHECK: o <= GEN_0 ;CHECK: Finished Remove Accesses ;CHECK: Done! diff --git a/test/passes/remove-accesses/simple8.fir b/test/passes/remove-accesses/simple8.fir index 6b084ed3..1d275618 100644 --- a/test/passes/remove-accesses/simple8.fir +++ b/test/passes/remove-accesses/simple8.fir @@ -21,25 +21,26 @@ circuit top : wire T_75 : UInt<128>[2] T_75[0] <= UInt<1>("h00") T_75[1] <= UInt<1>("h00") - reg T_81 : UInt<12>, clock, reset, T_81 + reg T_81 : UInt<12>, clock with : + reset => ( reset, T_81) when read.valid : T_81 <= read.bits.addr skip cmem T_84 : UInt<128>[256] node T_86 = neq(T_65, UInt<1>("h00")) node T_87 = and(T_86, write.valid) - node T_88 = bit(write.bits.wmask, 0) + node T_88 = bits(write.bits.wmask, 0, 0) node T_89 = and(T_87, T_88) when T_89 : node T_90 = bits(write.bits.data, 63, 0) node T_91 = cat(T_90, T_90) - node T_92 = bit(T_65, 0) - node T_93 = bit(T_65, 1) + node T_92 = bits(T_65, 0, 0) + node T_93 = bits(T_65, 1, 1) wire T_95 : UInt<1>[2] T_95[0] <= T_92 T_95[1] <= T_93 - node T_100 = subw(UInt<64>("h00"), T_95[0]) - node T_102 = subw(UInt<64>("h00"), T_95[1]) + node T_100 = tail(sub(UInt<64>("h00"), T_95[0]),1) + node T_102 = tail(sub(UInt<64>("h00"), T_95[1]),1) wire T_104 : UInt<64>[2] T_104[0] <= T_100 T_104[1] <= T_102 @@ -57,7 +58,8 @@ circuit top : skip node T_118 = neq(T_66, UInt<1>("h00")) node T_119 = and(T_118, read.valid) - reg T_120 : UInt<8>, clock, reset, T_120 + reg T_120 : UInt<8>, clock with : + reset => ( reset, T_120) when T_119 : T_120 <= raddr skip @@ -66,18 +68,18 @@ circuit top : cmem T_124 : UInt<128>[256] node T_126 = neq(T_65, UInt<1>("h00")) node T_127 = and(T_126, write.valid) - node T_128 = bit(write.bits.wmask, 1) + node T_128 = bits(write.bits.wmask, 1, 1) node T_129 = and(T_127, T_128) when T_129 : node T_130 = bits(write.bits.data, 127, 64) node T_131 = cat(T_130, T_130) - node T_132 = bit(T_65, 0) - node T_133 = bit(T_65, 1) + node T_132 = bits(T_65, 0, 0) + node T_133 = bits(T_65, 1, 1) wire T_135 : UInt<1>[2] T_135[0] <= T_132 T_135[1] <= T_133 - node T_140 = subw(UInt<64>("h00"), T_135[0]) - node T_142 = subw(UInt<64>("h00"), T_135[1]) + node T_140 = tail(sub(UInt<64>("h00"), T_135[0]),1) + node T_142 = tail(sub(UInt<64>("h00"), T_135[1]),1) wire T_144 : UInt<64>[2] T_144[0] <= T_140 T_144[1] <= T_142 @@ -95,7 +97,8 @@ circuit top : skip node T_158 = neq(T_66, UInt<1>("h00")) node T_159 = and(T_158, read.valid) - reg T_160 : UInt<8>, clock, reset, T_160 + reg T_160 : UInt<8>, clock with : + reset => ( reset, T_160) when T_159 : T_160 <= raddr skip @@ -128,25 +131,26 @@ circuit top : wire T_202 : UInt<128>[2] T_202[0] <= UInt<1>("h00") T_202[1] <= UInt<1>("h00") - reg T_208 : UInt<12>, clock, reset, T_208 + reg T_208 : UInt<12>, clock with : + reset => ( reset, T_208) when read.valid : T_208 <= read.bits.addr skip cmem T_211 : UInt<128>[256] node T_213 = neq(T_192, UInt<1>("h00")) node T_214 = and(T_213, write.valid) - node T_215 = bit(write.bits.wmask, 0) + node T_215 = bits(write.bits.wmask, 0, 0) node T_216 = and(T_214, T_215) when T_216 : node T_217 = bits(write.bits.data, 63, 0) node T_218 = cat(T_217, T_217) - node T_219 = bit(T_192, 0) - node T_220 = bit(T_192, 1) + node T_219 = bits(T_192, 0, 0) + node T_220 = bits(T_192, 1, 1) wire T_222 : UInt<1>[2] T_222[0] <= T_219 T_222[1] <= T_220 - node T_227 = subw(UInt<64>("h00"), T_222[0]) - node T_229 = subw(UInt<64>("h00"), T_222[1]) + node T_227 = tail(sub(UInt<64>("h00"), T_222[0]),1) + node T_229 = tail(sub(UInt<64>("h00"), T_222[1]),1) wire T_231 : UInt<64>[2] T_231[0] <= T_227 T_231[1] <= T_229 @@ -164,7 +168,8 @@ circuit top : skip node T_245 = neq(T_193, UInt<1>("h00")) node T_246 = and(T_245, read.valid) - reg T_247 : UInt<8>, clock, reset, T_247 + reg T_247 : UInt<8>, clock with : + reset => ( reset, T_247) when T_246 : T_247 <= raddr skip @@ -173,18 +178,18 @@ circuit top : cmem T_251 : UInt<128>[256] node T_253 = neq(T_192, UInt<1>("h00")) node T_254 = and(T_253, write.valid) - node T_255 = bit(write.bits.wmask, 1) + node T_255 = bits(write.bits.wmask, 1, 1) node T_256 = and(T_254, T_255) when T_256 : node T_257 = bits(write.bits.data, 127, 64) node T_258 = cat(T_257, T_257) - node T_259 = bit(T_192, 0) - node T_260 = bit(T_192, 1) + node T_259 = bits(T_192, 0, 0) + node T_260 = bits(T_192, 1, 1) wire T_262 : UInt<1>[2] T_262[0] <= T_259 T_262[1] <= T_260 - node T_267 = subw(UInt<64>("h00"), T_262[0]) - node T_269 = subw(UInt<64>("h00"), T_262[1]) + node T_267 = tail(sub(UInt<64>("h00"), T_262[0]),1) + node T_269 = tail(sub(UInt<64>("h00"), T_262[1]),1) wire T_271 : UInt<64>[2] T_271[0] <= T_267 T_271[1] <= T_269 @@ -202,7 +207,8 @@ circuit top : skip node T_285 = neq(T_193, UInt<1>("h00")) node T_286 = and(T_285, read.valid) - reg T_287 : UInt<8>, clock, reset, T_287 + reg T_287 : UInt<8>, clock with : + reset => ( reset, T_287) when T_286 : T_287 <= raddr skip diff --git a/test/passes/remove-accesses/simple9.fir b/test/passes/remove-accesses/simple9.fir index 5405c42a..d1aec9f1 100644 --- a/test/passes/remove-accesses/simple9.fir +++ b/test/passes/remove-accesses/simple9.fir @@ -7,7 +7,8 @@ circuit top : input reset : UInt<1> input clock : Clock output out : UInt<1> - reg T_4590 : UInt<1>[2], clock, reset, T_4590 + reg T_4590 : UInt<1>[2], clock with : + reset => ( reset, T_4590) T_4590[0] <= UInt(0) T_4590[1] <= UInt(0) out <= UInt(0) diff --git a/test/passes/resolve-genders/gcd.fir b/test/passes/resolve-genders/gcd.fir index 4d7772d9..c2a0df4a 100644 --- a/test/passes/resolve-genders/gcd.fir +++ b/test/passes/resolve-genders/gcd.fir @@ -6,8 +6,8 @@ circuit top : input x : UInt input y : UInt output z : UInt - z <= subw(x, y) - ;CHECK: z@<g:f> <= subw(x@<g:m>, y@<g:m>) + z <= tail(sub(x, y),1) + ;CHECK: z@<g:f> <= tail(sub(x@<g:m>, y@<g:m>)@<g:m>, 1)@<g:m> module gcd : input a : UInt<16> input b : UInt<16> @@ -16,8 +16,10 @@ circuit top : input reset : UInt<1> output z : UInt<16> output v : UInt<1> - reg x : UInt,clk,reset,UInt(0) - reg y : UInt,clk,reset,UInt(42) + reg x : UInt,clk with : + reset => (reset,UInt(0)) + reg y : UInt,clk with : + reset => (reset,UInt(42)) ; CHECK: reg x : UInt when gt(x, y) : ;CHECK: when gt(x@<g:m>, y@<g:m>)@<g:m> : diff --git a/test/passes/resolve-genders/subbundle.fir b/test/passes/resolve-genders/subbundle.fir index 0d0dd574..e91fa52e 100644 --- a/test/passes/resolve-genders/subbundle.fir +++ b/test/passes/resolve-genders/subbundle.fir @@ -6,7 +6,8 @@ circuit top : input clk : Clock input reset : UInt<1> wire w : { flip x : UInt<10>} - reg r : { flip x : UInt<10>},clk,reset,w + reg r : { flip x : UInt<10>},clk with : + reset => (reset,w) w <= r ; CHECK r_x := w_x w.x <= r.x ; CHECK w_x := r_x ; CHECK: Finished Lower Types diff --git a/test/passes/resolve-kinds/gcd.fir b/test/passes/resolve-kinds/gcd.fir index bb978972..cdc8c337 100644 --- a/test/passes/resolve-kinds/gcd.fir +++ b/test/passes/resolve-kinds/gcd.fir @@ -6,8 +6,8 @@ circuit top : input x : UInt input y : UInt output z : UInt - z <= subw(x, y) - ;CHECK: z@<k:port> <= subw(x@<k:port>, y@<k:port>) + z <= tail(sub(x, y),1) + ;CHECK: z@<k:port> <= tail(sub(x@<k:port>, y@<k:port>)@<k:exp>, 1)@<k:exp> module gcd : input clk : Clock input reset : UInt<1> @@ -16,8 +16,10 @@ circuit top : input e : UInt<1> output z : UInt<16> output v : UInt<1> - reg x : UInt,clk,reset,UInt(0) - reg y : UInt,clk,reset,UInt(42) + reg x : UInt,clk with : + reset => (reset,UInt(0)) + reg y : UInt,clk with : + reset => (reset,UInt(42)) when gt(x, y) : inst s of subtracter s.x <= x diff --git a/test/passes/split-exp/gcd.fir b/test/passes/split-exp/gcd.fir index e651f41a..4b42d007 100644 --- a/test/passes/split-exp/gcd.fir +++ b/test/passes/split-exp/gcd.fir @@ -6,7 +6,7 @@ circuit top : input x : UInt input y : UInt output q : UInt - q <= subw(x, y) + q <= tail(sub(x, y),1) module gcd : input clk : Clock input reset : UInt<1> @@ -14,8 +14,10 @@ circuit top : input b : UInt<16> input e : UInt<1> output z : UInt<16> - reg x : UInt,clk,reset,UInt(0) - reg y : UInt,clk,reset,UInt(42) + reg x : UInt,clk with : + reset => (reset,UInt(0)) + reg y : UInt,clk with : + reset => (reset,UInt(42)) when gt(x, y) : inst s of subtracter s.x <= x diff --git a/test/passes/split-exp/split-and.fir b/test/passes/split-exp/split-and.fir new file mode 100644 index 00000000..8eb4bdab --- /dev/null +++ b/test/passes/split-exp/split-and.fir @@ -0,0 +1,8 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s + +; CHECK: Done! +circuit Top : + module Top : + input a : SInt<2> + output c : UInt<2> + c <= and(a,asSInt(UInt(2))) diff --git a/test/passes/split-exp/split-in-when.fir b/test/passes/split-exp/split-in-when.fir index e4d0da36..207ad757 100644 --- a/test/passes/split-exp/split-in-when.fir +++ b/test/passes/split-exp/split-in-when.fir @@ -9,13 +9,14 @@ circuit Top : input b : UInt<10> input c : UInt<10> - reg out : UInt<10>,clk,p,a + reg out : UInt<10>,clk with : + reset => (p,a) - when bit(subw(a,c),3) : out <= mux(eqv(bits(UInt(32),4,0),UInt(13)),addw(a,addw(b,c)),subw(c,b)) + when bits(tail(sub(a,c),1),3,3) : out <= mux(eq(bits(UInt(32),4,0),UInt(13)),tail(add(a,tail(add(b,c),1)),1),tail(sub(c,b),1)) ;CHECK: node GEN_0 = subw(a, c) -;CHECK: node GEN_1 = bit(GEN_0, 3) -;CHECK: node GEN_2 = eqv(UInt("h0"), UInt("hd")) +;CHECK: node GEN_1 = bits(GEN_0, 3, 3) +;CHECK: node GEN_2 = eq(UInt("h0"), UInt("hd")) ;CHECK: node GEN_3 = addw(b, c) ;CHECK: node GEN_4 = addw(a, GEN_3) ;CHECK: node GEN_5 = subw(c, b) diff --git a/test/passes/to-verilog/gcd.fir b/test/passes/to-verilog/gcd.fir index cadd9ec8..5a50ddd1 100644 --- a/test/passes/to-verilog/gcd.fir +++ b/test/passes/to-verilog/gcd.fir @@ -6,7 +6,7 @@ circuit top : input x : UInt input y : UInt output q : UInt - q <= subw(x, y) + q <= tail(sub(x, y),1) module gcd : input clk : Clock input reset : UInt<1> @@ -14,8 +14,10 @@ circuit top : input b : UInt<16> input e : UInt<1> output z : UInt<16> - reg x : UInt,clk,reset,UInt(0) - reg y : UInt,clk,reset,UInt(42) + reg x : UInt,clk with : + reset => (reset,UInt(0)) + reg y : UInt,clk with : + reset => (reset,UInt(42)) when gt(x, y) : inst s of subtracter s.x <= x diff --git a/test/passes/to-verilog/rdwr-mem.fir b/test/passes/to-verilog/rdwr-mem.fir index e382b3b5..c7897163 100644 --- a/test/passes/to-verilog/rdwr-mem.fir +++ b/test/passes/to-verilog/rdwr-mem.fir @@ -18,51 +18,44 @@ circuit top : c <= wdata -; CHECK: module top( -; CHECK: output [31:0] rdata, -; CHECK: input [31:0] wdata, -; CHECK: input [1:0] index, -; CHECK: input ren, -; CHECK: input wen, -; CHECK: input clk -; CHECK: ); -; CHECK: reg [31:0] m [0:3]; -; CHECK: wire [31:0] m_c_rdata; -; CHECK: wire [1:0] m_c_raddr; -; CHECK: wire m_c_ren; -; CHECK: wire [31:0] m_c_wdata; -; CHECK: wire [1:0] m_c_waddr; -; CHECK: wire m_c_wmask; -; CHECK: wire m_c_wen; -; CHECK: wire m_c_clk; -; CHECK: reg [1:0] GEN_2; -; CHECK: reg GEN_3; -; CHECK: reg [1:0] GEN_0; -; CHECK: reg [31:0] GEN_1; -; CHECK: assign rdata = m_c_rdata; -; CHECK: assign m_c_clk = clk; -; CHECK: assign m_c_raddr = index; -; CHECK: assign m_c_ren = 1'h1; -; CHECK: assign m_c_rdata = m[GEN_2]; -; CHECK: assign m_c_wdata = wen ? wdata : GEN_1; -; CHECK: assign m_c_waddr = index; -; CHECK: assign m_c_wmask = wen ? 1'h1 : 1'h0; -; CHECK: assign m_c_wen = 1'h1; -; CHECK: `ifndef SYNTHESIS -; CHECK: integer initvar; -; CHECK: initial begin -; CHECK: #0.002; -; CHECK: for (initvar = 0; initvar < 4; initvar = initvar+1) -; CHECK: m[initvar] = {1{$random}}; -; CHECK: GEN_0 = {1{$random}}; -; CHECK: GEN_1 = {1{$random}}; -; CHECK: end -; CHECK: `endif -; CHECK: always @(posedge m_c_clk) begin -; CHECK: GEN_2 <= m_c_raddr; -; CHECK: GEN_3 <= m_c_ren; -; CHECK: if(m_c_wen & m_c_wmask) begin -; CHECK: m[m_c_waddr] <= m_c_wdata; -; CHECK: end -; CHECK: end -; CHECK: endmodule +;CHECK: module top( +;CHECK: output [31:0] rdata, +;CHECK: input [31:0] wdata, +;CHECK: input [1:0] index, +;CHECK: input ren, +;CHECK: input wen, +;CHECK: input clk +;CHECK: ); +;CHECK: reg [31:0] m [0:3]; +;CHECK: wire m_c_wmode; +;CHECK: wire [31:0] m_c_rdata; +;CHECK: wire [31:0] m_c_data; +;CHECK: wire m_c_mask; +;CHECK: wire [1:0] m_c_addr; +;CHECK: wire m_c_en; +;CHECK: wire m_c_clk; +;CHECK: reg [1:0] GEN_0; +;CHECK: assign rdata = m_c_rdata; +;CHECK: assign m_c_clk = clk; +;CHECK: assign m_c_addr = index; +;CHECK: assign m_c_data = wdata; +;CHECK: assign m_c_addr = index; +;CHECK: assign m_c_mask = wen ? 1'h1 : 1'h0; +;CHECK: assign m_c_en = 1'h1; +;CHECK: assign m_c_wmode = wen ? 1'h1 : 1'h0; +;CHECK: assign m_c_rdata = m[GEN_0]; +;CHECK: `ifndef SYNTHESIS +;CHECK: integer initvar; +;CHECK: initial begin +;CHECK: #0.002; +;CHECK: for (initvar = 0; initvar < 4; initvar = initvar+1) +;CHECK: m[initvar] = {1{$random}}; +;CHECK: end +;CHECK: `endif +;CHECK: always @(posedge m_c_clk) begin +;CHECK: GEN_0 <= m_c_addr; +;CHECK: if(m_c_en & m_c_mask & m_c_wmode) begin +;CHECK: m[m_c_addr] <= m_c_data; +;CHECK: end +;CHECK: end +;CHECK: endmodule diff --git a/test/passes/to-verilog/shr.fir b/test/passes/to-verilog/shr.fir index d8e889da..6921e74e 100644 --- a/test/passes/to-verilog/shr.fir +++ b/test/passes/to-verilog/shr.fir @@ -16,9 +16,12 @@ circuit HellaCache : inst dtlb of TLB_60 poison init : {addr : UInt<40>} - reg s1_req : {addr : UInt<40>}, clock, reset, init - reg s2_req : {addr : UInt<40>}, clock, reset, init - reg s1_clk_en : UInt<1>, clock, reset, UInt(0) + reg s1_req : {addr : UInt<40>}, clock with : + reset => ( reset, init) + reg s2_req : {addr : UInt<40>}, clock with : + reset => ( reset, init) + reg s1_clk_en : UInt<1>, clock with : + reset => ( reset, UInt(0)) node T_928 = bits(s1_req.addr, 11, 0) node s1_addr = cat(dtlb.resp.ppn, T_928) diff --git a/test/passes/to-verilog/signed-and.fir b/test/passes/to-verilog/signed-and.fir new file mode 100644 index 00000000..ffb7bd23 --- /dev/null +++ b/test/passes/to-verilog/signed-and.fir @@ -0,0 +1,17 @@ +; RUN: firrtl -i %s -o %s.v -X verilog ; cat %s.v | FileCheck %s + +circuit Top : + module Top : + input a : SInt<2> + output c : UInt<2> + c <= and(a,asSInt(UInt(2))) + +; CHECK: module Top( +; CHECK: input [1:0] a, +; CHECK: output [1:0] c +; CHECK: ); +; CHECK: wire [1:0] GEN_0; +; CHECK: assign c = $signed(a) & $signed(GEN_0); +; CHECK: assign GEN_0 = $signed(2'h2); +; CHECK: endmodule + diff --git a/test/passes/to-verilog/wr-mem.fir b/test/passes/to-verilog/wr-mem.fir index 06745812..8c197265 100644 --- a/test/passes/to-verilog/wr-mem.fir +++ b/test/passes/to-verilog/wr-mem.fir @@ -12,39 +12,34 @@ circuit top : when wen : c <= wdata -; CHECK: module top( -; CHECK: input [31:0] wdata, -; CHECK: input [1:0] index, -; CHECK: input wen, -; CHECK: input clk -; CHECK: ); -; CHECK: reg [31:0] m [0:3]; -; CHECK: wire [31:0] m_c_data; -; CHECK: wire [1:0] m_c_addr; -; CHECK: wire m_c_mask; -; CHECK: wire m_c_en; -; CHECK: wire m_c_clk; -; CHECK: reg [1:0] GEN_0; -; CHECK: reg [31:0] GEN_1; -; CHECK: assign m_c_data = wen ? wdata : GEN_1; -; CHECK: assign m_c_addr = index; -; CHECK: assign m_c_mask = wen ? 1'h1 : 1'h0; -; CHECK: assign m_c_en = 1'h1; -; CHECK: assign m_c_clk = clk; -; CHECK: `ifndef SYNTHESIS -; CHECK: integer initvar; -; CHECK: initial begin -; CHECK: #0.002; -; CHECK: for (initvar = 0; initvar < 4; initvar = initvar+1) -; CHECK: m[initvar] = {1{$random}}; -; CHECK: GEN_0 = {1{$random}}; -; CHECK: GEN_1 = {1{$random}}; -; CHECK: end -; CHECK: `endif -; CHECK: always @(posedge m_c_clk) begin -; CHECK: if(m_c_en & m_c_mask) begin -; CHECK: m[m_c_addr] <= m_c_data; -; CHECK: end -; CHECK: end -; CHECK: endmodule - +;CHECK: module top( +;CHECK: input [31:0] wdata, +;CHECK: input [1:0] index, +;CHECK: input wen, +;CHECK: input clk +;CHECK: ); +;CHECK: reg [31:0] m [0:3]; +;CHECK: wire [31:0] m_c_data; +;CHECK: wire [1:0] m_c_addr; +;CHECK: wire m_c_mask; +;CHECK: wire m_c_en; +;CHECK: wire m_c_clk; +;CHECK: assign m_c_data = wdata; +;CHECK: assign m_c_addr = index; +;CHECK: assign m_c_mask = wen ? 1'h1 : 1'h0; +;CHECK: assign m_c_en = 1'h1; +;CHECK: assign m_c_clk = clk; +;CHECK: `ifndef SYNTHESIS +;CHECK: integer initvar; +;CHECK: initial begin +;CHECK: #0.002; +;CHECK: for (initvar = 0; initvar < 4; initvar = initvar+1) +;CHECK: m[initvar] = {1{$random}}; +;CHECK: end +;CHECK: `endif +;CHECK: always @(posedge m_c_clk) begin +;CHECK: if(m_c_en & m_c_mask) begin +;CHECK: m[m_c_addr] <= m_c_data; +;CHECK: end +;CHECK: end +;CHECK: endmodule diff --git a/utils/bin/FileCheck_mac b/utils/bin/FileCheck_mac Binary files differnew file mode 100755 index 00000000..2ab52bb6 --- /dev/null +++ b/utils/bin/FileCheck_mac |