Fixed rdwr and wr to verilog tests

2 files changed, 72 insertions, 84 deletions

diff --git a/test/passes/to-verilog/rdwr-mem.fir b/test/passes/to-verilog/rdwr-mem.fir
index e382b3b5..c7897163 100644
--- a/test/passes/to-verilog/rdwr-mem.fir
+++ b/test/passes/to-verilog/rdwr-mem.fir
@@ -18,51 +18,44 @@ circuit top :
          c <= wdata
 
 
-; CHECK: module top(
-; CHECK:    output [31:0] rdata,
-; CHECK:    input  [31:0] wdata,
-; CHECK:    input  [1:0] index,
-; CHECK:    input   ren,
-; CHECK:    input   wen,
-; CHECK:    input   clk
-; CHECK: );
-; CHECK:    reg [31:0] m [0:3];
-; CHECK:    wire [31:0] m_c_rdata;
-; CHECK:    wire [1:0] m_c_raddr;
-; CHECK:    wire  m_c_ren;
-; CHECK:    wire [31:0] m_c_wdata;
-; CHECK:    wire [1:0] m_c_waddr;
-; CHECK:    wire  m_c_wmask;
-; CHECK:    wire  m_c_wen;
-; CHECK:    wire  m_c_clk;
-; CHECK:    reg [1:0] GEN_2;
-; CHECK:    reg  GEN_3;
-; CHECK:    reg [1:0] GEN_0;
-; CHECK:    reg [31:0] GEN_1;
-; CHECK:    assign rdata = m_c_rdata;
-; CHECK:    assign m_c_clk = clk;
-; CHECK:    assign m_c_raddr = index;
-; CHECK:    assign m_c_ren = 1'h1;
-; CHECK:    assign m_c_rdata = m[GEN_2];
-; CHECK:    assign m_c_wdata = wen ? wdata : GEN_1;
-; CHECK:    assign m_c_waddr = index;
-; CHECK:    assign m_c_wmask = wen ? 1'h1 : 1'h0;
-; CHECK:    assign m_c_wen = 1'h1;
-; CHECK: `ifndef SYNTHESIS
-; CHECK:   integer initvar;
-; CHECK:   initial begin
-; CHECK:     #0.002;
-; CHECK:    for (initvar = 0; initvar < 4; initvar = initvar+1)
-; CHECK:       m[initvar] = {1{$random}};
-; CHECK:    GEN_0 = {1{$random}};
-; CHECK:    GEN_1 = {1{$random}};
-; CHECK:   end
-; CHECK: `endif
-; CHECK:    always @(posedge m_c_clk) begin
-; CHECK:       GEN_2 <= m_c_raddr;
-; CHECK:       GEN_3 <= m_c_ren;
-; CHECK:       if(m_c_wen & m_c_wmask) begin
-; CHECK:          m[m_c_waddr] <= m_c_wdata;
-; CHECK:       end
-; CHECK:    end
-; CHECK: endmodule
+;CHECK: module top(
+;CHECK:    output [31:0] rdata,
+;CHECK:    input  [31:0] wdata,
+;CHECK:    input  [1:0] index,
+;CHECK:    input   ren,
+;CHECK:    input   wen,
+;CHECK:    input   clk
+;CHECK: );
+;CHECK:    reg [31:0] m [0:3];
+;CHECK:    wire  m_c_wmode;
+;CHECK:    wire [31:0] m_c_rdata;
+;CHECK:    wire [31:0] m_c_data;
+;CHECK:    wire  m_c_mask;
+;CHECK:    wire [1:0] m_c_addr;
+;CHECK:    wire  m_c_en;
+;CHECK:    wire  m_c_clk;
+;CHECK:    reg [1:0] GEN_0;
+;CHECK:    assign rdata = m_c_rdata;
+;CHECK:    assign m_c_clk = clk;
+;CHECK:    assign m_c_addr = index;
+;CHECK:    assign m_c_data = wdata;
+;CHECK:    assign m_c_addr = index;
+;CHECK:    assign m_c_mask = wen ? 1'h1 : 1'h0;
+;CHECK:    assign m_c_en = 1'h1;
+;CHECK:    assign m_c_wmode = wen ? 1'h1 : 1'h0;
+;CHECK:    assign m_c_rdata = m[GEN_0];
+;CHECK: `ifndef SYNTHESIS
+;CHECK:   integer initvar;
+;CHECK:   initial begin
+;CHECK:     #0.002;
+;CHECK:    for (initvar = 0; initvar < 4; initvar = initvar+1)
+;CHECK:       m[initvar] = {1{$random}};
+;CHECK:   end
+;CHECK: `endif
+;CHECK:    always @(posedge m_c_clk) begin
+;CHECK:       GEN_0 <= m_c_addr;
+;CHECK:       if(m_c_en & m_c_mask & m_c_wmode) begin
+;CHECK:          m[m_c_addr] <= m_c_data;
+;CHECK:       end
+;CHECK:    end
+;CHECK: endmodule
diff --git a/test/passes/to-verilog/wr-mem.fir b/test/passes/to-verilog/wr-mem.fir
index 06745812..8c197265 100644
--- a/test/passes/to-verilog/wr-mem.fir
+++ b/test/passes/to-verilog/wr-mem.fir
@@ -12,39 +12,34 @@ circuit top :
       when wen :
          c <= wdata
 
-; CHECK: module top(
-; CHECK:    input  [31:0] wdata,
-; CHECK:    input  [1:0] index,
-; CHECK:    input   wen,
-; CHECK:    input   clk
-; CHECK: );
-; CHECK:    reg [31:0] m [0:3];
-; CHECK:    wire [31:0] m_c_data;
-; CHECK:    wire [1:0] m_c_addr;
-; CHECK:    wire  m_c_mask;
-; CHECK:    wire  m_c_en;
-; CHECK:    wire  m_c_clk;
-; CHECK:    reg [1:0] GEN_0;
-; CHECK:    reg [31:0] GEN_1;
-; CHECK:    assign m_c_data = wen ? wdata : GEN_1;
-; CHECK:    assign m_c_addr = index;
-; CHECK:    assign m_c_mask = wen ? 1'h1 : 1'h0;
-; CHECK:    assign m_c_en = 1'h1;
-; CHECK:    assign m_c_clk = clk;
-; CHECK: `ifndef SYNTHESIS
-; CHECK:   integer initvar;
-; CHECK:   initial begin
-; CHECK:     #0.002;
-; CHECK:    for (initvar = 0; initvar < 4; initvar = initvar+1)
-; CHECK:       m[initvar] = {1{$random}};
-; CHECK:    GEN_0 = {1{$random}};
-; CHECK:    GEN_1 = {1{$random}};
-; CHECK:   end
-; CHECK: `endif
-; CHECK:    always @(posedge m_c_clk) begin
-; CHECK:       if(m_c_en & m_c_mask) begin
-; CHECK:          m[m_c_addr] <= m_c_data;
-; CHECK:       end
-; CHECK:    end
-; CHECK: endmodule
-
+;CHECK: module top(
+;CHECK:    input  [31:0] wdata,
+;CHECK:    input  [1:0] index,
+;CHECK:    input   wen,
+;CHECK:    input   clk
+;CHECK: );
+;CHECK:    reg [31:0] m [0:3];
+;CHECK:    wire [31:0] m_c_data;
+;CHECK:    wire [1:0] m_c_addr;
+;CHECK:    wire  m_c_mask;
+;CHECK:    wire  m_c_en;
+;CHECK:    wire  m_c_clk;
+;CHECK:    assign m_c_data = wdata;
+;CHECK:    assign m_c_addr = index;
+;CHECK:    assign m_c_mask = wen ? 1'h1 : 1'h0;
+;CHECK:    assign m_c_en = 1'h1;
+;CHECK:    assign m_c_clk = clk;
+;CHECK: `ifndef SYNTHESIS
+;CHECK:   integer initvar;
+;CHECK:   initial begin
+;CHECK:     #0.002;
+;CHECK:    for (initvar = 0; initvar < 4; initvar = initvar+1)
+;CHECK:       m[initvar] = {1{$random}};
+;CHECK:   end
+;CHECK: `endif
+;CHECK:    always @(posedge m_c_clk) begin
+;CHECK:       if(m_c_en & m_c_mask) begin
+;CHECK:          m[m_c_addr] <= m_c_data;
+;CHECK:       end
+;CHECK:    end
+;CHECK: endmodule