diff options
| author | azidar | 2015-07-13 16:22:43 -0700 |
|---|---|---|
| committer | azidar | 2015-07-13 16:22:43 -0700 |
| commit | 9b6d8514a3be860562d8d524fa425c87d1537e8a (patch) | |
| tree | ca46b9703046e23068860b5c5d8d6af01296c000 /test/passes/jacktest/ModuleVec.fir | |
| parent | 1ed6d4a47c92072b12db4b784f239071e4928049 (diff) | |
Added tests for clocks. Added remove scope and special chars passes. Added tests. Made more tests pass
Diffstat (limited to 'test/passes/jacktest/ModuleVec.fir')
| -rw-r--r-- | test/passes/jacktest/ModuleVec.fir | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/test/passes/jacktest/ModuleVec.fir b/test/passes/jacktest/ModuleVec.fir index 04c119a1..2fde69f3 100644 --- a/test/passes/jacktest/ModuleVec.fir +++ b/test/passes/jacktest/ModuleVec.fir @@ -5,13 +5,13 @@ circuit ModuleVec : input in : UInt<32> output out : UInt<32> - node T_33 = add-wrap(in, UInt<1>(1)) + node T_33 = addw(in, UInt<1>(1)) out := T_33 module PlusOne_25 : input in : UInt<32> output out : UInt<32> - node T_34 = add-wrap(in, UInt<1>(1)) + node T_34 = addw(in, UInt<1>(1)) out := T_34 module ModuleVec : input ins : UInt<32>[2] |