New memory works with verilog. Slowly changing tests and fixing bugs.

Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables

1 files changed, 9 insertions, 9 deletions

diff --git a/test/passes/jacktest/EnableShiftRegister.fir b/test/passes/jacktest/EnableShiftRegister.fir
index 902098b7..7937d37f 100644
--- a/test/passes/jacktest/EnableShiftRegister.fir
+++ b/test/passes/jacktest/EnableShiftRegister.fir
@@ -9,16 +9,16 @@ circuit EnableShiftRegister :
     input shift : UInt<1>
     
     reg r0 : UInt<4>,clk,reset
-    onreset r0 := UInt<4>(0)
+    onreset r0 <= UInt<4>(0)
     reg r1 : UInt<4>,clk,reset
-    onreset r1 := UInt<4>(0)
+    onreset r1 <= UInt<4>(0)
     reg r2 : UInt<4>,clk,reset
-    onreset r2 := UInt<4>(0)
+    onreset r2 <= UInt<4>(0)
     reg r3 : UInt<4>,clk,reset
-    onreset r3 := UInt<4>(0)
+    onreset r3 <= UInt<4>(0)
     when shift : 
-      r0 := in
-      r1 := r0
-      r2 := r1
-      r3 := r2
-    out := r3
+      r0 <= in
+      r1 <= r0
+      r2 <= r1
+      r3 <= r2
+    out <= r3