diff options
| author | Adam Izraelevitz | 2016-08-15 10:32:41 -0700 |
|---|---|---|
| committer | GitHub | 2016-08-15 10:32:41 -0700 |
| commit | bebd04c4c68c320b2b72325e348c726dc33beae6 (patch) | |
| tree | 69f6d4da577977cc7ff428b0545bb4735507aad0 /test/passes/jacktest/Counter.fir | |
| parent | cca37c46fc0848f5dbf5f95ba60755ed6d60712b (diff) | |
Remove stanza (#231)
* Removed stanza implementation/tests.
In the future we can move the stanza tests over, but for now they should
be deleted.
* Added back integration .fir files
* Added Makefile to give Travis hooks
* Added firrtl script (was ignored before)
Diffstat (limited to 'test/passes/jacktest/Counter.fir')
| -rw-r--r-- | test/passes/jacktest/Counter.fir | 18 |
1 files changed, 0 insertions, 18 deletions
diff --git a/test/passes/jacktest/Counter.fir b/test/passes/jacktest/Counter.fir deleted file mode 100644 index 266c1849..00000000 --- a/test/passes/jacktest/Counter.fir +++ /dev/null @@ -1,18 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit Counter : - module Counter : - input inc : UInt<1> - input clk : Clock - input reset : UInt<1> - output tot : UInt<8> - input amt : UInt<4> - - reg T_13 : UInt<8>,clk with : - reset => (reset,UInt<8>(0)) - when inc : - node T_14 = tail(add(T_13, amt),1) - node T_15 = gt(T_14, UInt<8>(255)) - node T_16 = mux(T_15, UInt<1>(0), T_14) - T_13 <= T_16 - tot <= T_13 |