New memory works with verilog. Slowly changing tests and fixing bugs.

Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables

1 files changed, 5 insertions, 5 deletions

diff --git a/test/passes/jacktest/ComplexAssign.fir b/test/passes/jacktest/ComplexAssign.fir
index e3858765..9ce51652 100644
--- a/test/passes/jacktest/ComplexAssign.fir
+++ b/test/passes/jacktest/ComplexAssign.fir
@@ -7,9 +7,9 @@ circuit ComplexAssign :
     input e : UInt<1>
     when e : 
       wire T_18 : {re : UInt<10>, im : UInt<10>}
-      T_18 := in
-      out.re := T_18.re
-      out.im := T_18.im
+      T_18 <= in
+      out.re <= T_18.re
+      out.im <= T_18.im
     else : 
-      out.re := UInt<1>(0)
-      out.im := UInt<1>(0)
+      out.re <= UInt<1>(0)
+      out.im <= UInt<1>(0)