diff options
| author | azidar | 2015-04-17 10:59:32 -0700 |
|---|---|---|
| committer | azidar | 2015-04-17 10:59:32 -0700 |
| commit | 01fa067fe52081463222110b957053734e357f79 (patch) | |
| tree | e54db5f543c4c9a84e6b120468c4008a4edac8d0 /test/passes/expand-connect-indexed/bundle-vecs.fir | |
| parent | 06ff7f7dddcb479d9d4d775a55cbb18d873b35b9 (diff) | |
Fixed bug in primop lowering during type inference. Added reduce instructions and renamed concat -> cat, equal -> eq, and added neq and neg
Diffstat (limited to 'test/passes/expand-connect-indexed/bundle-vecs.fir')
| -rw-r--r-- | test/passes/expand-connect-indexed/bundle-vecs.fir | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/test/passes/expand-connect-indexed/bundle-vecs.fir b/test/passes/expand-connect-indexed/bundle-vecs.fir index f3754a32..e00dd9c2 100644 --- a/test/passes/expand-connect-indexed/bundle-vecs.fir +++ b/test/passes/expand-connect-indexed/bundle-vecs.fir @@ -16,10 +16,10 @@ circuit top : ; CHECK: wire b$x : UInt(32) ; CHECK: wire b$y : UInt(32) ; CHECK: b$x := a$0$x - ; CHECK: when equal-uu(i, UInt(1)) : + ; CHECK: when eq-uu(i, UInt(1)) : ; CHECK: b$x := a$1$x ; CHECK: a$0$y := b$y - ; CHECK: when equal-uu(i, UInt(1)) : + ; CHECK: when eq-uu(i, UInt(1)) : ; CHECK: a$1$y := b$y j := b |