Remove stanza (#231)

* Removed stanza implementation/tests.

In the future we can move the stanza tests over, but for now they should
be deleted.

* Added back integration .fir files

* Added Makefile to give Travis hooks

* Added firrtl script (was ignored before)

4 files changed, 0 insertions, 123 deletions

diff --git a/test/passes/expand-accessors/accessor-mem.fir b/test/passes/expand-accessors/accessor-mem.fir
deleted file mode 100644
index ce1d8da3..00000000
--- a/test/passes/expand-accessors/accessor-mem.fir
+++ /dev/null
@@ -1,36 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-
-circuit top :
-   module top :
-      input clk : Clock
-      wire i : UInt<4>
-      wire j : UInt<32>
-      wire z : UInt<32>
-      i <= UInt(1)
-      mem m : 
-         data-type => UInt<32>[2]
-         depth => 2
-         reader => a
-         writer => x
-         read-latency => 0
-         write-latency => 1
-      m.a.addr <= i
-      m.a.clk <= clk
-      m.a.en <= UInt(1)
-      m.x.addr <= i
-      m.x.clk <= clk
-      m.x.en <= UInt(1)
-      m.x.mask[0] <= UInt(1)
-      m.x.mask[1] <= UInt(1)
-      wire b : UInt<32>[2]
-      b <= m.a.data
-      node c = b[i]
-      z <= j
-      j <= c
-      wire y : UInt<32>[2]
-      y[0] <= UInt(1)
-      y[1] <= UInt(1)
-      m.x.data <= y
-      y[i] <= z
-
-; CHECK: Done!
diff --git a/test/passes/expand-accessors/accessor-vec.fir b/test/passes/expand-accessors/accessor-vec.fir
deleted file mode 100644
index 8b4b7eb8..00000000
--- a/test/passes/expand-accessors/accessor-vec.fir
+++ /dev/null
@@ -1,53 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-
-circuit top :
-   module top :
-      wire m : UInt<32>[2][2][2]
-      wire a : UInt<32>[2][2]
-      wire b : UInt<32>[2]
-      wire c : UInt<32>
-      wire i : UInt
-      wire j : UInt
-      m[0][0][0] <= UInt(1)
-      m[1][0][0] <= UInt(1)
-      m[0][1][0] <= UInt(1)
-      m[1][1][0] <= UInt(1)
-      m[0][0][1] <= UInt(1)
-      m[1][0][1] <= UInt(1)
-      m[0][1][1] <= UInt(1)
-      m[1][1][1] <= UInt(1)
-      i <= UInt(1)
-      a <= m[i]
-      b <= a[i]
-      c <= b[i]
-      j <= c
-
-      wire x : UInt<32>[2][2]
-      wire y : UInt<32>[2]
-      wire z : UInt<32>
-      x[0][0] <= UInt(1)
-      x[1][0] <= UInt(1)
-      x[0][1] <= UInt(1)
-      x[1][1] <= UInt(1)
-      y[0] <= UInt(1)
-      y[1] <= UInt(1)
-      m[i] <= x
-      x[i] <= y
-      y[i] <= z
-      z <= j
-
-      wire p : {n : UInt<32>[2]}
-      p.n[0] <= UInt(1)
-      p.n[1] <= UInt(1)
-      wire q : UInt<32>
-      p.n[i] <= q
-      q <= j
-
-      wire r : {m : UInt<32>}[2]
-      r[0].m <= UInt(1)
-      r[1].m <= UInt(1)
-      wire s : { m : UInt<32>}
-      s <= r[i] 
-      j <= s.m
-
-; CHECK: Done!
diff --git a/test/passes/expand-accessors/simple.fir b/test/passes/expand-accessors/simple.fir
deleted file mode 100644
index b595fc4c..00000000
--- a/test/passes/expand-accessors/simple.fir
+++ /dev/null
@@ -1,16 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-
-;CHECK: Done!
-circuit top :
-   module top :
-      output o : UInt
-      wire m : UInt<32>[2]
-      wire i : UInt
-      m[0] <= UInt("h1")
-      m[1] <= UInt("h1")
-      i <= UInt("h1")
-      wire a : UInt<32>
-      a <= m[i]
-      o <= a
-
-
diff --git a/test/passes/expand-accessors/simple2.fir b/test/passes/expand-accessors/simple2.fir
deleted file mode 100644
index a7d8258d..00000000
--- a/test/passes/expand-accessors/simple2.fir
+++ /dev/null
@@ -1,18 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-
-;CHECK: Done!
-circuit top :
-   module top :
-      output o1 : UInt
-      output o2 : UInt
-      wire m : UInt<32>[2]
-      wire i : UInt
-      m[0] <= UInt("h1")
-      m[1] <= UInt("h1")
-      i <= UInt("h1")
-      wire a : UInt<32>
-      a <= m[i]
-      o1 <= a
-      o2 <= a
-
-