diff options
| author | Adam Izraelevitz | 2016-08-15 10:32:41 -0700 |
|---|---|---|
| committer | GitHub | 2016-08-15 10:32:41 -0700 |
| commit | bebd04c4c68c320b2b72325e348c726dc33beae6 (patch) | |
| tree | 69f6d4da577977cc7ff428b0545bb4735507aad0 /test/passes/const-prop | |
| parent | cca37c46fc0848f5dbf5f95ba60755ed6d60712b (diff) | |
Remove stanza (#231)
* Removed stanza implementation/tests.
In the future we can move the stanza tests over, but for now they should
be deleted.
* Added back integration .fir files
* Added Makefile to give Travis hooks
* Added firrtl script (was ignored before)
Diffstat (limited to 'test/passes/const-prop')
| -rw-r--r-- | test/passes/const-prop/bits.fir | 11 | ||||
| -rw-r--r-- | test/passes/const-prop/rsh.fir | 14 |
2 files changed, 0 insertions, 25 deletions
diff --git a/test/passes/const-prop/bits.fir b/test/passes/const-prop/bits.fir deleted file mode 100644 index 74aa19de..00000000 --- a/test/passes/const-prop/bits.fir +++ /dev/null @@ -1,11 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Constant Propagation -;CHECK: node x = UInt<3>("h7") -;CHECK: Finished Constant Propagation - -circuit top : - module top : - output out : UInt - node x = bits(UInt(127),2,0) - out <= x diff --git a/test/passes/const-prop/rsh.fir b/test/passes/const-prop/rsh.fir deleted file mode 100644 index 5ed8b1be..00000000 --- a/test/passes/const-prop/rsh.fir +++ /dev/null @@ -1,14 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Constant Propagation -;CHECK: x <= UInt<5>("h1f") -;CHECK: y <= SInt<6>("h20") -;CHECK: Finished Constant Propagation - -circuit top : - module top : - output x : UInt - output y : SInt - x <= shr(UInt(127),2) - y <= shr(SInt(-128),2) - |