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authorAdam Izraelevitz2016-08-15 10:32:41 -0700
committerGitHub2016-08-15 10:32:41 -0700
commitbebd04c4c68c320b2b72325e348c726dc33beae6 (patch)
tree69f6d4da577977cc7ff428b0545bb4735507aad0 /test/features/ValidIf.fir
parentcca37c46fc0848f5dbf5f95ba60755ed6d60712b (diff)
Remove stanza (#231)
* Removed stanza implementation/tests. In the future we can move the stanza tests over, but for now they should be deleted. * Added back integration .fir files * Added Makefile to give Travis hooks * Added firrtl script (was ignored before)
Diffstat (limited to 'test/features/ValidIf.fir')
-rw-r--r--test/features/ValidIf.fir21
1 files changed, 0 insertions, 21 deletions
diff --git a/test/features/ValidIf.fir b/test/features/ValidIf.fir
deleted file mode 100644
index 70c69313..00000000
--- a/test/features/ValidIf.fir
+++ /dev/null
@@ -1,21 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-circuit Top :
- module Top :
- input clk : Clock
- input reset : UInt<1>
- input a : { w : UInt<42>, x : UInt<30>}[2]
- input b : { w : UInt<42>, x : UInt<30>}[2]
- input p: UInt<1>
- input q: UInt<1>
- output c : { w : UInt<42>, x : UInt<30>}[2]
- output d : { w : UInt<42>, x : UInt<30>}[2]
-
- c is invalid
- when p :
- when q :
- c <= a
- else :
- c <= b
- d <= validif(p,b)
-
-;CHECK: Done!