diff options
| author | azidar | 2015-12-10 12:27:56 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | 0246ab2479724fb0118bb7a25577c71e2a038223 (patch) | |
| tree | e3a5aa22a3712d28b5b094580cd50babd6520e2f /test/features/TwoClocks.fir | |
| parent | be78d49aa01c097978f69a3b022acb2047fdf438 (diff) | |
WIP, hit semantic bug in WSubAccess
Diffstat (limited to 'test/features/TwoClocks.fir')
| -rw-r--r-- | test/features/TwoClocks.fir | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/test/features/TwoClocks.fir b/test/features/TwoClocks.fir index f68a2769..6562d3e1 100644 --- a/test/features/TwoClocks.fir +++ b/test/features/TwoClocks.fir @@ -5,15 +5,14 @@ circuit Top : input clk2 : Clock input reset1 : UInt<1> input reset2 : UInt<1> - reg src : UInt<10>, clk1, reset1 - reg sink : UInt<10>, clk2, reset2 + reg src : UInt<10>, clk1, reset1, UInt(0) + reg sink : UInt<10>, clk2, reset2, UInt(0) - onreset src <= UInt(0) src <= addw(src,UInt(1)) - reg sync_A : UInt<10>, clk2, reset2 + reg sync_A : UInt<10>, clk2, reset2, UInt(0) sync_A <= src - reg sync_B : UInt<10>, clk2, reset2 + reg sync_B : UInt<10>, clk2, reset2, UInt(0) sync_B <= sync_A sink <= sync_B |