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authorAdam Izraelevitz2016-08-15 10:32:41 -0700
committerGitHub2016-08-15 10:32:41 -0700
commitbebd04c4c68c320b2b72325e348c726dc33beae6 (patch)
tree69f6d4da577977cc7ff428b0545bb4735507aad0 /test/features/Stop.fir
parentcca37c46fc0848f5dbf5f95ba60755ed6d60712b (diff)
Remove stanza (#231)
* Removed stanza implementation/tests. In the future we can move the stanza tests over, but for now they should be deleted. * Added back integration .fir files * Added Makefile to give Travis hooks * Added firrtl script (was ignored before)
Diffstat (limited to 'test/features/Stop.fir')
-rw-r--r--test/features/Stop.fir20
1 files changed, 0 insertions, 20 deletions
diff --git a/test/features/Stop.fir b/test/features/Stop.fir
deleted file mode 100644
index 888da3d7..00000000
--- a/test/features/Stop.fir
+++ /dev/null
@@ -1,20 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-
-;CHECK: Expand Whens
-
-circuit Top :
- module Top :
- input p : UInt<1>
- input q : UInt<1>
- input clk : Clock
- when p :
- stop(clk,UInt(1),0)
- when q :
- stop(clk,UInt(1),1)
- stop(clk,UInt(1),3)
-
-;CHECK: stop(clk, p, 0)
-;CHECK: stop(clk, q, 1)
-;CHECK: stop(clk, UInt<1>("h1"), 3)
-;CHECK: Done!
-