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authorAdam Izraelevitz2016-08-15 10:32:41 -0700
committerGitHub2016-08-15 10:32:41 -0700
commitbebd04c4c68c320b2b72325e348c726dc33beae6 (patch)
tree69f6d4da577977cc7ff428b0545bb4735507aad0 /test/features/MuxNodeExamples.fir
parentcca37c46fc0848f5dbf5f95ba60755ed6d60712b (diff)
Remove stanza (#231)
* Removed stanza implementation/tests. In the future we can move the stanza tests over, but for now they should be deleted. * Added back integration .fir files * Added Makefile to give Travis hooks * Added firrtl script (was ignored before)
Diffstat (limited to 'test/features/MuxNodeExamples.fir')
-rw-r--r--test/features/MuxNodeExamples.fir28
1 files changed, 0 insertions, 28 deletions
diff --git a/test/features/MuxNodeExamples.fir b/test/features/MuxNodeExamples.fir
deleted file mode 100644
index 07fa16b4..00000000
--- a/test/features/MuxNodeExamples.fir
+++ /dev/null
@@ -1,28 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-;CHECK: Expand Connects
-circuit Top :
- module Top :
- input a : {f:UInt<3>[3], flip g:UInt<3>[3]}[2]
- input b : {f:UInt<3>[3], flip g:UInt<3>[3]}[2]
- input p : UInt<1>
- input i : UInt<1>
- b[0].g[0] <= UInt(0)
- b[0].g[1] <= UInt(0)
- b[0].g[2] <= UInt(0)
- b[1].g[0] <= UInt(0)
- b[1].g[1] <= UInt(0)
- b[1].g[2] <= UInt(0)
- a[0].g[0] <= UInt(0)
- a[0].g[1] <= UInt(0)
- a[0].g[2] <= UInt(0)
- a[1].g[0] <= UInt(0)
- a[1].g[1] <= UInt(0)
- a[1].g[2] <= UInt(0)
- node x = mux(p,a[i].f,b[i].f)
-
-
-
-;CHECK: Finished Expand Connects
-;CHECK: Done!
-
-