diff options
| author | azidar | 2015-12-09 18:31:45 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | be78d49aa01c097978f69a3b022acb2047fdf438 (patch) | |
| tree | 76dc4b32b5e6861938404ebb4d124ca5b87d13a5 /test/features/Link.fir | |
| parent | c427b31a1ef8361b643d5f7435aeb42472dfe626 (diff) | |
New memory works with verilog. Slowly changing tests and fixing bugs.
Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
Diffstat (limited to 'test/features/Link.fir')
| -rw-r--r-- | test/features/Link.fir | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/test/features/Link.fir b/test/features/Link.fir index 040ac2c5..57fb8605 100644 --- a/test/features/Link.fir +++ b/test/features/Link.fir @@ -1,5 +1,5 @@ ; RUN: firrtl -i %s -m %S/Queue.fir -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Lower To Ground +;CHECK: Done! circuit Top : module Top : input clk : Clock @@ -7,8 +7,8 @@ circuit Top : output out : UInt<10> inst q of Queue - q.clk := clk - q.reset := reset - q.in := UInt(1) - out := q.out + q.clk <= clk + q.reset <= reset + q.in <= UInt(1) + out <= q.out |