New memory works with verilog. Slowly changing tests and fixing bugs.

Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables

1 files changed, 12 insertions, 12 deletions

diff --git a/test/features/InitializeVec.fir b/test/features/InitializeVec.fir
index 0aa28835..ef6400a0 100644
--- a/test/features/InitializeVec.fir
+++ b/test/features/InitializeVec.fir
@@ -6,17 +6,17 @@ circuit Tst :
     input in : {valid : UInt<1>, flip ready : UInt<1>, bits : UInt<8>}
     output outs : {valid : UInt<1>, flip ready : UInt<1>, bits : UInt<8>}[4]
     
-    in.ready := UInt<1>(1)
-    outs[0].valid := UInt<1>(0)
-    outs[0].bits := UInt<1>(0)
-    outs[1].valid := UInt<1>(0)
-    outs[1].bits := UInt<1>(0)
-    outs[2].valid := UInt<1>(0)
-    outs[2].bits := UInt<1>(0)
-    outs[3].valid := UInt<1>(0)
-    outs[3].bits := UInt<1>(0)
-    in.ready := UInt<1>(1)
+    in.ready <= UInt<1>(1)
+    outs[0].valid <= UInt<1>(0)
+    outs[0].bits <= UInt<1>(0)
+    outs[1].valid <= UInt<1>(0)
+    outs[1].bits <= UInt<1>(0)
+    outs[2].valid <= UInt<1>(0)
+    outs[2].bits <= UInt<1>(0)
+    outs[3].valid <= UInt<1>(0)
+    outs[3].bits <= UInt<1>(0)
+    in.ready <= UInt<1>(1)
     infer accessor out = outs[in.bits]
     when out.ready : 
-      out.bits := UInt<7>(99)
-      out.valid := UInt<1>(1)
+      out.bits <= UInt<7>(99)
+      out.valid <= UInt<1>(1)