diff options
| author | azidar | 2015-12-09 18:31:45 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | be78d49aa01c097978f69a3b022acb2047fdf438 (patch) | |
| tree | 76dc4b32b5e6861938404ebb4d124ca5b87d13a5 /test/errors/high-form/RemoveChar.fir | |
| parent | c427b31a1ef8361b643d5f7435aeb42472dfe626 (diff) | |
New memory works with verilog. Slowly changing tests and fixing bugs.
Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
Diffstat (limited to 'test/errors/high-form/RemoveChar.fir')
| -rw-r--r-- | test/errors/high-form/RemoveChar.fir | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/test/errors/high-form/RemoveChar.fir b/test/errors/high-form/RemoveChar.fir index 74c4a092..9341468c 100644 --- a/test/errors/high-form/RemoveChar.fir +++ b/test/errors/high-form/RemoveChar.fir @@ -4,9 +4,9 @@ circuit Top : module Top : wire x_1 : UInt<1> - x_1 := UInt(1) + x_1 <= UInt(1) wire x : UInt<1> - x := addw(addw(UInt(1),UInt(1)),UInt(1)) + x <= addw(addw(UInt(1),UInt(1)),UInt(1)) |