New memory works with verilog. Slowly changing tests and fixing bugs.

Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables

6 files changed, 25 insertions, 25 deletions

diff --git a/test/errors/high-form/InvalidLOC.fir b/test/errors/high-form/InvalidLOC.fir
index a0a3cea9..8329cc02 100644
--- a/test/errors/high-form/InvalidLOC.fir
+++ b/test/errors/high-form/InvalidLOC.fir
@@ -6,7 +6,7 @@
 circuit Top :
   module Top :
     wire x : UInt
-    add(x,x) := UInt(1)
-    UInt(1) := UInt(1)
-    SInt(1) := UInt(1)
+    add(x,x) <= UInt(1)
+    UInt(1) <= UInt(1)
+    SInt(1) <= UInt(1)
 
diff --git a/test/errors/high-form/InvalidSubexp.fir b/test/errors/high-form/InvalidSubexp.fir
index 07f529d2..23c155e2 100644
--- a/test/errors/high-form/InvalidSubexp.fir
+++ b/test/errors/high-form/InvalidSubexp.fir
@@ -5,5 +5,5 @@
 circuit Top :
   module Top :
     wire x : UInt<4>
-    add(x,x)[10] := UInt(1)
-    add(x,x).x := UInt(1)
+    add(x,x)[10] <= UInt(1)
+    add(x,x).x <= UInt(1)
diff --git a/test/errors/high-form/NegUInt.fir b/test/errors/high-form/NegUInt.fir
index 35f25013..8249f791 100644
--- a/test/errors/high-form/NegUInt.fir
+++ b/test/errors/high-form/NegUInt.fir
@@ -4,4 +4,4 @@
 circuit Top :
   module Top :
     wire x : UInt<4>
-    x := UInt(-2)
+    x <= UInt(-2)
diff --git a/test/errors/high-form/RemoveChar.fir b/test/errors/high-form/RemoveChar.fir
index 74c4a092..9341468c 100644
--- a/test/errors/high-form/RemoveChar.fir
+++ b/test/errors/high-form/RemoveChar.fir
@@ -4,9 +4,9 @@
 circuit Top :
   module Top :
     wire x_1 : UInt<1>
-    x_1 := UInt(1)
+    x_1 <= UInt(1)
     wire x : UInt<1>
-    x := addw(addw(UInt(1),UInt(1)),UInt(1))
+    x <= addw(addw(UInt(1),UInt(1)),UInt(1))
 
 
 
diff --git a/test/errors/high-form/RemoveScope.fir b/test/errors/high-form/RemoveScope.fir
index 16498fd8..63dfb4de 100644
--- a/test/errors/high-form/RemoveScope.fir
+++ b/test/errors/high-form/RemoveScope.fir
@@ -8,11 +8,11 @@ circuit Top :
     node p = UInt(1)
     when p :
        wire x : UInt<1>
-       x := UInt(1)
+       x <= UInt(1)
        node y = add(x,UInt(1))
     else :
        wire x : UInt<1>
-       x := UInt(1)
+       x <= UInt(1)
        node z = add(x,UInt(1))
-    x := UInt(1)
+    x <= UInt(1)
     node w = add(x,UInt(1))
diff --git a/test/errors/high-form/SpecialChars.fir b/test/errors/high-form/SpecialChars.fir
index 99df9143..85911c06 100644
--- a/test/errors/high-form/SpecialChars.fir
+++ b/test/errors/high-form/SpecialChars.fir
@@ -4,32 +4,32 @@
 circuit Top :
   module Top :
     wire x : UInt<1>
-    x := UInt(1)
+    x <= UInt(1)
     wire x~y : UInt<2>
-    x~y := UInt(1)
+    x~y <= UInt(1)
     wire x!y : UInt<2>
-    x!y := UInt(1)
+    x!y <= UInt(1)
     wire x@y : UInt<2>
-    x@y := UInt(1)
+    x@y <= UInt(1)
     wire x#y : UInt<2>
-    x#y := UInt(1)
+    x#y <= UInt(1)
     wire x%y : UInt<2>
-    x%y := UInt(1)
+    x%y <= UInt(1)
     wire x^y : UInt<2>
-    x^y := UInt(1)
+    x^y <= UInt(1)
     wire x*y : UInt<2>
-    x*y := UInt(1)
+    x*y <= UInt(1)
     wire x-y : UInt<2>
-    x-y := UInt(1)
+    x-y <= UInt(1)
     wire x_y : UInt<2>
-    x_y := UInt(1)
+    x_y <= UInt(1)
     wire x+y : UInt<2>
-    x+y := UInt(1)
+    x+y <= UInt(1)
     wire x=y : UInt<2>
-    x=y := UInt(1)
+    x=y <= UInt(1)
     wire x?y : UInt<2>
-    x?y := UInt(1)
+    x?y <= UInt(1)
     wire x/y : UInt<2>
-    x/y := UInt(1)
+    x/y <= UInt(1)