diff options
| author | azidar | 2015-12-09 18:31:45 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | be78d49aa01c097978f69a3b022acb2047fdf438 (patch) | |
| tree | 76dc4b32b5e6861938404ebb4d124ca5b87d13a5 /test/errors/high-form/InvalidLOC.fir | |
| parent | c427b31a1ef8361b643d5f7435aeb42472dfe626 (diff) | |
New memory works with verilog. Slowly changing tests and fixing bugs.
Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
Diffstat (limited to 'test/errors/high-form/InvalidLOC.fir')
| -rw-r--r-- | test/errors/high-form/InvalidLOC.fir | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/test/errors/high-form/InvalidLOC.fir b/test/errors/high-form/InvalidLOC.fir index a0a3cea9..8329cc02 100644 --- a/test/errors/high-form/InvalidLOC.fir +++ b/test/errors/high-form/InvalidLOC.fir @@ -6,7 +6,7 @@ circuit Top : module Top : wire x : UInt - add(x,x) := UInt(1) - UInt(1) := UInt(1) - SInt(1) := UInt(1) + add(x,x) <= UInt(1) + UInt(1) <= UInt(1) + SInt(1) <= UInt(1) |