diff options
| author | azidar | 2015-06-02 10:41:27 -0700 |
|---|---|---|
| committer | azidar | 2015-06-02 10:41:27 -0700 |
| commit | f8f9de58dbba5e53193246a5fd2145dfe6537e10 (patch) | |
| tree | dedcbc9b1dc7709d6efbc2dce3c5f36303f2a990 /test/chisel3/Tile.fir | |
| parent | 8fc826a2770f46d63d8d7b1bccf14d2bf6e6b7cd (diff) | |
Added sequential/combinational memories. Started debugging verilog backend. Added Long support so UInt(LARGENUMBER) works
Diffstat (limited to 'test/chisel3/Tile.fir')
| -rw-r--r-- | test/chisel3/Tile.fir | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/test/chisel3/Tile.fir b/test/chisel3/Tile.fir index eeec18ee..01d78cd0 100644 --- a/test/chisel3/Tile.fir +++ b/test/chisel3/Tile.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s ;CHECK: Done! circuit Tile : @@ -97,7 +97,7 @@ circuit Tile : input waddr : UInt<5> input wdata : UInt<32> - mem regs : UInt<32>[32] + cmem regs : UInt<32>[32] node T_1616 = eq(raddr1, UInt<1>(0)) node T_1617 = bit-not(T_1616) accessor T_1618 = regs[raddr1] @@ -1026,7 +1026,7 @@ circuit Tile : input enq : {valid : UInt<1>, flip ready : UInt<1>, bits : {mask : UInt<4>, tag : UInt<5>, rw : UInt<1>, addr : UInt<32>}} output deq : {valid : UInt<1>, flip ready : UInt<1>, bits : {mask : UInt<4>, tag : UInt<5>, rw : UInt<1>, addr : UInt<32>}} - mem ram : {mask : UInt<4>, tag : UInt<5>, rw : UInt<1>, addr : UInt<32>}[4] + cmem ram : {mask : UInt<4>, tag : UInt<5>, rw : UInt<1>, addr : UInt<32>}[4] reg T_2381 : UInt<2> on-reset T_2381 := UInt<2>(0) reg T_2382 : UInt<2> @@ -1089,7 +1089,7 @@ circuit Tile : input enq : {valid : UInt<1>, flip ready : UInt<1>, bits : {data : UInt<32>}} output deq : {valid : UInt<1>, flip ready : UInt<1>, bits : {data : UInt<32>}} - mem ram : {data : UInt<32>}[4] + cmem ram : {data : UInt<32>}[4] reg T_2412 : UInt<2> on-reset T_2412 := UInt<2>(0) reg T_2413 : UInt<2> |