diff options
| author | azidar | 2015-06-02 10:41:27 -0700 |
|---|---|---|
| committer | azidar | 2015-06-02 10:41:27 -0700 |
| commit | f8f9de58dbba5e53193246a5fd2145dfe6537e10 (patch) | |
| tree | dedcbc9b1dc7709d6efbc2dce3c5f36303f2a990 /test/chisel3/Tbl.fir | |
| parent | 8fc826a2770f46d63d8d7b1bccf14d2bf6e6b7cd (diff) | |
Added sequential/combinational memories. Started debugging verilog backend. Added Long support so UInt(LARGENUMBER) works
Diffstat (limited to 'test/chisel3/Tbl.fir')
| -rw-r--r-- | test/chisel3/Tbl.fir | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/test/chisel3/Tbl.fir b/test/chisel3/Tbl.fir index d64916f1..e7397f61 100644 --- a/test/chisel3/Tbl.fir +++ b/test/chisel3/Tbl.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s ;CHECK: Done! circuit Tbl : @@ -8,7 +8,7 @@ circuit Tbl : output o : UInt<16> input we : UInt<1> - mem m : UInt<10>[256] + cmem m : UInt<10>[256] o := UInt<1>(0) when we : accessor T_13 = m[i] |