diff options
| author | azidar | 2015-05-26 17:33:40 -0700 |
|---|---|---|
| committer | azidar | 2015-05-26 17:33:40 -0700 |
| commit | cf80ff9c83c2fedd42ec186a3e342520c89f91ab (patch) | |
| tree | ebbf3455b91e8840d49057754585d567dacea384 /test/chisel3/ModuleWire.fir | |
| parent | eb125225cb96875f31a9af0db187406782b75223 (diff) | |
Added <>. Added additional checks for primops. Added new chisel3 files.
Diffstat (limited to 'test/chisel3/ModuleWire.fir')
| -rw-r--r-- | test/chisel3/ModuleWire.fir | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/test/chisel3/ModuleWire.fir b/test/chisel3/ModuleWire.fir new file mode 100644 index 00000000..fefe42bd --- /dev/null +++ b/test/chisel3/ModuleWire.fir @@ -0,0 +1,17 @@ +; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +;CHECK: Done! + +circuit ModuleWire : + module Inc : + input in : UInt<32> + output out : UInt<32> + + node T_12 = add-wrap(in, UInt<1>(1)) + out := T_12 + module ModuleWire : + input in : UInt<32> + output out : UInt<32> + + inst T_13 of Inc + T_13.in := in + out := T_13.out |