diff options
| author | jackbackrack | 2015-05-01 12:13:32 -0700 |
|---|---|---|
| committer | jackbackrack | 2015-05-01 12:13:32 -0700 |
| commit | 9eba69c6a6a756d0d9fbd6063c8a2e4d77aae570 (patch) | |
| tree | e9c3edbc813a862674962e3a69c808b0b8215d8a /test/chisel3/ModuleVec.fir | |
| parent | e3bf1ddc8491557e9cff90a6d85725765e733c35 (diff) | |
| parent | 0a00a6aaa846b695a7a750cf40079d56a9bb94d6 (diff) | |
merge
Diffstat (limited to 'test/chisel3/ModuleVec.fir')
| -rw-r--r-- | test/chisel3/ModuleVec.fir | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/test/chisel3/ModuleVec.fir b/test/chisel3/ModuleVec.fir index a4617267..a53c9549 100644 --- a/test/chisel3/ModuleVec.fir +++ b/test/chisel3/ModuleVec.fir @@ -21,9 +21,9 @@ circuit ModuleVec : inst T_37 of PlusOne inst T_38 of PlusOne_25 - wire pluses : { in : UInt<32>, flip out : UInt<32>}[2] - pluses[0] := Pad(T_37,?) - pluses[1] := Pad(T_38,?) + wire pluses : { flip in : UInt<32>, out : UInt<32>}[2] + pluses[0] := T_37 + pluses[1] := T_38 pluses[0].in := Pad(ins[0],?) outs[0] := Pad(pluses[0].out,?) pluses[1].in := Pad(ins[1],?) |